CN100511149C - Logic emulation testing system and method - Google Patents
Logic emulation testing system and method Download PDFInfo
- Publication number
- CN100511149C CN100511149C CNB031228852A CN03122885A CN100511149C CN 100511149 C CN100511149 C CN 100511149C CN B031228852 A CNB031228852 A CN B031228852A CN 03122885 A CN03122885 A CN 03122885A CN 100511149 C CN100511149 C CN 100511149C
- Authority
- CN
- China
- Prior art keywords
- module
- message
- analysis
- excited
- stimulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The logically simulation test system completes the test of logic to be tested in the simulator module by means of the user's script file. The system includes control module for interpreting and executing the main script file and controlling the other modules; message data base module for the access, search, display, saving and loading of the message data; CPU configuration module for data write/read and interruption; several excitation modules for constituting excitation message; simulator module for simulating and testing the input excitation message and outputting; and several analysis modules for analyzing tested message and outputting analysis result. The present invention has simple test codes the user edits in TCL scrip, no need of compiling the test codes and short simulation system creating time.
Description
Technical field
The present invention relates to the testing of equipment field, relate to a kind of modular logical simulation test macro and method specifically.
Background technology
Nowadays the extensive logic of a large amount of communication classes has obtained using widely, before coming into operation, to carry out emulation testing to the function of the extensive logic of this kind communication class, a large amount of work is to write the test code of being made up of excitation generation function and interpretation of result function during test, tests then.
Existing method of testing mainly is at first to write test code by the tester, then the logic verification system of this test code input non-modularization is finished test.Be illustrated in figure 1 as the present application structured flowchart of the logic verification system that adopts of Zaiq company very widely, it includes three parts: C test code part, interface layer part, general HDL (Hardware Design Language: emulation part hardware design language).
The C test code comprises that partly the user realizes test purpose test case code, the interface function (comprising: TX trial function, RX trial function, cpu test function) of realizing the data transfer exchange, environment control, message accounting storehouse.Test case code call data exchange interface function is realized the transmitting-receiving of data, calls the TX trial function and sends excited data, and the excited data that produces is passed to tested logic; Call the RX trial function and realize Data Receiving, receive the data that tested logical delivery is come, finish the reception data analysis; Call the cpu test function and realize the reading and writing data and the interruption of cpu i/f.The data exchange interface function is the requirement of user according to the specific incentives data layout, the DLL (dynamic link library) that the calling interface layer provides, and coding forms.The message accounting storehouse is used to write down the relevant information of excited message, such as transmitting-receiving port, transmitting-receiving time, message construction data, and sequence of message number etc.The environment control section, the message transmission between the realization module and synchronous, emulator control, Message Record etc.
The interface layer part realizes the exchange of above-mentioned C test code partial data and following HDL emulation partial data, is present in the kernel of this logic verification system, is some DLL (dynamic link library) for the user.
HDL emulation part comprises TX data exchange interface, RX data exchange interface, cpu data Fabric Interface, by the logic of emulation testing.Wherein TX data exchange interface, RX data exchange interface, cpu data Fabric Interface are that the user realizes with the HDL language compilation, be used for becoming clock signal to pass to data-switching, perhaps receive clock signal and convert data to from tested logic by the logic of emulation testing.The module of HDL emulation part also is to realize with the HDL speech encoding, moves the behavior of simulation hardware in the universal emulator software environment.
This logic verification system provides many bottom functions, and such as message data organization definition, message constructed fuction, synchronization mechanism function etc., the tester uses these functions to write the C test code.
Though above-mentioned prior art has reached test code to a certain extent and shared, and has improved testing efficiency, still there are many deficiencies in it.At first owing to be extensive logic item development one a cover test code of communication class, prior art does not form modular assembly, has only provided the bottom function of programming, and the tester has to be familiar with a lot of functions; And test code is with relevant by the logic of emulation, and test code degree of reusing is very low, repeatable very poor; In addition, each functional module does not have clear and definite programming guidance or interface specification, just proposes the general division of labor, and the function of realization is mainly designed according to concrete project demand by the user, so the programing work amount is very big.Secondly very high to logic testing personnel's programming technique requirement, the logic testing personnel are Hardware Engineers usually, are not to be good at very much to software programming, and difficulty and inconvenience that this has more increased the logical simulation test job cause testing efficiency low.
Summary of the invention
Fundamental purpose of the present invention provides the main script file that a kind of tester only need write a small amount of code relevant with logic to be tested, the test code degree of reusing that exists with the solution prior art is low, repeatability is poor, the programing work amount is big and the low inferior problem of testing efficiency, just can finish the modular logical simulation test macro and the method for the test and the analysis of emulation logic automatically.
For achieving the above object, logical simulation test macro of the present invention is finished the test that is included in the logic to be tested in the emulator module by user's main script file, and wherein, this system includes:
Control module is used for explaining and carries out this main script file and control each following module;
The message data library module is used for realizing the storage of message data and reads, retrieves and show, is saved in file and loads from file;
The CPU configuration module is used for realizing data write and interruption;
Several stimulating modules are used for constructing excited message;
Emulator module is used for the excited message of input is finished the simulation process test, and the message after the output test;
Several analysis modules are used for message behind the analytical test, and analysis result is exported;
HDL code module in the described emulator module sends the test and excitation request to control module, this control module is transmitted this test and excitation request to corresponding stimulating module, this stimulating module structure excited message, with the message data information stores to described message data library module, and this excited message is sent to described emulator module, read and handle incoming message by the HDL code module that in emulator module, moves, and the message after the output processing is to corresponding analysis module, this analysis module is analyzed the message after the tested logical process, and analysis result is saved in the message data library module under the control of described CPU configuration module.
Wherein, described stimulating module includes the message constructor that contains the TCL script accordingly.This stimulating module obtains the parameter of selected data stream by the scheduling internal data flow, calls this message constructor again, promptly produces described excited message.
This system also further comprises: be used for further verifying the subscriber authentication module of logic to be tested to the processing of excited message, described stimulating module passes to subscriber authentication module with excited message, obtain the expection result of this message, stimulating module will expect that result is saved in the message data storehouse; The message of described analysis module after with original excited message and test is passed to this subscriber authentication module, and this subscriber authentication module is finished the further checking that logic to be tested is handled excited message, and will verify that the result returns to described analysis module.Described analysis module is finished the analysis to some behaviors of message automatically according to the record data of message in the message store.
Connection between described control module and described stimulating module, analysis module, the CPU configuration module is undertaken by the base class module.And the connection between described subscriber authentication module and described stimulating module, the analysis module is undertaken by the base class module.
In addition, a kind of logical simulation method of testing of the present invention is finished the test that is included in the logic to be tested in the emulator module by user's main script file, and wherein, this method comprises following steps:
Main script file is carried out in a, explanation, sets up stimulating module object and analysis module object according to main script file then, and according to parameter wherein this stimulating module object and analysis module object is configured;
B, emulator module are sent the testing service request, and deliver to this stimulating module object;
C, this stimulating module object are delivered to emulator module according to this testing service request structure excited message with this excited message;
D, emulator module are finished simulation process to this excited message of input according to the hardware behavior of HDL code description, and the message after handling is delivered to corresponding analysis stimulating module object;
E, this analysis module object analysis are somebody's turn to do the message after handling, and analysis result is exported.
Set up stimulating module object and analysis module object among the wherein said step a are meant and set up several corresponding stimulating module object and analysis module objects.
Structure excited message among the described step c is by dispatching the excited data stream in each stimulating module object, call corresponding TCL script again and carry out the message structure, producing described excited message.
Message after this test of analysis among the described step e more specifically comprises:
E1, the message after this test is carried out the analysis of agreement accordance,, then carry out the message reorganization, obtain complete message if be the section message;
E2, this complete message is resolved, extract the insertion label, obtain the message payload;
E3, verify this message payload, obtain analysis result.
Wherein, further comprise among the step e1 of described step e: if the message after this test is the message that logic to be tested is inserted automatically, then by user's aided verification; Otherwise continue.
The present invention is based upon the abundant investigation of tested object and fully analytically, extract the general character of tested object and the general character of authentication policy, thereby design fixing modular assembly, and worked out the intermodule interface standard, make system modular, and can add (or exploitation) new module the later stage and replenish into, and do not need the original module of platform is recompilated.Stimulating module and analysis module are shared between the logic project aspect excitation generation and message analysis easily.The test code that the user writes is fairly simple and size of code is few, and test code adopts the TCL script to write, and does not need compiling.Use designed system of the present invention, the time of building the analogue system input significantly reduces, and makes the tester most of energy mainly can be put in the design of tested entries.
Describe the present invention in detail below in conjunction with the drawings and specific embodiments.
Description of drawings
Fig. 1 is the structured flowchart of existing logic verification system;
Fig. 2 is the structured flowchart of logical simulation test macro of the present invention;
Fig. 3 is the process flow diagram of logical simulation method of testing of the present invention;
Fig. 4 is the exchanges data synoptic diagram between control module of the present invention, stimulating module, the emulator module;
Fig. 5 is the message construction process synoptic diagram of stimulating module of the present invention.
Specific implementation
The structured flowchart of the described logical simulation test macro of the embodiment of the invention as shown in Figure 2, it mainly is made of a control module, a message data library module, a CPU configuration module, a stimulating module, an emulator module, an analysis module and a subscriber authentication module, wherein:
Control module is used for explaining and carries out this main script file and control each following module;
The message data library module is used for realizing the storage of message data and reads, retrieves and show, is saved in file and loads from file;
The CPU configuration module is used for realizing data write and interruption;
Stimulating module is used for constructing excited message;
Emulator module is used for the excited message of input is finished simulation process according to the hardware behavior of HDL code description, and the message after handling is delivered to corresponding analysis module; This emulator module is a simulated environment, uses general third party HDL simulation software, is used for the hardware behavior of emulation HDL code description, and the function that this part realizes is the tested logical process input stimulus of an emulation message, the output response of this logic of emulation.The HDL code comprises tested logic DUV and a plurality of bus interface module BFM.
Analysis module is used for analyzing the message after emulator module is handled, and analysis result is exported;
Subscriber authentication module is used for further verifying the processing of logic to be tested to excited message, for analysis module is realized analyzing automatically some behavior of message providing analysis condition.
Above-mentioned control module, message data library module are basic modules, be changeless, this control module includes the user interface service module that is used for the process user interface operation and is used for the data exchange service module of deal with data exchange request, this user interface service module can be checked statistics and do not influenced the carrying out of emulation in simulation process, this data exchange service module is transmitted to corresponding stimulating module or analysis module (being object module) with data exchange request, and object module produces excitation or handles and receives data; And the CPU configuration module, system provides a basic module to realize read-write and interruption, in the logic testing of reality, the tester adds required function on the basis of this basic module, such as the transmitting-receiving that realizes certain message, dynamic control of implementing according to the logic operation state and to logic or the like.
The message data library module is mainly realized the storage of message accounting data and is read, retrieves and show, is saved in file and from file load.Core is the definition of message accounting data structure, and these record data support stimulating module and analysis module to finish result's automatic analysis.
Stimulating module, analysis module can have a lot of in addition, can add in the later stage.For a logic project testing, multiple different stimulating module and multiple different analysis module are arranged usually, the routine as required entity that dissolves these stimulating modules and analysis module of user gets final product, and present embodiment has only provided the situation of a stimulating module and an analysis module.Can on original module base class, derive from and get final product if develop new excitation or analysis module, but the definition of the base class of these modules mainly is the interface that has defined module that the module that the control module visit later stage adds can be undertaken by the interface of base class module.
Emulator module among Fig. 2 is logic DUV to be tested (Design Under verficaTion)+testbench (test platform)+emulator, belongs to the range of control of emulator; Wherein, logic DUV to be tested is the program of being write out by hardware language VERILOG or VHDL, testbench is mainly by BFM (Bus Bunction Module: bus functional model) form, its function of finishing obtains (behavioral scaling) excited data from stimulating module, the excited data (with respect to the bit flow data) of behavioral scaling is transformed into one group of clock signal (or level signal), passes to DUV; BFM receives the clock signal of DUV output, converts the data of behavioral scaling to, gives analysis module with the data transfer of behavioral scaling.Emulator is explained DUV+testbench, the behavior of emulation logic carried out.
To be the tester oneself write the module that test code is realized according to concrete logic project characteristic to subscriber authentication module, mainly finish with by the relevant checking of emulation logic specific behavior.Such as logic Modification the target MAC (Media Access Control) address of Ethernet message, whether revise correctly needs subscriber authentication module analysis.The indispensable parts that this module can be not be formed as emulation test system, this moment, emulation test system just defined the interface of subscriber authentication module, and as being described below of interface definition: the input original message obtains anticipatory export tabulation and expection copy number; Input original message and message inlet, input receive message and message outlet, are verified message or the error message whether passed through.And the interface of subscriber authentication module and stimulating module and analysis module is a standardized interface, can be by the base class of a subscriber authentication module of definition, for different logic testing projects, the user derives concrete subscriber authentication module on the basis of this base class.The user can be by the script command in the main script file, and the order subscriber authentication module loads joins the table data or realize other function.
Need be clearly, here pass to the message of subscriber authentication module, it all is complete message, the reception message that passes to subscriber authentication module such as the UTOPIA analysis module is the message of the AAL packing forms after cell is recombinated, rather than cell or IP that extracts from AAL PAYLOAD or Ethernet message.
Emulator module equivalence among Fig. 2 is the logic chip that can work, and it can handle the input data, and the output result data.Logic chip has several data input ports and several data outputs, and each data input port and data output all have corresponding BFM butt joint.BFM is the function that realizes that behavioral scaling excited data and sequential level signal are changed mutually, is the interface bridge that connects logic chip and stimulating module and analysis module.Each carries the example of the corresponding stimulating module of BFM of excited data to logic chip, each from logic chip receive data the example of the corresponding analysis module of BFM.Logic chip generally all has cpu i/f, and outer CPU carries out read-write operation by this interface to logic chip, therefore has a BFM to dock with the CPU mouth of logic chip.The outer CPU of CPU configuration module imitation logic chip, many logic chips carry out read-write operation.Basic CPU configuration module is only realized read-write interface, and the user can utilize these interfaces, realizes the complexity control to logic chip.
Logic chip in the present embodiment has own specific Data Input Interface and data output interface, and the type of data-interface has a variety of, and each interface type has all defined a group interface signal and a sequential, such as UTOPIA L1 atm interface, MII interface.The Data Input Interface of each type, logical simulation test macro all need to provide a kind of corresponding stimulating module; The data output interface of each type, logical simulation test macro all need to provide a kind of correspondence analysis module.
Use the logical simulation test macro to carry out must setting up stimulating module example, analysis module example, CPU configuration module example before the logical simulation test, and the parameter that each example is set, it is called configuration operation.The user on the graphical interfaces of logical simulation test macro, selects the stimulating module type to set up the stimulating module example according to the interface type of logic chip, sets up the example of analysis module, the example of CPU module equally.Each example requires the title of input example when setting up, title must be unique, can not bear the same name.
As previously mentioned, the excitation or the example of analysis module be with BFM one to one, has a binding relationship, this binding has a parameter by the title realization in each BFM, the value of this parameter is exactly the title of corresponding instance.After finishing excitation and analysis module, the foundation of CPU module instance, can open the graphical interfaces of each example, carry out parameter configuration.The logical simulation test macro can be with the parameter of each module, and correlation parameters such as the stimulating module example set up of user, analysis module example, CPU configuration module example are preserved into a parameter configuration files.When the logical simulation test macro starts, can load this parameter configuration files, the setting before recovering.
As shown in Figure 3, the described logical simulation test macro of the embodiment of the invention is to realize testing by following step.
The first, explain the main script file of execution, set up stimulating module object and analysis module object according to main script file then, and this stimulating module object and analysis module object are configured according to parameter wherein.
The example of main script file is as follows:
1.Lcfg (cfg_filename)--load configuration data
2.onbreak{--referring to the control module detailed design part of emulation module
3.If{brkmsg＝＝＂note＂}?{resume}else{
(a)Set?result＂error＂
(b) Writechkmsg (result)--information is write the LOG file of special-purpose LOG file and this use-case.
(c) Exit_test--withdraw from
b)}
4.run
5.# change the order of configuration parameter
6...............
7.Run
8.# change the order of configuration parameter
9...............
10.set result[auto_check]--result=＂ ok ＂ or ＂ error ＂
11.# judge whether the result of auto_check checking is correct, the information of writing success or failure is to log file.
12.Writechkmsg (result)--information is write the LOG file of special-purpose LOG file and this use-case.
13.Exit_test--withdraw from
Control module is explained and is carried out above-mentioned script file, the behavior of each module in the steering logic emulation test system.The logical simulation test macro provides many TCL explosion commands, and the user uses these explosion commands and TCL inherent comma to write the emulation script.The all operations of emulation platform can be realized by expansion TCL order.Script file directly is not responsible for setting up excitation and is produced and analyze, but can set up stimulating module object and analysis module object, promptly sets up stimulating module and analysis module, so the code of each script and few.The important point after the emulation logic test execution finishes, can obtain the information whether this test case is passed through, and can preservation information arrive specified file.
In the script onbreak be explained as follows described:
When stimulating module and analysis module reach the upper limit number of user's setting at transmitting-receiving message number, can send message to control module, the rank of this message is " note ".Control module is just carried out the onbreak statement body when receiving message.If stimulating module and analysis module are found mistake when analyzing message, also can send message to control module, the rank of this message is " error ".The user writes the onbreak statement body, can handle these message, and can judge the module instance name of transmission message and concrete message content, thereby carries out related command, and the parameter such as revising certain module perhaps finishes emulation.Onbreak exists " note " after other Message Processing of level, can finish the execution of run order usually, it is returned, so script continues to carry out next bar script sentence.
Being explained as follows that run orders in the script is described:
Run in script order is more special, and it can automatic reception or returns, and it waits for the complete of resume order in the onbreak statement body always.During the run command execution, the services request that BFM initiates to emulation platform can be delivered to control module, and then processed.During non-run command execution, the services request that BFM initiates to emulation platform gets clogged, and the operation of emulator also gets clogged simultaneously.
Being explained as follows that auto_check orders in the script is described:
This order generally is positioned at the rear portion of script, carries out this order when emulation finishes.Whether control module travels through each module instance, calls their auto_check interface function, and each module instance is carried out the internal state inspection, check wrong.
The second, emulator module is sent the testing service request, and delivers to this stimulating module object.
Emulator module is sent the testing service request according to the instruction of control module, and promptly the BFM of testbench sends message request, realizes by calling the PLI interface routine.The PLI interface routine writes the Parameters data structure among Fig. 4 with the parameter that BFM transmits, and initiates request to control module then, waits for the message that this Request Processing is finished again.Be the example that this BFM calls the PLI interface routine below:
$mii_read_pkt(modulename，framegap，tx_frame_len，tx_frame_data)；
As shown in Figure 4, pass through the Parameters data structure swap data between PLI interface routine and the stimulating module (modulename in the following formula), the PLI interface routine is in filling in the message request Parameters data structure after the related data, the interface function that calling system the provides request of sending is (term of execution of this function, the execution of simulation software stops), after the data service module of control module is received this excitation request, control module obtains object module (being the stimulating module example) name from the message request Parameters data structure, thereby obtain the handle of stimulating module example, call the message processing program of stimulating module example then, this stimulating module example is delivered in the request that should encourage.
Three, this stimulating module object writes this excited message in the aforementioned message request Parameters data structure according to this testing service request structure excited message.
Various stimulating modules are similarly on structure excited message mechanism, all are the at first scheduling by convection current, will many stream mix and form excited messages and flow.Usually can will have the sequence of message of certain feature, be defined as a stream.Can be defined as a stream such as the message with identical VLANID, the sequence of message with identical sources MAC Address also can be defined as a stream, perhaps the sequence of message that has certain several attribute simultaneously is defined as a stream.For a stream some attributes (as out of order, bandwidth, time-delay, burst, packet loss rate) can be set, how many time-delay maximums of passing through logics such as all messages that belong to this stream can not surpass.
Secondly a plurality of message flows are converged, promptly form the message that flows to logic to be tested.In logical simulation, in order to produce realistic excited data, we define a plurality of streams usually, (in the parameter configuration interface of stimulating module example, the number of stream and the parameter of each stream are set, these parameters are called the configuration parameter of stimulating module example).When the stimulating module example receives the request of application message, just these streams are dispatched according to certain dispatching algorithm, dispatch a stream, take out the parameter (referring to Fig. 5) that is used for the message structure from this stream, carry out the message structure script that the user writes then, transmit aforesaid message constructing variable simultaneously.The user writes message structure script and is responsible for constructing concrete message, and script must use the message structure order of emulation platform special use in this, and stimulating module just can read the good message of structure, and script executing finishes, and the stimulating module example has just obtained message data.The message that scheduling is come out just can be used as excited message and flows to logic to be tested.Wherein need the scheduling notion that clearly flows: be not the sequence of message that produces stream earlier, then to each bar message flow scheduling, but according to the attribute data that flows, convection current is dispatched, after dispatching out a stream, have the attribute data (employed parameter when being the message structure) of numbering character again according to the part of stream, call the message constructor, produce the message of dispatching out.For example UTOPIA L2 stimulating module has a plurality of subports, and a plurality of streams are arranged in each subport, and this moment, this stimulating module need realize that the scheduling of subport, each subport realize the scheduling of flowing again, and the scheduling of subport and the scheduling of stream have similar part.
The stimulating module of present embodiment includes the message constructor that contains the TCL script accordingly, and this stimulating module calls this message constructor again by the required excited data stream that each stimulating module of scheduling produces, and promptly produces described excited message.More specifically, be illustrated in figure 5 as message construction process synoptic diagram, this stimulating module is dispatched out required excited data stream through dispatching algorithm, and the parameter of taking out stream, produces quiet lotus Payload part, inserts a label in its front portion, and label definition is as follows:
The CRC32 (4 byte) of characteristic (F55F) (2 bytes)+FSN (sequence of message number) (3 byte)+check code (preceding 5 bytes add up and) (1 byte)+payload length (2 byte)+back payload;
Wherein Liu property parameters is in order to support QOS (Quality Of Services: the service quality) test of attribute (as out of order, bandwidth, time-delay, burst, packet loss rate), the user is in the user interface service module of control module or the property parameters of each stream can be set by script command, these parameters (as bandwidth, the burst of customer requirements) will be controlled the scheduling of stream, carry out also can using when the result analyzes automatically these parameters (as checking actual bandwidth, out of order, delay requirement, packet loss rate) at analysis module.
Then its parameter and quiet lotus Payload are partly passed to outside TCL script, return then, promptly obtain required excited message by TCL script message constructed fuction.The TCL code that wherein produces message can adopt following mode to write:
#--------------------------------------------------------
The #port_sn port numbering supposes that the port of numbering 1 and 2 is two MII mouths, sends the Ethernet message to logic
#last_txpkt_sn is the sequence number of message in stream.
#flow_sn is the sequence number of stream in port
#port_sn, last_txpkt_sn, flow_sn are defined as TCL script global variable, and are connected with the interior corresponding global variable of primary module, and the corresponding parameter assignment that stimulating module will flow is given these global variables of primary module.
#------------------------------------------
proc?mii_pkt_build{}{
if($port_sn<3){
The #to_hex explosion command is used for the decimal system parameter with input, forms 16 system character strings, and the character number that returns is by second parameter control.
set?templ[to_hex$last_txpkt_sn6]
set?temp2[to_hex$flow_sn6]
set?dmac$temp2$temp1
set?smac[to_hex$port_sn12]
#create_mac is the message structure order of expansion.Unspecified parameter is according to default structure message.Referring to MII stimulating module service manual.Message after the generation is kept in the overall message buffer of primary module, and stimulating module can read the message of generation from this buffer zone.
create_mac-dmac0x$dmac-smac0x$smac
If # is encapsulated as AAL5 with the message that create_mac produces, then continue:
create_aa15
The #create_aa15 explosion command can be discerned the type of message that create_mac produces, and produces suitable encapsulation.
}
}
#-----------------------------------------------------
Above-mentioned this message building method is very easily for the message of structural anormaly message and multi-layer protocol encapsulation.Stream scheduling and message structure can be made a base class, can derive multiple stimulating module on this basis then, simplify the workload of developing new stimulating module like this.
After message produced, stimulating module was to message data library module logon message relevant information: each parameter, the message generation time used when producing message; Stimulating module also can call the family authentication module, obtains the expection result of message.
After the stimulating module structure is finished excited message, in the message request Parameters data structure, write excited message, PLI interface routine calling system interface function returns, from the message request Parameters data structure, take out the excited message after analogue system is finished dealing with, this excited message is delivered to BFM in the emulator module.
Four, emulator module is finished test to this excited message of input, and the message that will contain after the test of test result is delivered to corresponding analysis module object.
After input stimulus data in the emulator module obtained this excited message for the BFM of logic chip, it was transformed into clock signal with this excited data, passes to DUV.During emulation, DUV handles excited data, and the output result data.The BFM of logic chip data output is converted to the data of behavioral scaling with the signal of this DUV output, i.e. message (or message to be analyzed) as a result.
The BFM of logic chip data output sends services request, also realizes by calling the PLI interface routine.The parameter that the PLI interface routine transmits BFM is initiated request by above-mentioned message request Parameters data structure to control module, waits for the message that this Request Processing is finished then
Pass through message request Parameters data structure swap data between PLI interface routine and the analysis module, the PLI interface routine is in filling in the message request Parameters data structure after the related data, the interface function that the calling logic emulation test system the provides request of sending is (term of execution of this function, the execution of simulation software stops), after the data service module of control module is received this services request, control module obtains corresponding object module (being the analysis module example) name from the message request Parameters data structure, thereby obtain the handle of analysis module example, call the message processing program of analysis module then, this analysis request is delivered to this analysis module, be in the analysis module object, this analysis module can take out described message to be tested from the message request Parameters data structure.
Five, this analysis module object analysis is somebody's turn to do the message after testing, and analysis result is exported.
Analysis module is analyzed after BFM receives message after the test, is inserted into label in the message up to extracting emulation platform, and finishes the checking of the quiet lotus of message.This analytic process is standardized, can sequencing, and it more specifically comprises:
1, the message after this test is carried out the analysis of agreement accordance,, then carry out the message reorganization, obtain complete message if be the section message;
If the message after this test is the message that logic to be tested is inserted automatically, then by user's aided verification; Otherwise continue.
When analysis module is receiving that logic to be tested inserts message automatically, as administrative message, management cell, these messages do not contain sequence of message number, it or not the message that emulation test system produces, this class message, analysis module can't further be analyzed its correctness, and these messages are passed to subscriber authentication module, allows the subscriber authentication module correct judgment.
In addition, the route correctness of message, broadcasting correctness, message conversion correctness need subscriber authentication module to provide supplementary just can finish.After analysis module extracts test serial number, visit message data library module, obtain producing the stimulating module instance handle of this message, call the stimulating module example and recover original message, the analysis module example can call the subscriber authentication module of being worked out voluntarily by the user, original message and reception message are passed to subscriber authentication module, subscriber authentication module is finished the analysis of message conversion correctness, and provide the anticipatory export list information, analysis module is according to the expected information that returns, and, finish the route correctness according to the historical record of this message in the message data library module, the analysis of broadcasting copy correctness.Analysis module writes the message data library module with the outlet information of analysis result and reception message.
2, this complete message is resolved, extract the insertion label, obtain the message payload;
3, verify this message payload, obtain analysis result.
According to the record data of this message in the message store, analyze outlet correctness, message delay correctness and the packet out-ordering correctness of message automatically.
In aforesaid stimulating module, the series of parameters of stream is arranged, the QOS attribute of stream is described, analysis module will be notified stimulating module after receiving message, carry out the inspection of QOS accordance, such as, it is out of order to check whether the time-delay of message surpasses setting value, whether inspection exists.
Like this, the tester just can retrieve by the user interface service module in the control module, the analysis result in the explicit message database module and other relevant informations.
Claims (10)
1, a kind of logical simulation test macro is characterized in that, this system includes:
Emulator module, described emulator module comprises the HDL code module, and described HDL code module is used to send the test and excitation request, and the excited message of input is handled, and finishes the simulation process test, and the message after the output processing is to corresponding analysis module;
Control module is used for explaining and carries out main script file and control each module; Receive and transmit the test and excitation request that described HDL code module sends;
Stimulating module is accepted the test and excitation request that described control module is transmitted, and the structure excited message is stored to the message data library module with this excited message, and this excited message is sent to described emulator module carries out simulation process;
Analysis module receives HDL code module in the described emulator module and finishes the message of exporting after the simulation process and analyze, and analysis result is saved in message data library module and output;
The CPU configuration module is controlled described analysis module described analysis result is saved in the message data library module;
The message data library module is used to realize the storage of message data and read.
2, a kind of logical simulation test macro as claimed in claim 1, it is characterized in that, described stimulating module includes the message constructor that contains the TCL script accordingly, and described message constructor receives the excited data stream that this stimulating module produces, and constructs described excited message.
3, a kind of logical simulation test macro as claimed in claim 1, it is characterized in that, this system also further comprises: subscriber authentication module, described subscriber authentication module receives the excited message of described stimulating module structure, obtain the expection result of this message, and will expect that under described stimulating module calls result is stored to the message data library module; And receive the excited message of described analysis module transmission and the excited message after the simulation process, finish the further checking that the HDL code module is handled excited message, and will verify that the result returns to described analysis module.
4, as claim 1 or 2 or 3 described a kind of logical simulation test macros, it is characterized in that the connection between described control module and described stimulating module, analysis module, the CPU configuration module is undertaken by the base class module.
5, a kind of logical simulation test macro as claimed in claim 4 is characterized in that, the connection between described subscriber authentication module and described stimulating module, the analysis module is undertaken by the base class module.
6, a kind of logical simulation method of testing,, it is characterized in that this method comprises following steps:
Main script file is carried out in a, explanation, sets up stimulating module and analysis module according to main script file then, and according to parameter wherein this stimulating module and analysis module is configured;
B, emulator module are sent the testing service request, and deliver to this stimulating module;
C, this stimulating module produce excited data stream according to this test and excitation request, described excited data stream is converged, and take out the parameter of described excited data stream, produce quiet lotus part;
D, message constructor are partly constructed described parameter and quiet lotus, obtain excited message, and this excited message is delivered to emulator module;
E, emulator module are finished simulation process to this excited message of input according to the hardware behavior of HDL code description, and the message after handling is delivered to corresponding analysis module;
F, this analysis module object obtain quiet lotus part from the message after the described simulation process, this quiet lotus is partly verified, and analysis result is exported.
7, a kind of logical simulation method of testing as claimed in claim 6 is characterized in that, set up stimulating module and analysis module among the described step a are meant and set up several corresponding stimulating module and analysis modules.
8, a kind of logical simulation method of testing as claimed in claim 6 is characterized in that,
The emulator module among the exchanges data of emulator module in described step b, the steps d and stimulating module object and the step e and the exchanges data of analysis module object are undertaken by Parameters data structure.
9, a kind of logical simulation method of testing as claimed in claim 6 is characterized in that described step f specifically comprises:
F1, the message after the described simulation process is carried out the analysis of agreement accordance,, then the section message is recombinated, obtain complete message if be the section message;
F2, this complete message is resolved, obtain the message payload;
F3, verify this message payload, obtain analysis result and output.
10, a kind of logical simulation method of testing as claimed in claim 9 is characterized in that, further comprises among the step f1 of described step f: if the message after this test is the message that logic to be tested is inserted automatically, then by user's aided verification; Otherwise continue.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031228852A CN100511149C (en) | 2003-05-07 | 2003-05-07 | Logic emulation testing system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031228852A CN100511149C (en) | 2003-05-07 | 2003-05-07 | Logic emulation testing system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1549119A CN1549119A (en) | 2004-11-24 |
| CN100511149C true CN100511149C (en) | 2009-07-08 |
Family
ID=34321152
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031228852A Expired - Fee Related CN100511149C (en) | 2003-05-07 | 2003-05-07 | Logic emulation testing system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100511149C (en) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100349416C (en) * | 2004-12-01 | 2007-11-14 | 华为技术有限公司 | Method and device for controlling excited data flow, and excited message producer |
| CN100359488C (en) * | 2005-08-19 | 2008-01-02 | 华为技术有限公司 | Method for automatic generating random excitation based on percentage of function coverage |
| CN100432954C (en) * | 2005-09-23 | 2008-11-12 | 中兴通讯股份有限公司 | Inlaid system detection method and system |
| CN100452062C (en) * | 2006-01-13 | 2009-01-14 | 大同股份有限公司 | Method for testing hardware circuit block writen by hardware descriptive language |
| CN101604290B (en) * | 2009-06-05 | 2012-05-16 | 中国移动（深圳）有限公司 | Background module test method and backstage module test system |
| CN101782869B (en) * | 2010-03-09 | 2013-10-02 | 南京航空航天大学 | Method for testing function of panel based on Bash shell script |
| CN101847162B (en) * | 2010-05-25 | 2013-03-27 | 中国电力科学研究院 | Electric system simulation centre data processing method based on file and database exchange |
| CN102495778B (en) * | 2011-12-13 | 2014-10-22 | 曙光信息产业(北京)有限公司 | System and method for testing single-packet regular matching logic |
| CN103580954A (en) * | 2013-10-29 | 2014-02-12 | 盛科网络（苏州）有限公司 | Device and method for verifying switch chip through software simulation |
| CN104679963B (en) * | 2015-03-20 | 2018-04-27 | 杭州士兰微电子股份有限公司 | A kind of simulating, verifying apparatus and method based on TCL |
| CN106155903B (en) * | 2015-04-20 | 2021-05-07 | 恩智浦美国有限公司 | Apparatus and method for system design verification |
| CN105574292B (en) * | 2016-01-29 | 2018-12-11 | 盛科网络（苏州）有限公司 | A method of realizing that any bandwidth of multichannel is given out a contract for a project based on dynamic array |
| CN107566204B (en) * | 2016-06-30 | 2020-11-10 | 中兴通讯股份有限公司 | Excitation message generation control method and device and logic detection equipment |
| CN106841974B (en) * | 2016-12-13 | 2019-11-12 | 深圳市紫光同创电子有限公司 | A kind of FPGA test platform and method |
| CN108279890B (en) * | 2017-01-06 | 2021-12-24 | 阿里巴巴集团控股有限公司 | Component publishing method, component constructing method and graphical machine learning algorithm platform |
| CN109426503B (en) * | 2017-07-21 | 2022-05-31 | 华为技术有限公司 | Method and apparatus for providing artificial excitation |
| CN108108306B (en) * | 2018-02-09 | 2021-10-15 | 苏州盛科通信股份有限公司 | Method and system for improving message analysis test coverage rate |
| CN108363567B (en) * | 2018-02-12 | 2021-02-12 | 盛科网络（苏州）有限公司 | Database-based verification platform exciter automatic generation method |
| CN109213680B (en) * | 2018-08-28 | 2022-01-25 | 康烁 | Automatic testing method based on embedded software simulator |
| CN110688296A (en) * | 2019-02-25 | 2020-01-14 | 上海核工程研究设计院有限公司 | Automatic testing method for computerized rule configuration |
| CN111221693B (en) * | 2019-12-31 | 2020-10-27 | 深圳市芯天下技术有限公司 | Verification method, system, device and storage medium for NOR flash configuration module |
| CN112905154A (en) * | 2020-12-30 | 2021-06-04 | 杭州加速科技有限公司 | Method and device for improving software and hardware collaborative development speed |
| CN113704044B (en) * | 2021-07-19 | 2024-05-24 | 新华三半导体技术有限公司 | Interface verification system, method and chip |
-
2003
- 2003-05-07 CN CNB031228852A patent/CN100511149C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1549119A (en) | 2004-11-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100511149C (en) | Logic emulation testing system and method | |
| US6708329B1 (en) | Method and apparatus for producing modules compatible with a target system platform from simulation system modules utilized to model target system behavior | |
| CN103178996B (en) | Distributed packet-switching chip model verification system and method | |
| US5390320A (en) | Automatically converting structured analysis tool database outputs into an integrated simulation model via transportable standardized metafile | |
| US7020722B2 (en) | Synchronization of distributed simulation nodes by keeping timestep schedulers in lockstep | |
| US7424416B1 (en) | Interfacing hardware emulation to distributed simulation environments | |
| CN107807878A (en) | Automatic test engine based on keyword | |
| CN101093521B (en) | FPGA emulation device and method | |
| Bazjanac et al. | IFC HVAC interface to EnergyPlus-A case of expanded interoperability for energy simulation | |
| CN102480467B (en) | A kind of SOC software and hardware cooperating simulation verification method of communications protocol Network Based | |
| CN109657379A (en) | A kind of model aircraft simulation and verification platform | |
| CN106951575A (en) | A kind of multidisciplinary Virtual Experiment Simulation method based on COSIM | |
| US7231338B2 (en) | Distributed simulation system having phases of a timestep | |
| CN100417075C (en) | Interface test method | |
| Pang et al. | Automatic model generation of IEC 61499 function block using net condition/event systems | |
| Tahar et al. | Modeling and formal verification of the Fairisle ATM switch fabric using MDGs | |
| Pozefsky et al. | A meta-implementation for Systems Network Architecture | |
| Regensburger et al. | Formal verification of SDL systems at the Siemens mobile phone department | |
| Terpstra et al. | Testing theory in practice: A simple experiment | |
| CN111274750A (en) | FPGA simulation verification system and method based on visual modeling | |
| CN113391996A (en) | Software interface combination execution testing method based on workflow | |
| CN106682249A (en) | Model-independent general-purpose publish/subscribe interface testing system and model-independent general-purpose publish/subscribe interface testing method | |
| CN115426300B (en) | Method for automatically testing API (application program interface) of NP (network Programming) chip based on data packet | |
| CN102012856A (en) | Method and device for automatically generating hardware component simulation engineering | |
| Wytrębowicz | Hardware specification generated from Estelle |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090708 Termination date: 20160507 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |