CN105975726A - Verification method and platform based on SystemVerilog language - Google Patents
Verification method and platform based on SystemVerilog language Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention discloses a verification method and platform based on a systemVerilog language. The method comprises the steps of generating excitation, compiling the excitation to generate binary data, adding timing sequence information for the generated binary data, inputting the binary data into a chip to be tested according to the timing sequence information, and verifying the chip to be tested according to the binary data input to the chip to be tested and data output by the chip to be tested, wherein the verification environment is achieved through the systemVerilog language. According to the verification method and platform based on the systemVerilog language, a simulation control platform and a self-verification control platform are separated, reutilization is easy; the verification method and platform based on the systemVerilog language have good compatibility, and therefore the verification platform compiled through SystemVerilog can be conveniently transplanted to various kinds of simulation environments; a hierarchical structure is adopted, modules are relatively independent, the complexity of the verification platform is lowered, and the platform can be conveniently maintained and modified in the verification process; the verification accuracy degree is improved, the verification efficiency is greatly improved, the verification time is saved, and verification tasks are finished more quickly.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to a kind of based on SystemVerilog language test
Card method and platform.
Background technology
In integrated circuit fields, the design of integrated circuit and checking are that to realize two of volume production chip important
Content.The chip of function admirable needs based on advanced design, but in order to reduce the risk of volume production,
Needed to verify, to guarantee that the design of chip reaches intended requirement before chip flow.
Flash chip is chip conventional in current computer, communication and consumer electronics field, and it is one
Plant non-volatile random access memory (Non-Volatile Random Access Memory, NVRAM),
Program can directly perform in flash chip, and after power down, data will not disappear.The volume of flash chip is little,
Low in energy consumption, thus be widely used.
At present for the checking of chip design, general employing Verilog HDL language is to whole chip system
Verify.But, owing to the internal each module of flash chip has multiformity and complexity, such as numeral
Circuit and analog circuit coexist, and digital circuit and analog circuit interweave, so that for flash chip
Checking, if using Verilog HDL language to verify, will take for substantial amounts of manpower and materials, and with
The increase of later stage test case, the checking work making whole chip is more and more difficult, extremely inefficient, and
Verification quality cannot ensure.
Summary of the invention
In view of this, the present invention provides a kind of verification method based on SystemVerilog language and platform,
Its object is to reduce the difficulty of checking, improve the efficiency of checking.
The invention provides a kind of verification method based on SystemVerilog language, the method includes:
Generate excitation；
Compiling excitation generates binary data；
Binary data for generating adds time sequence information；
According to time sequence information, described binary data is inputted chip under test；
According to quilt described in the data verification of the binary data and chip under test output that input chip under test
Survey chip；
Wherein verification environment uses SystemVerilog language to realize.
Preferably, described generation encourages the random parameter included according to configuration and constraint to generate random constraints
Excitation.
Preferably, the described binary data according to input chip under test and the data of chip under test output
Verify that described chip under test includes:
If the binary data of input chip under test is corresponding with the data that chip under test exports, then checking is logical
Cross；
If the data of the binary data of input and chip under test output are the most corresponding, then verify and do not pass through.
Preferably, the method also includes:
In the case of checking is unsanctioned, change excitation is also verified, again until being verified or reaching
To the checking number of times preset.
Preferably, the described binary data according to input chip under test and the data of chip under test output
Verify that described chip under test includes:
If the binary data of input chip under test is consistent with excitation, then compare excitation defeated with chip under test
The data gone out；If the binary data of input chip under test is inconsistent with excitation, then verifies and do not pass through；
If encouraging corresponding with the data of chip under test output, then it is verified；If excitation and tested core
The data of sheet output are the most corresponding, otherwise verify and do not pass through.
Preferably, the method also includes:
According to function, instruction set is classified；
According to sorted instruction set, SystemVerilog language is used to write test case.
Preferably, the method also includes:
Statistical function coverage rate.
Preferably, described chip under test is flash chip.
The invention provides a kind of verification platform based on SystemVerilog language, this verification platform bag
Include:
Excitation generating module, is used for generating excitation；
Drive module, be used for compiling excitation to generate binary data；And the binary data for generation
Add time sequence information；
Input Monitor Connector module, for monitoring binary data according to time sequence information and binary data is defeated
Incoming interface module；
Interface module, for binary data inputting chip under test according to time sequence information, and exports tested
The data of chip output；
Output monitoring modular, for monitoring the data of the chip under test output of interface module output；
Authentication module, for the binary data according to Input Monitor Connector module monitors and output monitoring modular
Chip under test described in the data verification of the chip under test output of monitoring；
Wherein excitation generating module, driving module, Input Monitor Connector module, interface module, output monitoring mould
Block and authentication module use SystemVerilog language to realize.
Preferably, described excitation generating module be additionally operable to according to configuration random parameter and constraint generate with
Machine constraint excitation.
Preferably, described authentication module is additionally operable in the binary data of Input Monitor Connector module monitors and output
In the case of the data correspondence of the chip under test output of monitoring module monitors, identification is verified；In input
The data that the binary data of monitoring module monitors and the chip under test exporting monitoring module monitors export are not
In the case of correspondence, assert that checking is not passed through.
Preferably, this verification platform also includes authentication module again, is used in the case of checking is unsanctioned,
Change excitation is also verified again, until being verified or reach default checking number of times.
Preferably, authentication module, it is additionally operable to the binary data at input chip under test consistent with excitation
In the case of, compare the data of excitation and chip under test output；Input chip under test binary data with
Encourage inconsistent in the case of, assert checking do not pass through；Corresponding with the data of chip under test output in excitation
In the case of, identification is verified；In the case of excitation is the most corresponding with the data of chip under test output,
Assert that checking is not passed through.
Preferably, this verification platform also includes statistical module, for statistical function coverage rate.
Simulation Control Platform and self-inspection are controlled platform and are separated by the present invention, it is easy to recycling；Have good
Good compatibility so that the verification platform using SystemVerilog to write can transplant easily in
In various simulated environment；Use hierarchical structure so that each intermodule is relatively independent, reduce checking flat
The complexity of platform, it is simple to maintenance and amendment to platform in proof procedure；Automaticity is high, required
Random constraints excitation can automatically generate, and travels through all instructions and address, and can automatically collect and detect
Coverage rate；Improve the accuracy of checking, and significantly improve verification efficiency, save the proving time, more
Complete validation task soon.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes of the present invention
Point, the schematic description and description of the present invention is used for explaining the present invention, is not intended that the present invention's
Improper restriction.In the accompanying drawings:
Fig. 1 is the verification method flow chart based on SystemVerilog language that the present invention provides；
Fig. 2 is the verification method detail flowchart based on SystemVerilog language that the present invention provides；
Fig. 3 is the verification platform schematic diagram based on SystemVerilog language that the present invention provides.
Description of reference numerals
305 excitation generating module 310 drive module
315 Input Monitor Connector module 320 interface modules
325 chip under test 330 authentication modules
335 output monitoring modular 335 statistical modules
340 print modules
Detailed description of the invention
As employed some vocabulary in the middle of description and claim to censure specific components.This area skill
Art personnel are it is to be appreciated that hardware manufacturer may call same assembly with different nouns.This explanation
In the way of book and claim not difference by title is used as distinguishing assembly, but with assembly in function
On difference be used as distinguish criterion." bag as mentioned by the middle of description in the whole text and claim
Contain " it is an open language, therefore " comprise but be not limited to " should be construed to." substantially " refer to receivable
In range of error, those skilled in the art can solve described technical problem, base in the range of certain error
Originally described technique effect is reached.Description subsequent descriptions is to implement the better embodiment of the present invention, right institute
State description be the rule so that the present invention to be described for the purpose of, be not limited to the scope of the present invention.This
The protection domain of invention is when being as the criterion depending on the defined person of claims.
Using Verilog language to carry out the defect verified to overcome, the present invention uses SystemVerilog
Language realizes verification environment.
Fig. 1 shows the flow chart of the verification method based on SystemVerilog language that the present invention provides,
Specifically include: generate excitation (step 105)；Compiling excitation generates binary data (step 110)；
Binary data for generating adds time sequence information (step 115)；Enter described two according to time sequence information
Data processed input chip under test (step 120)；Binary data according to input chip under test and quilt
Survey chip under test (step 125) described in the data verification of chip output.
In step 105, it is possible to use the excitation generating module next life that SystemVerilog language is write
Become excitation, such as, according to the parameter received and instruction, dynamically produce and can be loaded into chip under test (such as
Flash chip) register transfer level model in random constraints instruction and data.Parameter and instruction are permissible
SystemVerilog language is used to write in test case.In test case, can be according to function pair
Instruction set is classified, and using instruction close for function as a class, is placed in same instruction set, such as
Sector/Block (64KB)/Block (32KB) Erase instruction is classified as a class.Above-mentioned parameter can be
Random parameter or preset parameter, it is preferable that for random parameter.
Stochastic instruction parameter and random data parameter can be realized by program language, refer to the most at random
Parameter is made to generate in the following way:
Read_select=$ dist_uniform (tb_seed, 0,6)；
Random data parameter can generate in the following way:
Mode=$ dist_uniform (tb_seed, 1,3)；
Complete_address=get_special_patterns (`DATA_ALL_RANDOM)；
The above-mentioned read class instruction random according to read_select order generation can be normal read, fast
Read, dual read, quad_read etc., mode generate random parameter with complete_address.And
Excitation generating module generates affined instruction according to the design parameter in read_select.Mode with
Design parameter in complete_address generates showing of affined data, bound data and constraint instructions
Under such as:
Bound data:
Constraint instructions:
As example, when classifying according to function, can be handled as follows:
1, (Standard/Dual/Quad SPI Instructions) pattern classification
Erase class: Sector/Block (64KB)/Block (32KB)/Chip
Read class:
Normal/Fast/Fast_Dual_O/Fast_Dual_IO/Fast_Quad_O/Fast_Quad_IO
Program class: Page/Quad Page
ID class: Manufacture/Device/JEDEC
Suspend class: Erase/Program
2, (QPI Instructions) pattern classification
SR class: Read/Write SR1
Read/Write SR2
Read/Write SR3；
Erase class: Sector/Block (64KB)/Block (32KB)/Chip
Read class: Fast_Quad_IO
ID class: Manufacture/Device/JEDEC
Program class: Page
Suspend class: Erase/Program
In step 110, it is possible to use driving module write in SystemVerilog language, thus can
To generate binary data by driving module to realize the compiling to excitation；
In step 115, similarly, module is driven can to pass over receiving excitation sending module
Complete random constraints instruction and data after, according to the timing requirements of design to be measured, generate required instruction
With data sequence；
In the step 120, similarly, module is driven can be inputted by binary data according to time sequence information
Chip under test；Preferably, for the ease of checking, can first binary data input be used
The Input Monitor Connector module that SystemVerilog language is write, it is hereby achieved that the two of input chip under test enter
Data message processed, is input to chip under test by Input Monitor Connector module by binary data the most again；Need
Bright, Input Monitor Connector module and chip under test can have what use SystemVerilog language was write
Interface module；
In step 125, chip under test, after receiving the binary data of input, can produce corresponding
Output data；In the present invention, chip under test example is flash chip, instruction mainly reading and writing, erasing
Deng, the data that the data therefore exported store with the binary data of input or flash chip should be consistent,
For other chips, such as algorithm chip, it is also possible to inputted in theory between data and output data
Relation；It is thus possible to it is the most corresponding, such that it is able to pass through with input data by comparing output data
Chip is verified by test case.
Above-mentioned flow process embodies the overall procedure of verification method based on SystemVerilog language.Need
It is noted that during checking, it is understood that there may be situation about being proved to be successful, needs parameter is carried out
Amendment generates new excitation and also again verifies, until being proved to be successful or reach predetermined checking number of times.
Fig. 2 shows verification method detail flowchart based on SystemVerilog language, and it is with Erase
Instruction is as example, and the method includes: parameter and constraint according to configuration generate random constraints excitation (step
Rapid 205)；Compiling excitation generates binary data (step 210)；For the binary data generated
Add time sequence information (step 215)；According to time sequence information, described binary data is inputted chip under test
(220)；Judge that the binary data of input is the most consistent with the binary data of output (step 225)；
If consistent, then judge whether to complete all of test case (step 230), if it is, statistics
Function coverage (step 235), it is preferable that print statistical result and preserve (step 240)；If
Inconsistent, then continue whether to reach default checking number of times (step 245), if it is not, change
Parameter, generating new excitation and re-starts checking, performing step 205, if having reached default testing
Card number of times, then continue to determine whether to complete all of test case, performs step 230, if it is,
Statistical function coverage rate, performs step 235, it is preferable that prints statistical result and preserves (step 240).
Without completing all of test case, then change test case, perform step 205.
In embodiment shown in above-mentioned, the comparison of input data and output data can pass through Scoreboard
Module realizes that (Scoreboard module can be a kind of implementation of authentication module, uses
SystemVerilog language is write), function coverage statistics can be realized by statistical module, prints statistics
Result can be realized by print module, and statistical module and print module can also be by SystemVerilog languages
Speech is write.Output monitoring module, can be automatically data transmission when monitoring chip under test and having data to export
In Scoreboard module；Scoreboard module after receiving design to be measured all output data,
And the input data automatically come with input monitoring module transfer compare.
Using flash chip as example, in proof procedure, by the register transfer level model of flash chip
In instruction set, internal special function register and data address position are as function coverage module collection
Point, sets up functional coverage module, all test cases run after, can add up obtain final
Function coverage.
In above-mentioned verification method, verification environment separates with control centre, say, that in above-described embodiment
The module being previously mentioned can use SystemVerilog language to write, and control command is by Perl language
Writing, the emulation platform that the register transfer level model of flash chip can carry out functional verification controls,
Realize test case serial automatically to load and parameter adjustment.
Excitation generating module mentioned above, in simulation process, excitation generating module according to
The data passed in task_data_gen function, dynamically generate and can be loaded in driving module without sequential
The random constraints instruction of information and data.In test case, the parameter of stochastic generation is deposited with the instruction retrained
In task_data_gen function.
Driving module mentioned above, the data that predominantly actuation generator passes over are compiled, and enter
Row generates binary data and adds time sequence information figure.As a example by flash memory is under standard SPI interface pattern,
Its CLK, the level on the pin such as CE, SI need to input in order according to SPI protocol specification, therefore needs respectively
Individual pin defines respectively.
`CSB_CODE:csbesd=logic_level；
`SCK_CODE:sckesd=logic_level；
Input Monitor Connector module mentioned above, be mainly used in chip under test (such as flash chip) is defeated
Enter end to be monitored, thus realize to chip under test internal receipt to real data detect, its inspection
Survey part can use the assertion statement in SystemVerilog to write, named
Assertions_data_in is mainly added on the command register in flash chip and address part, thus
Guarantee that the data driving the data produced in module to receive with flash chip are consistent.
Interface module mentioned above is for transmitting data to flash chip and receiving number from flash chip
According to, it is achieved realize channel function.It is directed to the running status of tested flash chip, is respectively configured as standard
SPI mode, DUAL pattern or QUAD pattern.
Output monitoring modular mentioned above is converted to parallel data to the serial data of design output to be measured,
And put in task_data_out function and call for Scoreboard module.
The verification platform based on SystemVerilog language that the present invention provides is as it is shown on figure 3, specifically wrap
Include excitation generating module 305, drive module 310, Input Monitor Connector module 315, interface module 320, defeated
Go out monitoring modular 335, authentication module 330, it is preferable that statistical module 335 can also be included and/or beat
Impression block 340.Excitation generating module 305 can be according to the parameter of the stochastic generation received from test case
After the instruction retrained, generate corresponding excitation；Drive module 310, be used for compiling excitation and generate
Binary data；And the binary data for generating adds time sequence information；Input Monitor Connector module 315,
For monitoring binary data according to time sequence information, and by binary data input interface module 320；Connect
Mouth die block 320, for binary data inputting chip under test according to time sequence information, and exports tested core
The data of sheet output；Output monitoring modular 335, for monitoring the chip under test of interface module 320 output
The data of output, the serial data that interface module exports is converted to and line number by preferably output monitoring modular
According to；Authentication module 330, for the binary data according to Input Monitor Connector module monitors and output monitoring
Chip under test described in the data verification of the chip under test output of module monitors.Statistical module 335 can be complete
When becoming all test cases, according to the result of command verification, statistical function coverage rate, such as, can pass through to survey
The ratio that examination successfully instructs and be test for instruct between summation carrys out computing function coverage rate.Print module
340, the result can be printed for each test case and preserve, it is also possible to print the merit that statistics obtains
Can coverage rate.Preferably, present invention additionally comprises authentication module (not shown) again, in checking not
In the case of by, change excitation is also verified again, until being verified or reach default checking
Number of times.In the present invention, Simulation Control Platform and self-inspection control platform and are separated, and such as self-inspection controls platform
Can be able to include with authentication module 330, print module 340 and statistical module 335, Simulation Control Platform
Excitation generating module 305, drive module 310, Input Monitor Connector module 315, interface module 320 and defeated
Go out monitoring modular 335, thus when the flash chip of different capabilities is verified, it is only necessary to amendment is imitative
Really control platform.
It should be noted that above-mentioned compiling refers mainly to change parallel data, become serial data.
As addr [23:0] data are compiled, i.e. it is carried out serial conversion output
As example, authentication module (the such as Scoreboard module) monitoring modular of detection output in real time,
Monitor output module and be in the presence of data in running status, and task_data_out, then
Scoreboard module starts, it is preferred that, start to contrast the input data of flash chip, output
Data and expected data.When input data, output, expected data contrast errorless after, Scoreboard
Output transcription comparison's information.If comparing is made mistakes, or the most then Scoreboard module output
Control signal, changes the acquiescence random arrangement in excitation maker, and mainly address and data bit, enter
The new emulation once of row, if makeing mistakes all the time through repeatedly circulating emulation (such as reaching default simulation times),
Then Scoreboard module output comparison information, indicates error coordinates.
Above-mentioned expected data is ideal data, and the original parallel data that i.e. excitation module generates (swash
Encourage).As chip carried out page program operation, it is desirable to data are generated by excitation generating module
The parallel data of 256 byte.Input data are to drive module that expectation parallel data is carried out serial conversion
The binary data obtained, can add time sequence information to it to input chip under test.Output data are
The binary serial data of output in flash chip.
Preferably, in comparison process, input data are carried out serioparallel exchange, use in units of byte
16 systems contrast one by one with expected data, if contrast is consistent, output data are carried out serioparallel exchange,
16 systems are used to contrast one by one with expected data in units of byte equally.If all entering correctly into
The statistical function coverage rate stage.If input data are inconsistent with expected data contrast, or export data and phase
Prestige Data Comparison is inconsistent, then labelling failure directly updates excitation, and re-starts emulation.
Those skilled in the art it should be appreciated that embodiments of the invention can be provided as method, device or
Computer program.Therefore, the present invention can use complete hardware embodiment, complete software implementation,
Or combine the form of embodiment in terms of software and hardware.And, the present invention can use one or more
The computer-usable storage medium wherein including computer usable program code (includes but not limited to disk
Memorizer, CD-ROM, optical memory etc.) form of the upper computer program implemented.
Described above illustrate and describes some specific embodiments of the present invention, but as previously mentioned, it should reason
Solve the present invention and be not limited to form disclosed herein, be not to be taken as the eliminating to other embodiments,
And can be used for various other combination, amendment and environment, and can in invention contemplated scope described herein,
It is modified by above-mentioned teaching or the technology of association area or knowledge.And those skilled in the art are carried out changes
Move and change is without departing from the spirit and scope of the present invention, the most all should be in the protection of claims of the present invention
In the range of.
Claims (14)
1. a verification method based on SystemVerilog language, it is characterised in that the method includes:
Generate excitation；
Compiling excitation generates binary data；
Binary data for generating adds time sequence information；
According to time sequence information, described binary data is inputted chip under test；
According to quilt described in the data verification of the binary data and chip under test output that input chip under test
Survey chip；
Wherein verification environment uses SystemVerilog language to realize.
Verification method the most according to claim 1, it is characterised in that described generation excitation includes
Random parameter and constraint according to configuration generate random constraints excitation.
Verification method the most according to claim 1, it is characterised in that described tested according to input
Chip under test described in the data verification of the binary data of chip and chip under test output includes:
If the binary data of input chip under test is corresponding with the data that chip under test exports, then checking is logical
Cross；
If the data of the binary data of input and chip under test output are the most corresponding, then verify and do not pass through.
Verification method the most according to claim 3, it is characterised in that the method also includes:
In the case of checking is unsanctioned, change excitation is also verified, again until being verified or reaching
To the checking number of times preset.
Verification method the most according to claim 1, it is characterised in that described tested according to input
Chip under test described in the data verification of the binary data of chip and chip under test output includes:
If the binary data of input chip under test is consistent with excitation, then compare excitation defeated with chip under test
The data gone out；If the binary data of input chip under test is inconsistent with excitation, then verifies and do not pass through；
If encouraging corresponding with the data of chip under test output, then it is verified；If excitation and tested core
The data of sheet output are the most corresponding, otherwise verify and do not pass through.
6. according to the verification method described in claim 1-5 any one, it is characterised in that the method is also
Including:
According to function, instruction set is classified；
According to sorted instruction set, SystemVerilog language is used to write test case.
Verification method the most according to claim 6, it is characterised in that the method also includes:
Statistical function coverage rate.
Verification method the most according to claim 1, it is characterised in that described chip under test is for dodging
Deposit chip.
9. a verification platform based on SystemVerilog language, it is characterised in that this verification platform
Including:
Excitation generating module, is used for generating excitation；
Drive module, be used for compiling excitation to generate binary data；And the binary data for generation
Add time sequence information；
Input Monitor Connector module, for monitoring binary data according to time sequence information and binary data is defeated
Incoming interface module；
Interface module, for binary data inputting chip under test according to time sequence information, and exports tested
The data of chip output；
Output monitoring modular, for monitoring the data of the chip under test output of interface module output；
Authentication module, for the binary data according to Input Monitor Connector module monitors and output monitoring modular
Chip under test described in the data verification of the chip under test output of monitoring；
Wherein excitation generating module, driving module, Input Monitor Connector module, interface module, output monitoring mould
Block and authentication module use SystemVerilog language to realize.
Verification platform the most according to claim 9, it is characterised in that described excitation generating module
It is additionally operable to the random parameter according to configuration and constraint generates random constraints excitation.
11. verification platforms according to claim 9, it is characterised in that described authentication module is also used
In exporting with the chip under test of output monitoring module monitors at the binary data of Input Monitor Connector module monitors
Data correspondence in the case of, identification is verified；Input Monitor Connector module monitors binary data with
Output monitoring module monitors chip under test output data the most corresponding in the case of, assert checking do not lead to
Cross.
12. verification platforms according to claim 11, it is characterised in that this verification platform also wraps
Including authentication module again, in the case of checking is unsanctioned, change excitation is also verified again,
Until being verified or reach default checking number of times.
13. verification platforms according to claim 9, it is characterised in that authentication module, are additionally operable to
In the case of the binary data of input chip under test is consistent with excitation, compare excitation defeated with chip under test
The data gone out；In the case of the binary data of input chip under test is inconsistent with excitation, assert checking
Do not pass through；In the case of excitation is corresponding with the data of chip under test output, identification is verified；Swashing
Encourage with chip under test output data the most corresponding in the case of, assert checking do not pass through.
14. according to the verification platform described in claim 9-13 any one, it is characterised in that this checking
Platform also includes statistical module, for statistical function coverage rate.
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| CN106529099A (en) * | 2016-12-20 | 2017-03-22 | 盛科网络（苏州）有限公司 | Method for automatically generating verification model on the basis of interface |
| CN106777571A (en) * | 2016-11-30 | 2017-05-31 | 北京广利核系统工程有限公司 | A kind of FPGA algorithmic block automatic Verification platform realized based on System Verilog |
| CN107247859A (en) * | 2017-08-14 | 2017-10-13 | 深圳云天励飞技术有限公司 | Verification method, device, electronic equipment and the storage medium of Logic Circuit Design |
| CN107944151A (en) * | 2017-11-28 | 2018-04-20 | 郑州云海信息技术有限公司 | The link-layer authentication platform and method of excitation and simulation result are preserved using binary system |
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| CN108596799A (en) * | 2018-03-27 | 2018-09-28 | 佛山市顺德区中山大学研究院 | It is a kind of that topic device, method and system are sentenced based on Verilog |
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| CN109885905A (en) * | 2019-01-29 | 2019-06-14 | 北京中科微电子技术有限公司 | A kind of verifying system improving digital circuitry functions verification efficiency |
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| CN108596799A (en) * | 2018-03-27 | 2018-09-28 | 佛山市顺德区中山大学研究院 | It is a kind of that topic device, method and system are sentenced based on Verilog |
| CN108596799B (en) * | 2018-03-27 | 2020-11-13 | 佛山市顺德区中山大学研究院 | Verilog-based question judging device, method and system |
| CN108763676A (en) * | 2018-05-15 | 2018-11-06 | 天津芯海创科技有限公司 | Driving source and function verification method |
| CN109885905A (en) * | 2019-01-29 | 2019-06-14 | 北京中科微电子技术有限公司 | A kind of verifying system improving digital circuitry functions verification efficiency |
| CN111061629A (en) * | 2019-11-21 | 2020-04-24 | 中国航空工业集团公司西安航空计算技术研究所 | Graphic command pre-decoding unit verification platform based on Verilog |
| CN111209660A (en) * | 2019-12-31 | 2020-05-29 | 深圳市芯天下技术有限公司 | Nor Flash simulation and verification system |
| CN111967209A (en) * | 2020-08-21 | 2020-11-20 | 广芯微电子（广州）股份有限公司 | SOC simulation verification method and device and storage medium |
| CN113157573A (en) * | 2021-04-19 | 2021-07-23 | 上海湃星信息科技有限公司 | Software test verification system and construction method thereof |
| CN113791938A (en) * | 2021-07-14 | 2021-12-14 | 中山大学 | High-level comprehensive simulation verification method and system based on FPGA chip |
| CN113791938B (en) * | 2021-07-14 | 2024-05-28 | 中山大学 | High-level comprehensive simulation verification method and system based on FPGA chip |
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