CN107247859B - Verification method, device, electronic equipment and the storage medium of Logic Circuit Design - Google Patents
Verification method, device, electronic equipment and the storage medium of Logic Circuit Design Download PDFInfo
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- CN107247859B CN107247859B CN201710693558.6A CN201710693558A CN107247859B CN 107247859 B CN107247859 B CN 107247859B CN 201710693558 A CN201710693558 A CN 201710693558A CN 107247859 B CN107247859 B CN 107247859B
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The present invention provides a kind of verification method of Logic Circuit Design, including generates configuration data and excited data by verification platform；Configuration and excited data are stored to target memory；It will be configured by verification platform and the excited data be sent to object to be tested；References object is controlled by verification platform and reads configuration and excited data from target memory, so that references object starts simulation calculation；Object to be tested is the logic circuit code that algorithm is realized with first language, and references object is the code that second language realizes identical algorithms, and controlling references object by verification platform terminates simulation calculation；The output data of references object is obtained by verification platform；The output data of object to be tested is obtained by verification platform；The verification result of object to be tested is determined according to the output data of references object and object to be tested.The present invention also provides a kind of verification devices of Logic Circuit Design.The present invention realizes the purpose for accurately verifying object to be tested.
Description
Technical field
The present invention relates to chip design technical field more particularly to a kind of verification method of Logic Circuit Design, device,
Electronic equipment and storage medium.
Background technology
Since integrated circuit becomes increasingly complex, digital IC design engineer is electric by the logic that SystemVerilog writes
Road code is tested design (Design Under Test, DUT) and is also become increasingly complex, how to ensure logic circuit code just
True property is just more and more important.And the work of number IC verification engineers, it is mainly based upon electric design automation
The function of (Electronics Design Automation, EDA) software programming test program verifying logic code.It is main at present
The test program of stream is to be based on SystemVerilog language, and this language is the superset of Verilog, and has object-oriented
Function, can very easily construct the program of higher abstraction hierarchy.
Many algorithm models are complicated at present, such as intelligent algorithm (Artificial Intelligence, AI), and
Including a large amount of matrix operation.In the verification of the logic circuit code of the algorithm, if realized comprising a large amount of with emulator
The algorithm of matrix operation needs to use more cycle, and operational efficiency is low, and debugging is difficult.A kind of method of solution is using straight
It connects programming interface (Direct Programming Interface) and calls reference model (algorithm model that such as C language is write),
Since the language of code of code language and reference model of emulator is different, will result in emulator can not directly read reference
The code of model causes certain difficulty to debugging, for example, SystemVerilog emulators can not directly read C code.
Invention content
In view of the foregoing, it is necessary to which a kind of verification method of Logic Circuit Design, device, electronic equipment and storage are provided
Medium accurately tests the Logic Circuit Design as object to be tested by being combined with references object verification platform
Card.It is also avoided that simultaneously and writes a large amount of test code, improve the verification efficiency of Logic Circuit Design.
A kind of verification method of Logic Circuit Design, the method includes：
Configuration data and excited data are generated by verification platform；
The configuration data and excited data are stored to target memory；
The configuration data and the excited data are sent to object to be tested by the verification platform；
References object is controlled by the verification platform, and the configuration data and described is read from the target memory
Excited data, so that the references object starts simulation calculation, the object to be tested is the logic that algorithm is realized with first language
Circuit code, the references object are that the code of the algorithm is realized with second language, the first language and second language
Speech is different；
The references object, which is controlled, by the verification platform terminates simulation calculation；
The output data of the references object is obtained by the verification platform；
The output data of the object to be tested is obtained by the verification platform；
According to the output data of the references object and the output data of the object to be tested, the object to be tested is determined
Verification result.
It is described to store the configuration data and excited data to target memory packet according to the preferred embodiment of the present invention
It includes：
The configuration data and excited data are preserved into text document with preset format, and stores to the target and stores
Device, the text document include the combination of one or more of：Plain text document, binary documents, JavaScript object
Marking language document.
According to the preferred embodiment of the present invention, the verification platform is communicated by interface one with the references object, is led to
It crosses interface two to be communicated with the object to be tested, the verification platform includes：Data input module, reference model module, number
According to output module and data comparing module；The data input module is used to send the configuration data and the excited data
To object to be tested；The data outputting module is used to obtain the output data of the object to be tested, and the reference model module is used
In the output data for obtaining the references object, the data comparing module be used for according to the output data of the references object and
The output data of the object to be tested determines the verification result of the object to be tested.
It is described to be deposited from the target by the verification platform control references object according to the preferred embodiment of the present invention
The configuration data and the excited data are read in reservoir, so that the references object starts simulation calculation includes：
When the verification platform starts, the process for controlling the references object is generated to start the references object, and
The references object detection is set to store the text document of the configuration data and the excited data；And/or
It is described the references object controlled by the verification platform terminate simulation calculation include：
Obtain the running state data of the verification platform；The running state data is stored with preset format to described
So that the references object is detected end status data in target memory；
When the references object detect it is described include terminating the running state data of status data when, the references object
Terminate simulation calculation, and the output data of the references object is stored with preset format into the target memory.
According to the preferred embodiment of the present invention, the output data packet that the references object is obtained by the verification platform
It includes：
By the reference model module, the output file of the references object is detected in the target memory, with
Preset format reads the output data of the references object from the output file of the references object.
According to the preferred embodiment of the present invention, the output data according to the references object and the object to be tested it is defeated
Go out data, determines that the verification result of the object to be tested includes：
When the output data of the references object is identical as the output data of object to be tested, it is described to be tested right to determine
As being verified；And/or
When the output data of the output data of the references object and the object to be tested differs, determine described to be tested
Banknote validation does not pass through.
According to the preferred embodiment of the present invention, the second language includes Python.
A kind of verification device of Logic Circuit Design, which is characterized in that the method includes：
Generation unit, for generating configuration data and excited data by verification platform；
Storage unit, for storing the configuration data and excited data to target memory；
Transmission unit, it is to be tested right for being sent to the configuration data and the excited data by the verification platform
As；
Control unit, for by the verification platform control references object read from the target memory described in match
Data and the excited data are set, so that the references object starts simulation calculation, the object to be tested is with first language reality
The logic circuit code of existing algorithm, the references object is that the code of the algorithm is realized with second language；
Control unit terminates simulation calculation for controlling the references object by the verification platform；
Acquiring unit, the output data for obtaining the references object by the verification platform；
The acquiring unit is additionally operable to obtain the output data of the object to be tested by the verification platform；
Comparing unit, for according to the output data of the references object and the output data of the object to be tested, determining
The verification result of the object to be tested.
A kind of electronic equipment, the electronic equipment include memory and processor, and the memory is for storing at least one
A instruction, the processor is for executing at least one instruction to realize the verification of Logic Circuit Design in any embodiment
In method.
A kind of computer readable storage medium, the computer-readable recording medium storage has at least one instruction, described
The verification method of Logic Circuit Design, the authentication of the Logic Circuit Design are realized at least one instruction when being executed by processor
Method includes in any embodiment in the verification method of Logic Circuit Design.
As can be seen from the above technical solutions, the present invention generates configuration data and excited data by verification platform；By institute
It states configuration data and excited data is stored to target memory；By the verification platform by the configuration data and the excitation
Data are sent to object to be tested；It is controlled described in the references object reads from the target memory by the verification platform
Configuration data and the excited data, so that the references object starts simulation calculation；Described in verification platform control
References object terminates simulation calculation；The output data of the references object is obtained by the verification platform；Pass through the verification
Platform obtains the output data of the object to be tested；According to the output of the output data of the references object and the object to be tested
Data determine the verification result of the object to be tested.The present invention by the way that the verification platform is combined with the references object,
Since the function of identical algorithms may be implemented in the references object and the object to be verified, ensureing the references object
When identical as the input data of object to be tested, pass through the output data for judging the references object and the object to be tested
The whether identical verification realized to the object to be tested of output data.Simultaneously the verification platform have good autgmentability,
Reusability.So as to avoid a large amount of coding work, the verification efficiency of Logic Circuit Design is improved.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the system architecture diagram of the preferred embodiment of the verification method of the realization Logic Circuit Design of the present invention.
Fig. 2 is the flow chart of the preferred embodiment of the verification method of Logic Circuit Design of the present invention.
Fig. 3 is the functional block diagram of the preferred embodiment of the verification device of Logic Circuit Design of the present invention.
Fig. 4 is the structural schematic diagram of the preferred embodiment of electronic equipment at least one example of the present invention.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is described in further detail.
As shown in Figure 1, Fig. 1 is the system tray of the preferred embodiment of the verification method of the realization Logic Circuit Design of the present invention
Composition.In the preferred embodiment, the system architecture diagram includes, but are not limited to：Verification platform 1 passes through interface 1 and institute
The references object 2 that verification platform 1 communicates is stated, and the object to be tested 3 communicated by interface 2 15 and the verification platform 1.
In the preferred embodiment, the verification platform 1 is generic validation methodology (Universal Verification
Methodology, UVM) verification platform 1.The UVM summarizes the common step and function of verification work, provides a set of complete
The thinking and frame of whole verification hardware logic.In addition, UVM verification platforms additionally provide abundant class library module, it is only necessary to logical
It crosses and extends these class library modules, organized according to the frame of the UVM verification platforms, you can complete building for verification platform 1.
Then it is emulated again by writing test case, completes the work of verifying logic code.The verification platform 1 has good
Autgmentability, reusability.It is therefore not necessary to directly test program be write with SystemVeilog, so as to avoid a large amount of coding work.
The verification platform 1 includes, but are not limited to：Data input module 13, reference model module 11, data outputting module
14 and data comparing module 12.The data input module 13, reference model module 11, data outputting module 14 and comparing
Module 12 is generic module, is different from unit functional module (such as generation unit 100) shown in Fig. 3.The data are defeated
The function of entering module 13, reference model module 11, data outputting module 14 and data comparing module 12 will be in subsequent embodiment
It is described in detail.
In the preferred embodiment, the object to be tested 3 is realizing algorithm (such as intelligent algorithm) with first language
Logic circuit code, i.e. Logic Circuit Design.The references object 2 is the code for the algorithm realized with second language.Its
In, the first language is different from the second language.For example, the second language includes Python, it is described to be tested right
As 3 be the logic circuit based on the Verilog algorithms write.The references object 2 is realized using Python
The code of the algorithm.The i.e. described references object 2 can realize the function of identical algorithms with the object 3 to be tested, realize algorithm
Programming language is different.
In the preferred embodiment, the interface 1 is the system function of programming language.For example, Verilog, Python
The system function of equal programming languages, the interface 2 15 is the interface of emulator, for example, SystemVerilog interface
Interface.Wherein, Python can be very good to support scientific calculation, be suitble to the various mathematical modelings of processing and operation, no
It needs that operation can be executed to list element using cycle, to the operation of matrix such as scalar, substantially increases operational efficiency.
In the preferred embodiment, the generation configuration data and excitation number that the electronic equipment passes through the verification platform 1
According to, and the configuration data and the excited data are sent to by object 3 to be tested by the verification platform 1, it is described to be tested right
As 3 configure running environment according to the configuration data, and simulation calculation is started according to the excited data, when simulation calculation terminates
Afterwards, the output data of the object to be tested 3 is obtained by the verification platform 1.
The configuration data and excited data are stored to target by the verification platform 1 and are stored by the electronic equipment
Device controls the references object 2 by the verification platform 1 and reads the configuration data and described from the target memory
Excited data, after the references object 2 obtains the configuration data, according to configuration data configuration running environment, and according to
The excited data starts simulation calculation, and after simulation calculation, the references object 2 is obtained by the verification platform 1
Output data.When the output data of the references object 2 is identical as the output data of object 3 to be tested, determine described in
Object 3 to be tested is verified；When the output data of the output data of the references object 2 and the object 3 to be tested differs,
Determine that the verification of object to be tested 3 does not pass through.
As shown in Fig. 2, being the flow chart of the preferred embodiment of the verification method of Logic Circuit Design of the present invention.According to difference
Demand, the sequence of step can change in the flow chart, and certain steps can be omitted.
S10, the electronic equipment generate configuration data and excited data by verification platform 1；
Wherein, the verification platform 1 may include that data generating function or data generate generic module.By being tested described in calling
It demonstrate,proves the data generating function of platform 1 or data generates generic module and generate configuration data and excited data.
In a preferred embodiment, the configuration data includes, but are not limited to following one or more：The verification is flat
The configuration data of the configuration data of platform 1, the configuration data of object to be tested 3, references object 2, wherein the configuration of the verification platform 1
Data are used for initializing verification environment, test pattern etc..The configuration data of the object to be tested 3 is mainly used to wait for described in initialization
Test object 3, setting operating mode etc..At the beginning of the configuration data of the object to be tested 3 includes, but are not limited to register configuration, interface
The configuration of beginning state, operating mode configuration etc..The configuration data of the references object 2 is mainly used to initialize the references object 2,
Operating mode etc. is set comprising, but be not limited to, register configuration, the configuration of interface original state, operating mode configuration etc..Institute
It states verification platform 1 and also will produce random excited data, for as algorithm in the object 3 to be tested and the references object 2
Input data, the excited data includes, but are not limited to clock, reset, input data etc..Therefore, because giving the parameter
The configuration data and excited data of object 2 and the object to be tested 3 input are identical, then the parameter object 2 and described to be tested right
As 3 input data is identical.
S11, the electronic equipment store the configuration data and excited data to target memory.
In a preferred embodiment, the target memory can be at least one processor of the electronic equipment, also may be used
To be at least one external memory being connected with the electronic equipment.
In a preferred embodiment, the electronic equipment is by the verification platform 1, with preset format by the configuration data
And excited data is preserved into text document, and store to the target memory, so that the references object 2 can be with preset format
The text document is parsed, and reads the configuration data and excited data.This ensures that the references object 2 with it is described
The input data of object 3 to be tested it is identical, ensure that the correctness of result of calculation.
The text document includes the combination of one or more of：Plain text document, binary documents, JavaScript
Object Markup Language document.
Preferably, it is pre-configured with the preset format, is included, but are not limited to：It is pre-configured in text document per a line
Storage content, such as the start information of every a line, ending message etc..
The configuration data and the excited data are sent to and are waited for by the verification platform 1 by S12, the electronic equipment
Test object 3.
In a preferred embodiment, by the data input module 13, and utilize the interface 2 15 by the configuration number
According to and the excited data be sent to the object to be tested 3.The object to be tested 3 configures operation ring according to the configuration data
Border, and according to the excited data, start simulation calculating, then output data.
S13, the electronic equipment control the references object 2 from the target memory by the verification platform 1
The configuration data and the excited data are read, so that the references object 2 starts simulation calculation.
In a preferred embodiment, the verification platform 1 may include the generic module of Process flowchart function or Process flowchart.It is logical
Cross call the generic module for generating control function or Process flowchart of the verification platform 1 generate control the references object 2 into
Journey.
In a preferred embodiment, when the verification platform 1 starts, the process for controlling the references object 2 is generated to open
The dynamic references object 2, and the references object 2 is made to detect the configuration data of the generation of the verification platform 1 and described swash
Encourage data.
It, can the persistently detection storage in the target memory by built-in function after the references object 2 starts
The configuration data and the excited data text document, and the text document is solved with the preset format
Analysis, reads the configuration data and the excited data to start simulation calculation.
S14, the electronic equipment control the references object 2 by the verification platform 1 and terminate simulation calculation.
In a preferred embodiment, described that the end simulation calculation packet of the references object 2 is controlled by the verification platform 1
It includes：Obtain the running state data of the verification platform 1；The running state data is stored with the preset format to described
So that the references object 2 is detected in target memory, when the references object 2 is detected including terminating status data
When running state data, the references object 2 terminates simulation calculation, and by the output data of the references object 2 to preset lattice
Formula is stored into the target memory.
S15, the electronic equipment obtain the output data of the references object 2 by the verification platform 1.
In a preferred embodiment, the electronic equipment is by the reference model module 11, in the target memory
The output file for detecting the references object 2 reads the reference with preset format from the output file of the references object 2
The output data of object 2, and the output data of the references object 2 is sent to the data comparing module 12.
S16, the electronic equipment obtain the output data of the object to be tested 3 by the verification platform 1.
In a preferred embodiment, the electronic equipment obtains the object to be tested 3 by the data outputting module 14
Output data, and the output data of the object 3 to be tested is sent to the data comparing module 12.
S17, the electronic equipment according to the output data of the references object 2 and the output data of the object to be tested 3,
Determine the verification result of the object to be tested 3.
In a preferred embodiment, the electronic equipment is by the data comparing module, according to the defeated of the references object 2
Go out data and the output data of the object to be tested 3, determines the verification result of the object to be tested 3.
When the output data of the references object 2 is identical as the output data of object 3 to be tested, determine described to be tested
Object 3 is verified.That is the logic circuit code of the object to be tested 3 is correct, can realize represented in the references object 2
Algorithm.
When the output data of the output data of the references object 2 and the object 3 to be tested differs, waited for described in determination
The verification of object 3 is tested not pass through.That is the logic circuit code of the object to be tested 3 is incorrect, can not achieve in the references object 2
Represented algorithm needs the logic circuit code for reminding developer to check the object to be tested 3.
The present invention generates configuration data and excited data by verification platform 1；The configuration data and excited data are deposited
It stores up to target memory；The configuration data and the excited data are sent to object 3 to be tested by the verification platform 1；
By the verification platform 1 control the references object 2 read from the target memory configuration data and it is described swash
Data are encouraged, so that the references object 2 starts simulation calculation；The references object 2 is controlled by the verification platform 1 to terminate to imitate
It is true to calculate；The output data of the references object 2 is obtained by the verification platform 1；It is obtained by the verification platform 1 described
The output data of object 3 to be tested；According to the output data of the references object 2 and the output data of the object to be tested 3, determine
The verification result of the object to be tested 3.The verification platform 1 is combined by the present invention with the references object 2, due to the ginseng
It examines object 2 and identical algorithms, and the input number of the references object 2 and the object to be tested 3 may be implemented with the object 3 to be tested
According to identical, thus it is whether identical i.e. by the output data of the determination references object 2 and the output data of the object to be tested 3
It can determine the correctness of the object to be tested 3.That is the output number of the output data and the references object 2 of the object to be tested 3
According to identical, then the object to be tested is correct (Logic Circuit Design is correct).If the output data of the object to be tested 3 and the ginseng
The output data for examining object 2 differs, then the object mistake to be tested (Logic Circuit Design mistake).Meanwhile the verification is put down
Platform 1 has good autgmentability, reusability.Without directly writing test program with SystemVeilog, so as to avoid a large amount of
Coding work improves the verification efficiency of Logic Circuit Design.
As shown in figure 3, the functional block diagram of the preferred embodiment of the verification device of Logic Circuit Design of the present invention.It is described to patrol
The verification device 16 for collecting circuit design includes generation unit 100, storage unit 101, transmission unit 102, control unit 103, obtains
Take unit 104 and comparing unit 105.The so-called unit of the present invention refer to it is a kind of can be by the verification device 16 of Logic Circuit Design
Processor it is performed and the series of computation machine program segment of fixed function can be completed, storage is in memory.At this
In embodiment, the function about each unit will be described in detail in subsequent embodiment.
The generation unit 100 generates configuration data and excited data by verification platform 1.
In a preferred embodiment, the verification platform 1 may include that data generating function or data generate generic module.Pass through
It calls the data generating function of the verification platform 1 or data to generate generic module and generates configuration data and excited data.
In a preferred embodiment, the generation unit 100 generates configuration data and excitation number by verification platform 1 at random
According to.The configuration data includes, but are not limited to following one or more：It is the configuration data of the verification platform 1, to be tested right
Configuration data, the configuration data of references object 2 as 3, wherein the configuration data of the verification platform 1 is used for initializing verification ring
Border, test pattern etc..The configuration data of the object to be tested 3 is mainly used to initialize the object to be tested 3, and operating mode is arranged
Deng.The configuration data of the object to be tested 3 includes, but are not limited to register configuration, the configuration of interface original state, operating mode
Configuration etc..The configuration data of the references object 2 is mainly used to initialize the references object 2, setting operating mode etc., packet
It includes, but is not limited to, register configuration, the configuration of interface original state, operating mode configuration etc..The generation unit 100 also passes through
Verification platform 1 generates random excited data, for as in the object 3 to be tested and the references object 2 algorithm it is defeated
Enter data, the excited data includes, but are not limited to clock, reset, input data etc..Therefore, because giving the parameter object
2 and the object to be tested 3 input configuration data and excited data it is identical, then the parameter object 2 and the object to be tested 3
Input data is identical.
The storage unit 101 stores the configuration data and excited data to target memory.
In a preferred embodiment, the target memory can be at least one processor of the electronic equipment, also may be used
To be at least one external memory being connected with the electronic equipment.
In a preferred embodiment, the storage unit 101 is by the verification platform 1, with preset format by the configuration
Data and excited data are preserved into text document, and are stored to the target memory, so that the references object 2 can be with default
Format parses the text document, and reads the configuration data and excited data.This ensures that the references object 2 with
The input data of the object to be tested 3 it is identical, ensure that the correctness of result of calculation.
The text document includes the combination of one or more of：Plain text document, binary documents, JavaScript
Object Markup Language document.
Preferably, it is pre-configured with the preset format, is included, but are not limited to：It is pre-configured in text document per a line
Storage content, such as the start information of every a line, ending message etc..
The configuration data and the excited data are sent to and are waited for by the verification platform 1 by the transmission unit 102
Test object 3.
In a preferred embodiment, the transmission unit 102 is by the data input module 13, and utilizes the interface two
The configuration data and the excited data are sent to the object to be tested 3 by 15.The object to be tested 3 is according to the configuration number
According to configuration running environment, and according to the excited data, start simulation calculating, then output data.
Described control unit 103 controls the references object 2 from the target memory by the verification platform 1 and reads
The configuration data and the excited data are taken, so that the references object 2 starts simulation calculation.
In a preferred embodiment, the verification platform 1 may include the generic module of Process flowchart function or Process flowchart.It is logical
Cross call the generic module for generating control function or Process flowchart of the verification platform 1 generate control the references object 2 into
Journey.
In a preferred embodiment, when the verification platform 1 starts, control unit 103, which generates, controls the references object 2
Process to start the references object 2, and make the references object 2 detect the verification platform 1 generation the configuration number
According to and the excited data.
It, can the persistently detection storage in the target memory by built-in function after the references object 2 starts
The configuration data and the excited data text document, and the text document is solved with the preset format
Analysis, reads the configuration data and the excited data to start simulation calculation.
Described control unit 103 controls the references object 2 by the verification platform 1 and terminates simulation calculation.
In a preferred embodiment, described control unit 103 controls the references object 2 by the verification platform 1 and terminates
Simulation calculation includes：Obtain the running state data of the verification platform 1；By the running state data with the preset format
It stores into the target memory so that the references object 2 is detected, when the references object 2 is detected including terminating
When the running state data of status data, the references object 2 terminates simulation calculation, and by the defeated of the references object 2
Go out data to store into the target memory with preset format.
The acquiring unit 104 obtains the output data of the references object 2 by the verification platform 1.
In a preferred embodiment, the acquiring unit 104 is by the reference model module 11, in the target memory
The middle output file for detecting the references object 2, the ginseng is read with preset format from the output file of the references object 2
The output data of object 2 is examined, and the output data of the references object 2 is sent to the data comparing module 12.
The acquiring unit 104 obtains the output data of the object to be tested 3 by the verification platform 1.
In a preferred embodiment, the acquiring unit 104 obtains the object to be tested 3 by the data outputting module 14
Output data, and the output data of the object 3 to be tested is sent to the data comparing module 12.
The comparing unit 105 according to the output data of the references object 2 and the output data of the object to be tested 3,
Determine the verification result of the object to be tested 3.
In a preferred embodiment, the comparing unit 105 is by the data comparing module 12, according to the references object
The output data of 2 output data and the object to be tested 3 determines the verification result of the object to be tested 3.
When the output data of the references object 2 is identical as the output data of object 3 to be tested, determine described to be tested
Object 3 is verified.That is the logic circuit code of the object to be tested 3 is correct, can realize represented in the references object 2
Algorithm.
When the output data of the output data of the references object 2 and the object 3 to be tested differs, waited for described in determination
The verification of object 3 is tested not pass through.That is the logic circuit code of the object to be tested 3 is incorrect, can not achieve in the references object 2
Represented algorithm needs the logic circuit code for reminding developer to check the object to be tested 3.
The present invention generates configuration data and excited data by verification platform 1；The configuration data and excited data are deposited
It stores up to target memory；The configuration data and the excited data are sent to object 3 to be tested by the verification platform 1；
By the verification platform 1 control the references object 2 read from the target memory configuration data and it is described swash
Data are encouraged, so that the references object 2 starts simulation calculation；The references object 2 is controlled by the verification platform 1 to terminate to imitate
It is true to calculate；The output data of the references object 2 is obtained by the verification platform 1；It is obtained by the verification platform 1 described
The output data of object 3 to be tested；According to the output data of the references object 2 and the output data of the object to be tested 3, determine
The verification result of the object to be tested 3.The verification platform 1 is combined by the present invention with the references object 2, due to the ginseng
It examines object 2 and identical algorithms, and the input number of the references object 2 and the object to be tested 3 may be implemented with the object 3 to be tested
According to identical, thus it is whether identical i.e. by the output data of the determination references object 2 and the output data of the object to be tested 3
The verification (correctness for determining the object to be tested 3) to the object 3 to be tested can be achieved.That is the output of the object to be tested 3
Data are identical as the output data of the references object 2, then the object to be tested is correct (Logic Circuit Design is correct).If described
The output data of the output data and the references object 2 of object 3 to be tested differs, then object mistake to be tested (the logic electricity
Road design mistake).Meanwhile the verification platform 1 has good autgmentability, reusability.Without directly using SystemVeilog
Test program is write, so as to avoid a large amount of coding work, improves the verification efficiency of Logic Circuit Design.
The above-mentioned integrated unit realized in the form of software function module, can be stored in one and computer-readable deposit
In storage media.Above-mentioned software function module is stored in a storage medium, including some instructions are used so that a computer
It is each that equipment (can be personal computer, server or the network equipment etc.) or processor (processor) execute the present invention
The part steps of embodiment the method.
As shown in figure 4, the electronic equipment 4 includes at least one sending device 31, at least one processor 32, at least one
A processor 33, at least one reception device 34, at least one display (not shown) and at least one communication bus.
Wherein, the communication bus is for realizing the connection communication between these components.
The electronic equipment 4 be it is a kind of can according to the instruction for being previously set or storing, it is automatic carry out numerical computations and/or
The equipment of information processing, hardware include but not limited to microprocessor, application-specific integrated circuit (Application Specific
Integrated Circuit, ASIC), programmable gate array (Field-Programmable Gate Array, FPGA), number
Word processing device (Digital Signal Processor, DSP), embedded device etc..The electronic equipment 4 may also include network
Equipment and/or user equipment.Wherein, the network equipment includes but not limited to single network server, multiple network servers
The server group of composition or the cloud being made of a large amount of hosts or network server for being based on cloud computing (Cloud Computing),
Wherein, cloud computing is one kind of Distributed Calculation, a super virtual computing being made of the computer collection of a group loose couplings
Machine.
The electronic equipment 4, which may be, but not limited to, any type, to pass through keyboard, touch tablet or voice-operated device with user
Etc. modes carry out the electronic product of human-computer interaction, for example, tablet computer, smart mobile phone, personal digital assistant (Personal
Digital Assistant, PDA), intellectual Wearable, picture pick-up device, the terminals such as monitoring device.
Network residing for the electronic equipment 4 includes, but are not limited to internet, wide area network, Metropolitan Area Network (MAN), LAN, virtual
Dedicated network (Virtual Private Network, VPN) etc..
Wherein, the reception device 34 and the sending device 31 can be wired sending ports, or wirelessly set
It is standby, such as including antenna assembly, for other equipment into row data communication.
The memory 32 is for storing program code.The memory 32 can not have physical form in integrated circuit
The circuit with store function, such as RAM (Random-Access Memory, random access memory), FIFO (First In
First Out) etc..Alternatively, the memory 32 can also be the memory with physical form, such as memory bar, TF card
(Trans-flash Card), smart media card (smart media card), safe digital card (secure digital
Card), storage facilities such as flash memory cards (flash card) etc..
The processor 33 may include one or more microprocessor, digital processing unit.The processor 33 is adjustable
With the program code stored in memory 32 to execute relevant function.For example, each unit described in Fig. 3 is stored in institute
The program code in memory 32 is stated, and performed by the processor 33, to realize a kind of authentication of Logic Circuit Design
Method.The processor 33 is also known as central processing unit (CPU, Central Processing Unit), is one piece of ultra-large collection
It is arithmetic core (Core) and control core (Control Unit) at circuit.
The embodiment of the present invention also provides a kind of computer readable storage medium, is stored thereon with computer instruction, the finger
It enables when being executed by the electronic equipment including one or more processors, electronic equipment is made to execute as described in embodiment of the method above
Logic Circuit Design verification method.
In several embodiments provided by the present invention, it should be understood that disclosed system, device and method can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the module
It divides, only a kind of division of logic function, formula that in actual implementation, there may be another division manner.
The module illustrated as separating component may or may not be physically separated, aobvious as module
The component shown may or may not be physical unit, you can be located at a place, or may be distributed over multiple
In network element.Some or all of module therein can be selected according to the actual needs to realize the mesh of this embodiment scheme
's.
In addition, each function module in each embodiment of the invention can be integrated in a processing unit, it can also
It is that each unit physically exists alone, it can also be during two or more units be integrated in one unit.Above-mentioned integrated list
The form that hardware had both may be used in member is realized, can also be realized in the form of hardware adds software function module.
It is obvious to a person skilled in the art that invention is not limited to the details of the above exemplary embodiments, Er Qie
In the case of without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present invention is by appended power
Profit requires rather than above description limits, it is intended that all by what is fallen within the meaning and scope of the equivalent requirements of the claims
Variation includes within the present invention.Should not any attached associated diagram label in claim be considered as the involved right of limitation to want
It asks.Furthermore, it is to be understood that one word of " comprising " is not excluded for other units or step, odd number is not excluded for plural number.It is stated in system claims
Multiple units or device can also be realized by software or hardware by a unit or device.Second equal words are used for table
Show title, and does not represent any particular order.
Finally it should be noted that the above examples are only used to illustrate the technical scheme of the present invention and are not limiting, although reference
Preferred embodiment describes the invention in detail, it will be understood by those of ordinary skill in the art that, it can be to the present invention's
Technical solution is modified or equivalent replacement, without departing from the spirit of the technical scheme of the invention and range.
Claims (9)
1. a kind of verification method of Logic Circuit Design, which is characterized in that the method includes：
Configuration data is generated by verification platform and excited data, the verification platform are led to by interface one with references object
Letter, is communicated by interface two with object to be tested；
The configuration data and excited data are preserved into text document with preset format and stored to target memory；
The configuration data and the excited data are sent to the object to be tested by the verification platform；
By the verification platform control the references object from the target memory with the preset format to the text
This document reads the configuration data and the excited data after being parsed, so that the references object starts simulation calculation,
The object to be tested is the logic circuit code that algorithm is realized with first language, and the references object is to realize institute with second language
The code of algorithm is stated, the first language is different from the second language；
The references object, which is controlled, by the verification platform terminates simulation calculation；
The references object is read from the output file of the references object with the preset format by the verification platform
Output data；
The output data of the object to be tested is obtained by the verification platform；
According to the output data of the references object and the output data of the object to be tested, the verification of the object to be tested is determined
As a result.
2. the verification method of Logic Circuit Design as described in claim 1, which is characterized in that the text document includes following
One or more combinations：Plain text document, binary documents, JavaScript object marking language document.
3. the verification method of Logic Circuit Design as described in claim 1, which is characterized in that the verification platform includes：Number
According to input module, reference model module, data outputting module and data comparing module；The data input module is used for will be described
Configuration data and the excited data are sent to object to be tested；The data outputting module is for obtaining the defeated of the object to be tested
Go out data, the reference model module is used to obtain the output data of the references object, and the data comparing module is used for root
According to the output data of the references object and the output data of the object to be tested, the verification result of the object to be tested is determined.
4. the verification method of Logic Circuit Design as described in claim 1, which is characterized in that described to pass through the verification platform
It controls the references object and reads the configuration data and the excited data from the target memory, so that the reference
Object starts simulation calculation：
When the verification platform starts, the process for controlling the references object is generated to start the references object, and make institute
State the text document that references object detection stores the configuration data and the excited data；And/or
It is described the references object controlled by the verification platform terminate simulation calculation include：
Obtain the running state data of the verification platform；
The running state data is stored into the target memory with preset format so that the references object is examined
It surveys and terminates status data；
When the references object detect it is described include terminating the running state data of status data when, the references object terminates
Simulation calculation, and the output data of the references object is stored with preset format into the target memory.
5. the verification method of Logic Circuit Design as described in claim 1, which is characterized in that described according to the references object
Output data and the object to be tested output data, determine that the verification result of the object to be tested includes：
When the output data of the references object is identical as the output data of object to be tested, determine that the object to be tested is tested
Card passes through；And/or
When the output data of the output data of the references object and the object to be tested differs, the object to be tested is determined
Verification does not pass through.
6. the verification method of the Logic Circuit Design as described in any one of claim 1 to 5, which is characterized in that described second
Language includes Python.
7. a kind of verification device of Logic Circuit Design, which is characterized in that the verification device includes：
Generation unit, for generating configuration data and excited data by verification platform, the verification platform by interface one and
References object is communicated, and is communicated with object to be tested by interface two；
Storage unit, for being preserved the configuration data and excited data at text document with preset format and being stored to target
Memory；
Transmission unit, it is described to be tested right for being sent to the configuration data and the excited data by the verification platform
As；
Control unit, for controlling the references object from the target memory by the verification platform with described default
Format reads the configuration data and the excited data after being parsed to the text document, so that the references object is opened
Beginning simulation calculation, the object to be tested are the logic circuit codes that algorithm is realized with first language, and the references object is with the
Two language realize the code of the algorithm；
Control unit terminates simulation calculation for controlling the references object by the verification platform；
Acquiring unit, for being read from the output file of the references object with the preset format by the verification platform
The output data of the references object；
The acquiring unit is additionally operable to obtain the output data of the object to be tested by the verification platform；
Comparing unit, described according to the output data of the references object and the output data of the object to be tested, determining
The verification result of object to be tested.
8. a kind of electronic equipment, which is characterized in that the electronic equipment includes memory and processor, and the memory is for depositing
At least one instruction is stored up, the processor is for executing at least one instruction to realize as any one in claim 1 to 6
The verification method of Logic Circuit Design described in.
9. a kind of computer readable storage medium, which is characterized in that the computer-readable recording medium storage has at least one
The logic circuit as described in any one of claim 1 to 6 is realized in instruction, at least one instruction when being executed by processor
The verification method of design.
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Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109977437B (en) * | 2017-12-27 | 2023-01-03 | 长鑫存储技术有限公司 | Verification method, device and equipment of transistor-level circuit and computer readable storage medium |
| CN108108306B (en) * | 2018-02-09 | 2021-10-15 | 苏州盛科通信股份有限公司 | Method and system for improving message analysis test coverage rate |
| CN110036367A (en) * | 2018-08-15 | 2019-07-19 | 深圳鲲云信息科技有限公司 | A kind of verification method and Related product of AI operation result |
| CN109857608A (en) * | 2018-12-27 | 2019-06-07 | 深圳云天励飞技术有限公司 | Micro-processor verification method, apparatus, electronic equipment and computer readable storage medium |
| CN111382021A (en) * | 2018-12-29 | 2020-07-07 | 深圳云天励飞技术有限公司 | Processor testing method, related device and equipment |
| CN109933948B (en) * | 2019-04-01 | 2024-02-02 | 合芯科技(苏州)有限公司 | Form verification method, device, form verification platform and readable storage medium |
| CN110457743B (en) * | 2019-06-27 | 2023-12-05 | 芯翼信息科技(上海)有限公司 | Chip detection method based on FPGA |
| CN111221693B (en) * | 2019-12-31 | 2020-10-27 | 深圳市芯天下技术有限公司 | Verification method, system, device and storage medium for NOR flash configuration module |
| CN111967209B (en) * | 2020-08-21 | 2024-06-14 | 广芯微电子（广州）股份有限公司 | SOC simulation verification method and device and storage medium |
| CN112560393B (en) * | 2020-12-17 | 2023-01-24 | 中科芯云微电子科技有限公司 | Comparison verification method and device of EDA software tool |
| CN112560401B (en) * | 2020-12-22 | 2024-04-09 | 成都海光微电子技术有限公司 | Verilog file conversion method, device, storage medium and equipment |
| CN112464500B (en) * | 2020-12-24 | 2021-10-29 | 芯天下技术股份有限公司 | Backup cell replacement circuit verification method, device, storage medium and terminal |
| CN113312879B (en) * | 2021-07-28 | 2021-11-09 | 北京燧原智能科技有限公司 | Chip circuit function verification system, method, device and storage medium |
| CN114169287B (en) * | 2021-10-22 | 2022-10-18 | 芯华章科技股份有限公司 | Method for generating connection schematic diagram of verification environment, electronic equipment and storage medium |
| CN116127886B (en) * | 2023-04-12 | 2023-06-23 | 北京燧原智能科技有限公司 | Verification method and device for memory circuit |
| CN118245309B (en) * | 2024-05-24 | 2024-07-26 | 北京开源芯片研究院 | Multi-language compatible method, device, equipment and storage medium for chip verification |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105975726A (en) * | 2016-05-27 | 2016-09-28 | 四川省豆萁科技股份有限公司 | Verification method and platform based on SystemVerilog language |
| CN106294895A (en) * | 2015-05-19 | 2017-01-04 | 上海华虹集成电路有限责任公司 | HDCP transponder controller module level function verification method and verification environment platform |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100365587C (en) * | 2004-01-05 | 2008-01-30 | 华为技术有限公司 | Adaptive wave filter logic verifying system and method |
| US7183801B2 (en) * | 2004-09-08 | 2007-02-27 | Atmel Corporation | Programmable logic auto write-back |
| CN101504690B (en) * | 2009-03-26 | 2011-04-13 | 北京航空航天大学 | Real-time simulation validation system and method for communication system integrated circuit design |
| CN101694677A (en) * | 2009-10-19 | 2010-04-14 | 上海华为技术有限公司 | Logic verification method, device and system |
| CN103150441B (en) * | 2013-03-14 | 2016-01-13 | 中山大学 | A kind of verification platform of software and hardware cooperating simulation and construction method thereof |
-
2017
- 2017-08-14 CN CN201710693558.6A patent/CN107247859B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106294895A (en) * | 2015-05-19 | 2017-01-04 | 上海华虹集成电路有限责任公司 | HDCP transponder controller module level function verification method and verification environment platform |
| CN105975726A (en) * | 2016-05-27 | 2016-09-28 | 四川省豆萁科技股份有限公司 | Verification method and platform based on SystemVerilog language |
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