CN112464500B - Backup cell replacement circuit verification method, device, storage medium and terminal - Google Patents
Backup cell replacement circuit verification method, device, storage medium and terminal Download PDFInfo
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- CN112464500B CN112464500B CN202011554831.5A CN202011554831A CN112464500B CN 112464500 B CN112464500 B CN 112464500B CN 202011554831 A CN202011554831 A CN 202011554831A CN 112464500 B CN112464500 B CN 112464500B
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Abstract
The invention discloses a verification method, a device, a storage medium and a terminal of a backup cell replacement circuit, wherein the backup cell replacement circuit is extracted and converted into a Verilog code, after replacement of a failed cell is completed, a data configuration replacement address is required to be generated randomly for simulation verification, if the simulation result is successful, the data configuration replacement address is required to be generated randomly for verification whether a replacement enabling signal is generated at the corresponding time by the address through assertion, if so, the replacement of the failed cell in a design to be tested by the backup cell replacement circuit is successful, otherwise, the replacement is failed; according to the scheme, the backup cell replacement circuit is converted into the Verilog code, so that a system can automatically and randomly generate a replacement address needing data configuration, automatically check the replacement condition, replace manual operation and greatly improve the simulation speed; and the system can randomly generate a large amount of replacement stimuli, so that the verification coverage rate is greatly increased.
Description
Technical Field
The invention relates to the technical field of nonvolatile memory verification, in particular to a backup cell replacement circuit verification method, a backup cell replacement circuit verification device, a storage medium and a terminal.
Background
In non-volatile memories, the cell backup circuit is used to replace failed bits in the memory, usually designed by simulation engineers. For the verification of the backup circuit of the memory unit, the traditional verification method generally simulates an engineer through an Hspice circuit (Hspice mainly realizes the functions of circuit description, excitation addition, output control and the like through a circuit Netlist (Netlist)), and excitation is only manually given no matter at a module level or a system level, the replacement condition is manually checked, so that the verification coverage condition is few due to manual operation, and the simulation speed is low.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a backup cell replacement circuit verification method, a device, a storage medium and a terminal, and aims to solve the problems that the existing backup circuit of a storage unit needs manual operation verification through hspice circuit simulation, so that the verification coverage rate is low and the simulation speed is slow.
The technical scheme of the invention is as follows: a backup cell replacement circuit verification method specifically comprises the following steps:
s1: extracting a backup cell replacement circuit and converting the backup cell replacement circuit into a Verilog code;
s2: opening a backup cell to replace the circuit enable;
s3: randomly generating an address needing data configuration replacement;
s4: after the replacement of the failed cell of the design to be tested is completed, carrying out simulation verification according to the randomly generated address needing data configuration replacement to obtain a simulation result;
s5: judging whether the simulation verification is successful or not according to the simulation result, if so, executing S6, and if not, executing S8;
s6: judging whether the address generates a replacement enabling signal at a corresponding moment according to the randomly generated address needing data configuration replacement, if so, executing S7, otherwise, executing S8;
s7: the backup cell replacement circuit is successfully verified, and a verification result is output;
s8: and outputting a verification result if the backup cell replacement circuit is not successfully verified.
In the verification method for the backup cell replacement circuit, in S1, the backup cell replacement circuit is extracted by software and converted into Verilog code.
According to the verification method of the backup cell replacement circuit, the backup cell replacement circuit is extracted through chipsmith software and converted into a Verilog code.
The backup cell replacement circuit verification method comprises the following steps of:
s 01: according to the randomly generated address needing data configuration replacement, writing instructions are respectively sent to the reference model and the design to be tested;
s 02: according to the randomly generated address needing data configuration replacement, respectively sending a reading instruction to the reference model and the design to be tested, and reading data written in the reference model and the design to be tested;
s 03: and judging whether the data read by the reference model is consistent with the data read by the design to be tested, if so, executing S6, and otherwise, executing S8.
In the verification method for the backup cell replacement circuit, in S6, it is determined whether the address generates a replacement enable signal at a corresponding time by assertion verification according to the randomly generated address that needs to be replaced by data configuration.
A backup cell replacement circuit verification device, comprising:
the circuit extraction module is used for extracting a backup cell replacement circuit and converting the backup cell replacement circuit into a Verilog code;
enabling the opening module, and opening the backup cell to replace the circuit to enable;
the address generation module randomly generates an address which needs to be replaced by data configuration;
the simulation verification module is used for carrying out simulation verification on the randomly generated address needing data configuration replacement after the replacement of the failed cell of the design to be tested is completed, so as to obtain a simulation result;
the first judgment module is used for judging whether the simulation verification is successful according to the simulation result;
the second judgment module is used for judging whether the address generates a replacement enabling signal at the corresponding moment according to the randomly generated address needing data configuration replacement;
and the verification result output module outputs a verification result.
The backup cell replacement circuit verification device comprises a simulation verification module and a backup cell replacement circuit verification module, wherein the simulation verification module comprises:
the writing instruction sending module is used for respectively sending writing instructions to the reference model and the design to be tested according to the randomly generated address needing data configuration replacement;
the read instruction sending module is used for respectively sending read instructions to the reference model and the design to be tested according to the randomly generated address needing data configuration replacement, and reading data written in the reference model and the design to be tested;
and the third judging module is used for judging whether the data read by the reference model is consistent with the data read by the design to be tested.
The backup cell replaces the circuit verification device, wherein the second judgment module adopts an assertion verification judgment module.
A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform any of the methods described above.
A terminal comprising a processor and a memory, the memory having stored therein a computer program, the processor being adapted to perform the method of any preceding claim by invoking the computer program stored in the memory.
The invention has the beneficial effects that: the invention provides a backup cell replacement circuit verification method, a device, a storage medium and a terminal, starting a backup cell replacement circuit converted into Verilog codes by opening the backup cell replacement circuit, replacing the failed cell of the corresponding address in the design to be tested by the backup cell replacement circuit according to the randomly generated address needing data configuration replacement, then, a write instruction is sent to the design to be tested and the reference model, then a read instruction is sent, whether the data read by the reference model is consistent with the data read by the design to be tested is judged, if so, then verifying whether the address generates a replacement enable signal at the corresponding moment by asserting according to the randomly generated address needing data configuration replacement, if so, the replacement of the failed cell in the design to be tested by the backup cell replacement circuit is successful, otherwise, the replacement is unsuccessful; according to the technical scheme, the backup cell replacement circuit is converted into the Verilog code, so that the system can automatically and randomly generate an address needing data configuration replacement, automatically check the replacement condition, replace manual operation and greatly improve the simulation speed; moreover, the system can randomly generate a large amount of replacement stimuli, and the verification coverage rate is greatly increased.
Drawings
FIG. 1 is a flowchart illustrating steps of a backup cell replacement circuit verification method according to the present invention.
Fig. 2 is a schematic diagram of a verification apparatus for a backup cell replacement circuit according to the present invention.
Fig. 3 is a schematic diagram of a terminal in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, a method for verifying a replacement circuit of a backup cell specifically includes the following steps:
s1: extracting a backup cell replacement circuit and converting the backup cell replacement circuit into a Verilog (Verilog generally refers to Verilog HDL. Verilog HDL is a hardware description language, describes the structure and the behavior of the digital system hardware in a text form, and can be used for representing a logic circuit diagram and a logic expression and also representing the logic function completed by a digital logic system) code;
s2: opening a backup cell to replace the circuit enable;
s3: randomly generating an address needing data configuration replacement;
s4: after the replacement of the failed cell of the design to be tested is completed, carrying out simulation verification according to the randomly generated address needing data configuration replacement to obtain a simulation result;
s5: judging whether the simulation verification is successful or not according to the simulation result, if so, executing S6, and if not, executing S8;
s6: judging whether the address generates a replacement enabling signal at a corresponding moment according to the randomly generated address needing data configuration replacement, if so, executing S7, otherwise, executing S8;
s7: the backup cell replacement circuit is successfully verified, and a verification result is output;
s8: and outputting a verification result if the backup cell replacement circuit is not successfully verified.
In some embodiments, in S1, the backup cell replacement circuit is extracted by software and converted into Verilog code, for example, chipsmith software is used to extract the backup cell replacement circuit.
In certain embodiments, the S4 and S5 specifically include the following steps:
s 01: according to the randomly generated address needing data configuration replacement, writing instructions are respectively sent to the reference model and the design to be tested;
s 02: according to the randomly generated address needing data configuration replacement, respectively sending a reading instruction to the reference model and the design to be tested, and reading data written in the reference model and the design to be tested;
s 03: and judging whether the data read by the reference model is consistent with the data read by the design to be tested, if so, executing S7, and otherwise, executing S9.
In some embodiments, S6 is implemented by writing assertions (when writing code, we always make assumptions that an assertion is used to capture in code; assertions are expressed as boolean expressions).
The method comprises the steps of starting a backup cell replacement circuit converted into a Verilog code by opening the backup cell replacement circuit, replacing a failed cell of a corresponding address in a design to be tested by the backup cell replacement circuit according to a randomly generated address needing data configuration replacement, sending a write instruction to the design to be tested and a reference model respectively, sending a read instruction, judging whether data read by the reference model is consistent with data read by the design to be tested, if so, verifying whether a replacement enabling signal is generated at the corresponding moment by the address through assertion according to the randomly generated address needing data configuration replacement, if so, indicating that the replacement of the failed cell in the design to be tested by the backup cell replacement circuit is successful, and otherwise, indicating that the replacement is unsuccessful.
As shown in fig. 2, a device for verifying a replacement circuit of a backup cell includes:
the circuit extraction module 101 is used for extracting a backup cell replacement circuit and converting the backup cell replacement circuit into a Verilog code;
the enabling and opening module 102 opens the backup cell to replace the circuit enable;
the address generation module 103 randomly generates an address which needs to be replaced by data configuration;
the simulation verification module 104 is used for performing simulation verification according to the randomly generated address which needs data configuration replacement after the replacement of the failed cell of the design to be tested is completed, so as to obtain a simulation result;
the first judging module 105 judges whether the simulation verification is successful according to the simulation result;
the second judging module 106 is configured to judge whether the address generates a replacement enable signal at a corresponding time according to the randomly generated address requiring data configuration replacement;
and a verification result output module 107 for outputting the verification result.
In some embodiments, the simulation verification module 104 includes:
the writing instruction sending module is used for respectively sending writing instructions to the reference model and the design to be tested according to the randomly generated address needing data configuration replacement;
the read instruction sending module is used for respectively sending read instructions to the reference model and the design to be tested according to the randomly generated address needing data configuration replacement, and reading data written in the reference model and the design to be tested;
and the third judging module is used for judging whether the data read by the reference model is consistent with the data read by the design to be tested.
Referring to fig. 3, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.
In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: s1: extracting a backup cell replacement circuit and converting the backup cell replacement circuit into a Verilog code; s2: opening a backup cell to replace the circuit enable; s3: randomly generating an address needing data configuration replacement; s4: after the replacement of the failed cell of the design to be tested is completed, carrying out simulation verification according to the randomly generated address needing data configuration replacement to obtain a simulation result; s5: judging whether the simulation verification is successful or not according to the simulation result, if so, executing S6, and if not, executing S8; s6: judging whether the address generates a replacement enabling signal at a corresponding moment according to the randomly generated address needing data configuration replacement, if so, executing S7, otherwise, executing S8; s7: the backup cell replacement circuit is successfully verified, and a verification result is output; s8: and outputting a verification result if the backup cell replacement circuit is not successfully verified.
Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.
An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: s1: extracting a backup cell replacement circuit and converting the backup cell replacement circuit into a Verilog code; s2: opening a backup cell to replace the circuit enable; s3: randomly generating an address needing data configuration replacement; s4: after the replacement of the failed cell of the design to be tested is completed, carrying out simulation verification according to the randomly generated address needing data configuration replacement to obtain a simulation result; s5: judging whether the simulation verification is successful or not according to the simulation result, if so, executing S6, and if not, executing S8; s6: judging whether the address generates a replacement enabling signal at a corresponding moment according to the randomly generated address needing data configuration replacement, if so, executing S7, otherwise, executing S8; s7: the backup cell replacement circuit is successfully verified, and a verification result is output; s8: and outputting a verification result if the backup cell replacement circuit is not successfully verified. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A backup cell replacement circuit verification method is characterized by comprising the following steps:
s1: extracting a backup cell replacement circuit and converting the backup cell replacement circuit into a Verilog code;
s2: opening a backup cell to replace the circuit enable;
s3: randomly generating an address needing data configuration replacement;
s4: after the replacement of the failed cell of the design to be tested is completed, carrying out simulation verification according to the randomly generated address needing data configuration replacement to obtain a simulation result;
s5: judging whether the simulation verification is successful or not according to the simulation result, if so, executing S6, and if not, executing S8;
s6: judging whether the address generates a replacement enabling signal at a corresponding moment according to the randomly generated address needing data configuration replacement, if so, executing S7, otherwise, executing S8;
s7: the backup cell replacement circuit is successfully verified, and a verification result is output;
s8: and outputting a verification result if the backup cell replacement circuit is not successfully verified.
2. The verification method of the backup cell replacement circuit according to claim 1, wherein in S1, the backup cell replacement circuit is extracted by software and converted into Verilog code.
3. The method of claim 2, wherein the backup cell replacement circuit is extracted by chipsmith software and converted into Verilog code.
4. The verification method of the backup cell replacement circuit according to claim 1, wherein the S4 and S5 specifically include the following steps:
s 01: according to the randomly generated address needing data configuration replacement, writing instructions are respectively sent to the reference model and the design to be tested;
s 02: according to the randomly generated address needing data configuration replacement, respectively sending a reading instruction to the reference model and the design to be tested, and reading data written in the reference model and the design to be tested;
s 03: and judging whether the data read by the reference model is consistent with the data read by the design to be tested, if so, executing S6, and otherwise, executing S8.
5. The verification method of the backup cell replacement circuit according to claim 1, wherein in S6, according to the randomly generated address that needs to be replaced by data configuration, it is determined whether the address generates a replacement enable signal at a corresponding time through assertion verification.
6. A backup cell replacement circuit verification device, comprising:
the circuit extraction module is used for extracting a backup cell replacement circuit and converting the backup cell replacement circuit into a Verilog code;
enabling the opening module, and opening the backup cell to replace the circuit to enable;
the address generation module randomly generates an address which needs to be replaced by data configuration;
the simulation verification module is used for carrying out simulation verification on the randomly generated address needing data configuration replacement after the replacement of the failed cell of the design to be tested is completed, so as to obtain a simulation result;
the first judgment module is used for judging whether the simulation verification is successful according to the simulation result;
the second judgment module is used for judging whether the address generates a replacement enabling signal at the corresponding moment according to the randomly generated address needing data configuration replacement;
and the verification result output module outputs a verification result.
7. The verification apparatus for backup cell replacement circuit as claimed in claim 6, wherein said emulation verification module comprises:
the writing instruction sending module is used for respectively sending writing instructions to the reference model and the design to be tested according to the randomly generated address needing data configuration replacement;
the read instruction sending module is used for respectively sending read instructions to the reference model and the design to be tested according to the randomly generated address needing data configuration replacement, and reading data written in the reference model and the design to be tested;
and the third judging module is used for judging whether the data read by the reference model is consistent with the data read by the design to be tested.
8. The verification apparatus for a backup cell replacement circuit as claimed in claim 6, wherein the second determination module employs an assertion verification determination module.
9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 5.
10. A terminal, characterized in that it comprises a processor and a memory, in which a computer program is stored, the processor being adapted to carry out the method of any one of claims 1 to 5 by calling the computer program stored in the memory.
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| CN106354652B (en) * | 2015-07-15 | 2019-09-27 | 上海华虹集成电路有限责任公司 | Nonvolatile memory read-write control circuit |
| CN107247859B (en) * | 2017-08-14 | 2018-11-02 | 深圳云天励飞技术有限公司 | Verification method, device, electronic equipment and the storage medium of Logic Circuit Design |
| CN109857608A (en) * | 2018-12-27 | 2019-06-07 | 深圳云天励飞技术有限公司 | Micro-processor verification method, apparatus, electronic equipment and computer readable storage medium |
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