CN112347723A

CN112347723A - ROM code extraction verification method and device based on layout

Info

Publication number: CN112347723A
Application number: CN202011198507.4A
Authority: CN
Inventors: 孟庆龙; 刘志哲; 刘宝光; 郑维维
Original assignee: Tuowei Electronic Technology Shanghai Co ltd
Current assignee: Tuowei Electronic Technology Shanghai Co ltd
Priority date: 2020-10-31
Filing date: 2020-10-31
Publication date: 2021-02-09
Anticipated expiration: 2040-10-31
Also published as: CN112347723B

Abstract

Embodiments of the present disclosure provide a layout-based ROM code extraction verification method, apparatus, device, and computer-readable storage medium. The method comprises the steps of converting a ROM layout to be extracted and verified into a circuit netlist; acquiring a circuit structure of a storage unit corresponding to binary data '0' and/or a circuit structure of a storage unit corresponding to binary data '1', and performing text comparison with the circuit structure of each storage unit in the circuit diagram; taking the comparison result of each storage unit as a ROM code corresponding to the circuit diagram; and verifying the ROM code and the sample ROM code to obtain a verification result. In this way, fast extraction and verification of ROM code can be quickly achieved.

Description

ROM code extraction verification method and device based on layout

Technical Field

Embodiments of the present disclosure relate generally to the field of computer aided design technology, and more particularly, to a layout-based ROM code extraction verification method, apparatus, device, and computer-readable storage medium.

Background

Information stored in a ROM (Read-Only Memory) can be Read Only and cannot be changed at will in a normal use condition, and stored data thereof is generated under a special condition. The ROM code is the information content stored in the ROM, and is implemented in the layout in the form of a memory cell array. The memory cell array has two kinds of memory cells, one for storing binary data '0' and one for storing binary data '1', which are implemented by different circuit structures.

In order to verify whether the ROM code in the used layout is correct, the ROM code needs to be extracted from the ROM layout by a certain technology and verified.

The existing ROM code extraction and verification method is to compare the data pattern of the ROM code by means of visual method and the like. The traditional method needs to process the graph, and the processing speed is low. Meanwhile, for scenes in which a complete layout cannot be obtained due to copyright, the conventional method is limited in use.

Disclosure of Invention

According to the embodiment of the disclosure, a layout-based ROM code extraction verification scheme is provided.

In a first aspect of the disclosure, a layout-based ROM code extraction and verification method is provided. The method comprises the following steps: acquiring a ROM (read only memory) layout to be extracted and verified, and converting the ROM layout into a circuit diagram; extracting codes of the circuit diagram to generate ROM codes; the ROM code is verified.

The aspect described above and any possible implementation manner further provide an implementation manner, where converting the ROM layout into a circuit diagram includes: and converting the ROM layout into a circuit diagram by adopting a netlist extraction tool, wherein the circuit diagram is a text file for describing a circuit structure.

The above-described aspect and any possible implementation further provide an implementation, where performing code extraction on the circuit diagram and generating ROM code includes: acquiring a memory cell circuit structure corresponding to binary data '0' and/or a memory cell circuit structure corresponding to binary data '1'; comparing the texts with the circuit structures corresponding to the storage units in the circuit diagram, and recording the comparison result; and generating a corresponding ROM code according to the comparison result.

The above-described aspects and any possible implementations further provide an implementation, and the method further includes: and comparing the circuit structure of the memory cell corresponding to the binary data '0' and the circuit structure of the memory cell corresponding to the binary data '1' with the circuit structures corresponding to the memory cells in the circuit diagram respectively, and verifying the comparison results obtained respectively.

The above-described aspects and any possible implementation further provide an implementation, wherein if the check result is incorrect, the data pattern of the corresponding memory cell in the ROM layout is boolean-anded with the data pattern of the memory cell corresponding to the binary data '0' and/or the data pattern of the memory cell corresponding to the binary data '1' to obtain the corresponding comparison result.

The above aspects and any possible implementations further provide an implementation, and the method further includes randomly selecting one or more memory cells in the ROM layout for data pattern comparison to verify the ROM code.

The above aspect and any possible implementation further provide an implementation in which verifying the ROM code includes: and comparing the ROM code with a sample ROM code to obtain a verification result.

In a second aspect of the present disclosure, a layout-based ROM code extraction verification apparatus is provided. The device includes: the circuit diagram conversion module is used for acquiring a ROM (read only memory) layout to be extracted and verified and converting the ROM layout into a circuit diagram; the code extraction module is used for extracting codes of the circuit diagram to generate ROM codes; and the verification module is used for verifying the ROM code.

In a third aspect of the disclosure, an electronic device is provided. The electronic device includes: a memory having a computer program stored thereon and a processor implementing the method as described above when executing the program.

In a fourth aspect of the present disclosure, a computer readable storage medium is provided, having stored thereon a computer program, which when executed by a processor, implements a method as in accordance with the first aspect of the present disclosure.

It should be understood that the statements herein reciting aspects are not intended to limit the critical or essential features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements, and wherein:

FIG. 1 shows a flow diagram of a layout-based ROM code extraction validation method according to an embodiment of the present disclosure;

FIG. 2 shows a schematic diagram of a method of code extraction for a circuit diagram according to an embodiment of the present disclosure;

FIG. 3 shows a block diagram of a layout-based ROM code extraction verification apparatus according to an embodiment of the present disclosure;

FIG. 4 illustrates a block diagram of an exemplary electronic device capable of implementing embodiments of the present disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

In addition, the term "and/or" herein is only one kind of association relationship describing an associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

In the method, a ROM layout to be extracted and verified is converted into a circuit netlist; acquiring a circuit structure of a storage unit corresponding to binary data '0' and/or a circuit structure of a storage unit corresponding to binary data '1', and performing text comparison with the circuit structure of each storage unit in the circuit diagram; taking the comparison result of each storage unit as a ROM code corresponding to the circuit diagram; and verifying the ROM code and the sample ROM code to obtain a verification result. The rapid extraction and verification of the ROM code are realized.

FIG. 1 shows a flowchart of a layout-based ROM code extraction verification method 100 according to an embodiment of the present disclosure.

In some embodiments, the total number of memory cells in the ROM layout is N, which is a positive integer. The ROM code is the information content stored in the ROM, and is implemented in the layout in the form of a memory cell array. The memory cell array has two kinds of memory cells, one for storing binary data '0' and one for storing binary data '1', which are implemented by different circuit structures.

At block 110, a ROM layout to be extracted and verified is obtained and converted into a circuit diagram.

In some embodiments, the ROM layout is converted to a circuit diagram using a netlist extraction tool, such as a netlist extractor. Wherein the circuit diagram is a transistor-level netlist (netlist). A netlist is used to describe the structure of a circuit, i.e., the connection of circuit elements to each other, and is typically a text file that follows some relatively simple markup syntax.

In some embodiments, to increase the translation speed, the ROM layout may be block partitioned to perform translation synchronously. The process of converting the ROM layout into the circuit diagram comprises the steps of dividing the ROM layout into modules (or not), respectively extracting netlists of each module (wire mesh extraction, correction, unit identification and correction), checking the netlists data by basic Electrical Rules (ERC), and merging the netlists of the modules (completing the lead at the seam between the modules); and deriving the generated circuit diagram. For example, the circuit diagram is as follows:

in block 120, code extraction is performed on the circuit diagram to generate ROM code;

and the code extraction is to acquire binary data corresponding to the storage unit in the circuit diagram.

In some embodiments, the following sub-steps are included:

in block 210, set i to 1;

in block 220, a circuit structure of a memory cell corresponding to the binary data '0' and/or a circuit structure of a memory cell corresponding to the binary data '1' is obtained, and compared with a circuit structure corresponding to the ith memory cell in the circuit diagram in a text manner, and a comparison result is recorded.

The circuit structure of the memory cell corresponding to the binary data '0' and/or the circuit structure of the memory cell corresponding to the binary data '1' and the circuit diagram are both in text form.

In some embodiments, binary data 0 corresponds to the memory cell circuit structure text described below, where denotes any character;

M* BL[*] WL[*] VSS VSS NMOS W＝0.1u L＝0.1u

in some embodiments, binary data 1 corresponds to a memory cell circuit structure text description, where denotes any character. When the second string is not BL [ ] or the third string is not WL [ ], which is binary data 1, three cases are distinguished:

in some embodiments, only the circuit structure of the memory cell corresponding to the binary data '0' or the circuit structure of the memory cell corresponding to the binary data '1' may be adopted for comparison with the circuit structure corresponding to the ith memory cell in the circuit diagram. Taking an example of comparing a circuit structure of a memory cell corresponding to binary data '0' with a circuit structure corresponding to an ith memory cell in the circuit diagram, if the circuit structure corresponding to the ith memory cell in the circuit diagram is the circuit structure of the memory cell corresponding to the binary data '0', and the comparison is the same, recording a comparison result corresponding to the ith memory cell in the circuit diagram as 0, and if the circuit structure corresponding to the ith memory cell in the circuit diagram is the circuit structure of the memory cell corresponding to the binary data '0', and the comparison is different, recording a comparison result corresponding to the ith memory cell in the circuit diagram as 1.

In some embodiments, a circuit structure of a memory cell corresponding to binary data '0' and a circuit structure of a memory cell corresponding to binary data '1' may be respectively compared with a circuit structure corresponding to the ith memory cell in the circuit diagram, and the comparison results obtained respectively are verified to increase the accuracy of comparison, and if the verification results are not consistent, the corresponding memory cells are re-compared. In some embodiments, if the comparison result is not consistent, whether the ROM layout to be extracted and verified is obtained in block 110 or not is considered, and an error occurs in the process of converting the ROM layout into the circuit diagram; and performing Boolean and operation on the data graph of the corresponding storage unit in the ROM layout and the data graph of the storage unit corresponding to the binary data '0' and/or the data graph of the storage unit corresponding to the binary data '1' to obtain a corresponding comparison result.

Because the circuit diagram is a text file for describing a circuit structure, the comparison speed is improved by comparing texts with the circuit structure of the memory cell corresponding to the binary data '0' and/or the circuit structure of the memory cell corresponding to the binary data '1' (the text comparison speed is much higher than the graphic comparison speed).

In block 230, i is incremented by 1, and if i is less than or equal to the total number of memory cells N, block 220 is repeated; if i is greater than the total number of memory cells N, block 240 is performed.

In block 240, corresponding ROM codes are generated based on the comparison of the memory cells in the circuit diagram. For example, the ROM code is 01001110.

In some embodiments, the total number of the memory cells in the ROM layout is N, where N is a positive integer, the ROM layout may be divided into P rows and Q columns, which total N memory cells, or i may be set to 1, and j may be set to 1, and the ith row and jth column memory cells in the circuit diagram are compared, where a specific comparison manner is similar to the comparison method described above, and is not described herein again.

In some embodiments, the comparison result of each memory cell in the circuit diagram is used as the corresponding ROM code of the circuit diagram. The ROM code is in binary code form.

In some embodiments, the ROM code is verified. For example, one or more storage units in the ROM layout to be extracted and verified are randomly selected, boolean and operation is performed on the data pattern of the storage unit corresponding to the data pattern and the binary data '0' and/or the data pattern of the storage unit corresponding to the binary data '1' to obtain a corresponding comparison result, and the comparison result obtained by comparing the data pattern is verified with the binary code of the corresponding storage unit in the ROM code.

In block 130, the ROM code is verified.

In some embodiments, the ROM code is compared to a sample ROM code to obtain a comparison result. The comparison may be that the ROM code and the sample ROM code perform a boolean and operation, and if the binary code value of the corresponding memory cell is the same as the binary code value of the corresponding memory cell in the sample ROM code, the comparison result is 1, otherwise, the comparison result is 0. If the comparison result of each corresponding storage unit is 1, the ROM code is correct, otherwise, an error exists.

In some embodiments, emulation verification may also be performed on the ROM code.

According to the embodiment of the disclosure, the following technical effects are achieved:

original data are simplified by converting the ROM layout into a netlist; the netlist is subjected to text processing, so that the processing speed is improved; the accuracy of the ROM code is ensured through graphical verification; through the text verification, the verification speed is improved; and further, the ROM code can be quickly extracted and verified.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

The above is a description of embodiments of the method, and the embodiments of the apparatus are further described below.

Fig. 3 shows a block diagram of a layout-based ROM code extraction verification apparatus 300 according to an embodiment of the present disclosure. As shown in fig. 3, the apparatus 300 includes:

the circuit diagram conversion module 310 is configured to obtain a ROM layout to be extracted and verified, and convert the ROM layout into a circuit diagram;

a code extraction module 320, configured to perform code extraction on the circuit diagram to generate a ROM code;

a verification module 330, configured to verify the ROM code.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the described module may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.

FIG. 4 shows a schematic block diagram of an electronic device 400 that may be used to implement embodiments of the present disclosure. Device 400 may be used to implement at least one of message system 104 and message arrival rate determination system 106 of fig. 1. As shown, device 400 includes a Central Processing Unit (CPU)401 that may perform various appropriate actions and processes in accordance with computer program instructions stored in a Read Only Memory (ROM)402 or loaded from a storage unit 408 into a Random Access Memory (RAM) 403. In the RAM 403, various programs and data required for the operation of the device 400 can also be stored. The CPU 401, ROM 402, and RAM 403 are connected to each other via a bus 404. An input/output (I/O) interface 405 is also connected to bus 404.

A number of components in device 400 are connected to I/O interface 405, including: an input unit 406 such as a keyboard, a mouse, or the like; an output unit 407 such as various types of displays, speakers, and the like; a storage unit 408 such as a magnetic disk, optical disk, or the like; and a communication unit 409 such as a network card, modem, wireless communication transceiver, etc. The communication unit 409 allows the device 400 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The processing unit 401 performs the various methods and processes described above, such as the

methods

200, 300. For example, in some embodiments, the

methods

200, 300 may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 408. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 400 via the ROM 402 and/or the communication unit 409. When the computer program is loaded into RAM 403 and executed by CPU 401, one or more steps of

methods

200, 300 described above may be performed. Alternatively, in other embodiments, the CPU 401 may be configured to perform the

methods

200, 300 by any other suitable means (e.g., by way of firmware).

The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a load programmable logic device (CPLD), and the like.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Further, while operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A ROM code extraction and verification method based on layout is characterized by comprising the following steps:

acquiring a ROM (read only memory) layout to be extracted and verified, and converting the ROM layout into a circuit diagram;

extracting codes of the circuit diagram to generate ROM codes;

the ROM code is verified.

2. The method of claim 1, wherein converting the ROM layout to a circuit diagram comprises:

and converting the ROM layout into a circuit diagram by adopting a netlist extraction tool, wherein the circuit diagram is a text file for describing a circuit structure.

3. The method of claim 1, wherein code extracting the circuit diagram, generating ROM code comprises:

acquiring a memory cell circuit structure corresponding to binary data '0' and/or a memory cell circuit structure corresponding to binary data '1';

comparing the texts with the circuit structures corresponding to the storage units in the circuit diagram, and recording the comparison result;

and generating a corresponding ROM code according to the comparison result.

4. The method of claim 3, further comprising:

and comparing the circuit structure of the memory cell corresponding to the binary data '0' and the circuit structure of the memory cell corresponding to the binary data '1' with the circuit structures corresponding to the memory cells in the circuit diagram respectively, and verifying the comparison results obtained respectively.

5. The method according to claim 4, wherein if the check result is incorrect, performing Boolean AND operation on the data pattern of the corresponding memory cell in the ROM layout and the data pattern of the memory cell corresponding to the binary data '0' and/or the data pattern of the memory cell corresponding to the binary data '1' to obtain the corresponding comparison result.

6. The method of claim 3, further comprising:

and randomly selecting one or more storage units in the ROM layout to carry out data pattern comparison so as to verify the ROM code.

7. The method of claim 1, wherein verifying the ROM code comprises:

and comparing the ROM code with a sample ROM code to obtain a verification result.

8. A layout-based ROM code extraction and verification device is characterized by comprising:

the circuit diagram conversion module is used for acquiring a ROM (read only memory) layout to be extracted and verified and converting the ROM layout into a circuit diagram;

the code extraction module is used for extracting codes of the circuit diagram to generate ROM codes;

and the verification module is used for verifying the ROM code.

9. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program, wherein the processor, when executing the program, implements the method of any of claims 1-7.

10. A computer-readable storage medium, on which a computer program is stored, which program, when being executed by a processor, carries out the method according to any one of claims 1 to 7.