JPH08221457A - Layout pattern generator - Google Patents

Abstract

PURPOSE: To provide a layout pattern generator which can automatically verify the ROM layout pattern data before an IC with a built-in mask ROM is produced. CONSTITUTION: A layout pattern synthesization means 7 synthesizes the ROM layout pattern data which are generated from the ROM code data by a ROM layout pattern data generation means 2 and the layout pattern data on an entire chip which are read by a layout pattern data reading means 6. Then, a logical simulation is carried out based on the net list data on an entire chip which are extracted out of the obtained ROM chip layout pattern data by a net list data extraction means 8 and the test pattern data which are read by a test pattern data reading means 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout pattern generator for creating ROM layout pattern data for writing a ROM code in an IC such as an LSI having a mask ROM.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional layout pattern generator. In the figure, reference numeral 1 is a ROM code data reading means for reading ROM code data written in a ROM block of an IC having a mask ROM, and 2 is a ROM code data reading means for converting the ROM code data read by the ROM code data reading means 1. ROM layout pattern data generating means for generating ROM rectangular layout pattern data (hereinafter referred to as ROM layout pattern data) in the ROM block. 3 is these ROM code data and ROM
Data storage means for storing layout pattern data and the like, and reference numeral 4 is a screen display means for displaying the ROM code data, ROM layout pattern data, etc. on the screen. 5 is for reading ROM code data and RO
It is a data control means for executing the overall control of the layout pattern generating device, including generation of M layout pattern data and screen display.

Further, FIG. 4 shows an IC having a built-in mask ROM.
3 is a block diagram showing a model of a logic circuit of a ROM block in FIG. In the figure, reference numeral 11 is a signal line which is a ROM address bus in the IC, and an 8-bit configuration of A0 to A7 is illustrated here. 12 is ROM
An X decoder for selecting a ROM rectangle in the X coordinate direction in the area, and 13 in the Y coordinate direction in the ROM area
It is a Y decoder for selecting an M rectangle. Reference numeral 14 is an X-direction select signal line selected by the X decoder 12 (eight lines from X0 to X7 from the right in the example shown), and 15 is a Y-direction select signal line selected by the Y decoder 13 (shown in the figure). In the example, it is Y0 to Y7 from the bottom). 16 is a select signal line 14 in the X direction and a select signal line 15 in the Y direction
The above-mentioned ROM rectangles are arranged at the respective intersections of the above, corresponding to the ROM code data, and selected by the X decoder 12 and the Y decoder 13. Further, FIG. 5 is an explanatory view showing an example of creating the ROM layout pattern data, and 17 in the drawing is ROM layout pattern data showing the layout pattern of the ROM rectangle 16 generated from the ROM code data.

Next, the operation will be described. Here, FIG.
3 is a flowchart showing a flow of operations of a conventional layout pattern generator. First, the ROM code data reading means 1 reads ROM code data for evaluation, and the read ROM code data is stored in the data storage means 3 by the data control means 5 (step ST1). Next, the ROM code data stored in the data storage means 3 is read by the data control means 5 and sent to the ROM layout pattern data generation means 2 to be converted to ROM layout pattern data and generated. The ROM layout pattern data is stored in the data storage means 3 by the data control means 5 (step ST2). Next, the data control means 5 reads the ROM layout pattern data stored in the data storage means 3 and displays it on the screen display means 4 (step ST3).

FIG. 5 shows the ROM layout pattern data 17 created in this way and displayed on the screen display means 4, and as shown in the drawing, each ROM
The rectangle 16 is arranged at a portion corresponding to each intersection of the select signal line 14 in the X direction and the select signal line 15 in the Y direction, corresponding to the read ROM code data for evaluation. The operator visually confirms the ROM layout pattern data 17 displayed on the screen of the screen display means 4 and creates the created ROM layout pattern data 17
ROM code value of any address in the
It is verified whether the ROM rectangle 16 in the M block has occurred.

Documents describing techniques related to such a conventional layout pattern generator are, for example, Japanese Patent Laid-Open No. 6-194822 and Japanese Patent Laid-Open No. 4-192822.
No. 352284, Japanese Patent Laid-Open No. 6-215070,
There is JP-A-5-314215.

[0007]

Since the conventional layout pattern generating device is constructed as described above, the ROM is used when verifying whether the read ROM code data is correctly converted into the ROM layout pattern data. The operator has to visually check the positional relationship between the code data and the ROM rectangle 16 of the ROM layout pattern data 17 displayed on the screen, which requires a great deal of time for the verification work and may cause a verification error. Not only that, but when the number of ROM rectangles 16 in the ROM block is extremely large, such as several thousand to tens of thousands, it is almost impossible to confirm all the ROM rectangles 16, and the above-mentioned visual inspection is necessary. If the inspection fails to detect a ROM layout pattern data generation error, the ROM IC products with a built-in mask ROM there is if there was a problem, such as there is a fear that is shipped as it is.

The present invention has been made to solve the above-mentioned problems, and a layout that can automatically verify ROM layout pattern data before manufacturing an IC product having a mask ROM built-in. The purpose is to obtain a pattern generator.

[0009]

A layout pattern generating device according to the present invention has an R in a ROM block read by a layout pattern data reading means.
The ROM is obtained by synthesizing the layout pattern data of the entire chip other than the OM layout pattern data and the ROM layout pattern data converted from the ROM code data by the ROM layout pattern data generation means.
Layout pattern synthesizing means for generating chip layout pattern data, netlist data extracting means for extracting netlist data by performing element confirmation and wiring recognition of the generated ROM chip layout pattern data, and read by test pattern data reading means. The test pattern data and the netlist data extracted by the netlist data extracting means are provided with logic simulation executing means for executing a logic simulation of the entire chip.

[0010]

The logic simulation means in the present invention is a ROM generated from ROM code data for evaluation.
From the ROM chip layout pattern data obtained by combining the layout pattern data and the layout pattern data of the entire chip read by the layout pattern data reading means, the netlist data of the entire chip extracted by the netlist data extracting means and the test pattern data reading A layout pattern generator capable of automatically confirming whether or not the ROM code data for evaluation operates according to a program by executing a logical simulation using the test pattern data read by the means. When it is operating properly, it is determined that there is no problem in the ROM layout pattern data, and when it is not operating correctly, it is determined that there is some problem in the ROM layout pattern data.

[0011]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a layout pattern generator according to a first embodiment of the present invention. In the figure, 1
Is a ROM code data reading means, 2 is a ROM layout pattern data generating means, 3 is a data storage means, 4
Is a screen display means, and 5 is a data control means, which are the same as or equivalent to those of the conventional one denoted by the same reference numeral in FIG.

Further, 6 is a layout pattern data reading means for reading the layout pattern data of the entire chip other than the ROM layout pattern data in the ROM block, and 7 is the layout of the entire chip read by the layout pattern data reading means 6. A layout pattern synthesizing unit that synthesizes the pattern data and the ROM layout pattern data generated by the ROM layout pattern data generating unit 2 to generate ROM chip layout pattern data based on the layout pattern of the entire chip including the ROM rectangle.
Reference numeral 8 is a netlist data extracting means for recognizing elements and wirings of the ROM chip layout pattern data generated by the layout pattern synthesizing means 7 and extracting netlist data of the entire chip which is connection information of elements. Reference numeral 9 is a test pattern data reading means for reading test pattern data for the evaluation ROM code, which is input data when executing the logic simulation of the IC, and 10 is read by the test pattern data reading means 9. It is a logic simulation executing means for executing a logic simulation of the entire chip on the IC including the ROM code based on the test pattern data and the netlist data extracted by the netlist data extracting means 8.

Next, the operation will be described. Here, FIG.
3 is a flow chart showing the flow of operation of the layout pattern generator according to this embodiment. First, the ROM code data reading means 1 reads the ROM code data for evaluation, and the read ROM code data is stored in the data storage means 3 by the data control means 5 (step ST11). Next, the layout pattern data reading unit 6 reads the layout pattern data of the entire chip other than the ROM layout pattern data in the ROM block, and the read layout pattern data is the data control unit 5.
Stored in the data storage means 3 (step ST
12). Furthermore, the test pattern data reading means 9
The test pattern data for the ROM code data for evaluation, which is input data when executing the logic simulation, is read, and the read test pattern data is stored in the data storage unit 3 by the data control unit 5. (Step ST13).

Next, the ROM code data for evaluation stored in this data storage means is read out by the data control means 5 and sent to the ROM layout pattern data generation means 2, and the ROM layout pattern data generation means 2 The ROM code data is converted to generate ROM layout pattern data, and the generated ROM layout pattern data is stored in the data storage means 3 by the data control means 5 (step ST14). Next, the ROM layout pattern data and the layout pattern data of the entire chip stored in this data storage means are read by the data control means 5 and sent to the layout pattern synthesizing means 7, and the layout pattern data synthesizing means 7 uses them. To generate ROM chip layout pattern data, and the generated ROM chip layout pattern data is stored in the data storage unit 3 by the data control unit 5 (step ST1).
5).

Next, the ROM chip layout pattern data stored in this data storage means is read out by the data control means 5 and sent to the netlist data extraction means 8, and the netlist data extraction means 8 outputs the R data.
OM chip layout pattern data is subjected to element recognition and wiring recognition, and netlist data of the entire chip, which is connection information of elements for logic simulation, is extracted,
The extracted netlist data is stored in the data storage means 3 by the data control means 5 (step ST1).
6). Next, the netlist data of the entire chip and the ROM code test pattern data for evaluation stored in the data storage means are read by the data control means 5 and sent to the logic simulation execution means 10.
The logic simulation executing means 10 executes the logic simulation of the entire chip including the ROM code (step ST16). Then, it is confirmed from the execution result of the logic simulation whether or not the operation of the ROM code of the evaluation program is performed as intended (step ST17).

[0016]

As described above, according to the present invention, the ROM layout pattern data generated from the ROM code data for evaluation and the layout pattern data of the entire chip read by the layout pattern data reading means are stored. Since it is configured to execute the logic simulation by using the netlist data of the entire chip extracted from the ROM chip layout pattern data obtained by synthesizing and the test pattern data read by the test pattern data reading means. RO for evaluation
It becomes possible to easily confirm whether or not the M code data operates according to the program, and it is possible to detect in advance a trouble at the time of ROM layout pattern data conversion which could not be verified at the time of generating the ROM layout pattern data. , ROM with defective ROM
There is an effect that a layout pattern generation device can be obtained that can prevent the IC product having the built-in IC from being produced and shipped by mistake.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a layout pattern generation device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation flow of the layout pattern generation device according to the above-mentioned embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional layout pattern generator.

FIG. 4 is a block diagram showing a model of a logic circuit of a ROM block.

FIG. 5 is an explanatory diagram showing an example of creating ROM layout pattern data.

FIG. 6 is a flowchart showing a flow of operations of a conventional layout pattern generation device.

[Explanation of symbols]

1 ROM code data reading means, 2 ROM layout pattern data generating means, 6 layout pattern data reading means, 7 layout pattern synthesizing means, 8 netlist data extracting means, 9 test pattern data reading means, 10 logic simulation executing means.

Claims (1)

[Claims] 1. R for reading ROM code data written in a ROM block of an IC having a mask ROM built-in
OM code data reading means and ROM layout pattern data generation means for converting the ROM code data read by the ROM code data reading means into ROM layout pattern data which is ROM rectangular layout pattern data in the ROM block of the IC. Layout pattern data reading means for reading layout pattern data for the entire chip other than the ROM layout pattern data in the ROM block, layout pattern data for the entire chip read by the layout pattern data reading means, and the ROM layout pattern By combining the ROM layout pattern data generated by the data generating means,
Layout pattern synthesizing means for generating ROM chip layout pattern data, which is layout pattern data for the entire chip of the IC including a ROM rectangle, and element recognition and wiring recognition of the ROM chip layout pattern data generated by the layout pattern synthesizing means. And a netlist data extracting means for extracting netlist data which is connection information of the element, and the IC
Test pattern data reading means for reading the test pattern data for performing the logical simulation of
From the test pattern data read by the test pattern data reading means and the netlist data extracted by the netlist data extracting means,
A layout pattern generation device comprising: a logic simulation executing means for executing a logic simulation of the entire chip on the IC.