JP2990155B1 - Verification test pattern design apparatus and verification test pattern design method - Google Patents

Abstract

An object of the present invention is to efficiently design and input a test pattern for verifying a circuit operation of an electronic circuit. SOLUTION: An input device 2 for giving an instruction to input a signal to each terminal of an electronic circuit for verifying an operation, a test pattern creating means 5 for performing test pattern creation control according to an input instruction from the input device 2, and a test pattern creation An arithmetic processing unit 3 for performing arithmetic processing of test pattern design in accordance with various instructions from the means 5; and a table format for inputting test patterns as processing results of the arithmetic processing unit 3 (vertical: pattern number x horizontal: table of terminal names) ) And an output device 1 for displaying a screen of a waveform format of input results (vertical: terminal name × horizontal: pattern number time chart) so that a test pattern can be designed based on a test pattern designing process. First, the input of the test pattern signal is performed on the screen in the table format, and the input result is displayed on the screen in the waveform format.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a verification test pattern designing apparatus and a verification test pattern designing method for designing a test pattern for verifying a circuit operation of an electronic circuit.

[0002]

2. Description of the Related Art An example of a conventional test pattern design method for designing a test pattern for verifying the circuit operation of an electronic circuit is described in Japanese Patent Application Laid-Open No. Hei 6-266790. In this conventional test pattern design method for verification, as shown in FIG. 18 of this publication, a test pattern is designed by means of inputting the input signal of each terminal in a waveform format in a pattern unit with a certain fixed time as one pattern. ing.

[0003]

In the waveform input method mainly used in the conventional test pattern design, there is a problem that the efficiency of design and input is low when inputting a test pattern while designing it. In the test pattern design,
In the process of deciding the input signal of each terminal for each pattern, the waveform input method is to input in the form of a waveform for each terminal, which is different from the test pattern design process. In the input method, since a final pattern is designed on a desk and then input in a waveform format for each terminal, it is difficult to input a test pattern while designing a test pattern.

[0004] It is an object of the present invention to verify a test pattern by inputting test patterns in a tabular form so that a test pattern can be input in accordance with a test pattern design process of determining an input signal of each terminal in pattern units. An object of the present invention is to provide a test pattern design apparatus and a test pattern design method for verification.

[0005]

SUMMARY OF THE INVENTION The present invention provides a test pattern design apparatus for designing a test pattern for verifying a circuit operation of an electronic circuit, in which a signal input instruction is given to each terminal of the electronic circuit. input means, a test pattern generation means for performing test pattern generation control according to the input instruction input from the input means, a calculating means for performing a calculation process of the test pattern designed by various commands from the test pattern forming means, the input Enter instructions from means
Table format where the vertical number is the pattern number and the horizontal
The test pattern input screen and the processing result of the
The time in the waveform format where the vertical is the terminal name and the horizontal is the pattern number
Output means for displaying a chart screen .

[0006] Table the test pattern generating means, for displaying the input control means for controlling the various means corresponding to said input instruction from the input means, the terminal name and the signal information of the test pattern input screen Screen control means;
The terminal name and signal information are displayed on the time chart screen.
Time chart / screen control means for displaying in the form of a terminal, terminal name input means for creating terminal name information to be displayed from the terminal name of the input instruction received by the input means, and the input instruction received by the input means Signal input means for creating signal information to be displayed from the signals of the above, test pattern reading means for reading already created test pattern data, and test pattern storage means for saving the input test pattern data. Features.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a test pattern design apparatus for verification of the present invention. The test pattern design device for verification shown in FIG. 1 includes an input device 2 in which a designer operates a keyboard, a mouse, or the like to perform an input instruction, and various information including a display of the input result and the designed test pattern on a display. An output device 1 for displaying
A data storage device 4 for storing the created test pattern data 41; and a test pattern creating means 5 for performing test pattern creation control in accordance with an input instruction input from the input device 2.
And an arithmetic processing unit 3 for performing arithmetic processing of test pattern design based on various information from the input device 2 and the data storage device 4 and various instructions from the test pattern creating means 5 and outputting the arithmetic processing result to the output device 1. ing.

The test pattern creating means 5 receives input instructions from the input device 2 and controls various corresponding means, and a table for displaying terminal names and signals on a test pattern input screen. A screen control means 52 including a time chart / screen control means 522 for displaying a terminal name, a signal, and the like input to the screen control means 521 in a time chart, and a terminal name displayed from a terminal name of an input instruction received by the input control means 51 A terminal name input unit 53 for creating information, and a signal input unit 54 for creating signal information to be displayed from a signal of an input instruction received by the input control unit 51
Test pattern reading means 55 for reading the already generated test pattern data 41 from the data storage device 4.
And test pattern storage means 56 for storing the input test pattern data.

[0010] The test pattern creation means 5 is all software (program) recorded on a recording medium.
The software is executed and processed by the arithmetic processing unit 3 to design a test pattern. A screen in a table format for inputting the test pattern (vertical: pattern number × horizontal: table of terminal names) and a waveform of the input result are displayed. A time chart (vertical: terminal name × horizontal: pattern number time chart) is displayed.

Next, the overall operation of this embodiment will be described in detail with reference to FIGS. FIG. 2 is a flowchart for explaining the operation of this embodiment. FIG. 3 is a view showing an example of a tabular screen for inputting a test pattern. FIG. 4 is a waveform screen of an input result of the test pattern. It is a figure showing an example of.

First, the screen control means 52 has a table for input.
The screen G1 and the time chart / screen G2 of the input result are displayed on the display of the output device 1 (step S10).

Next, the input control means 51 receives an input instruction from a keyboard, a mouse or the like of the input device 2 (S2).
0).

Here, when the test pattern data 41 already created exists in the data storage device 4, the test pattern reading means 55 reads the test pattern data 41 from the data storage device 4 (S50). The test pattern data is displayed on the input table / screen G1 (S83), and the test pattern data is displayed in a waveform format on the time chart / screen G2 of the input result (S93).

To input a terminal name, the terminal name input means 53 recognizes the position of the terminal name area G11 of the table / screen G1 and inputs it from the keyboard in the input device 2 (S30). In the terminal name area G1 of the table / screen G1.
1 (S81), and is also displayed in the terminal name area G21 of the time chart / screen G2 (S9).
1).

In order to input a test pattern, the signal input means 54 operates the test pattern area G1 of the table / screen G1.
When the position of No. 2 is recognized and input from the keyboard in the input device 2 (S40), a test pattern is displayed at the recognized position in the test pattern area G12 of the table / screen G1 (S8).
2) The test pattern is converted into a waveform and displayed in the waveform area G22 of the time chart / screen G2 (S91).

The test pattern is converted into a waveform according to the rule shown in the example of FIG. 5 and displayed on the time chart / screen G2.

The test pattern storage means 56 can store the test pattern data of the input flowchart (S60).

Further, when the test pattern input is completed, the input table / screen G1 and the input result time chart / screen G2 are deleted (S70).

[0020]

As described above, according to the present invention, in the test pattern design, the process of determining the input signal of each terminal for each pattern is performed in a table format (vertical: pattern number × horizontal: terminal name table). Since the input according to the test pattern design process can be performed on the screen of (1), there is an effect that the design and input of the test pattern can be efficiently performed.

Further, the present invention has an effect that the designed and inputted test pattern can be easily confirmed on a screen of a waveform format (vertical: terminal name × horizontal: pattern number time chart). In the design and input of the test pattern, the input signal of each terminal is determined for each pattern. In checking the test pattern after the design, the pattern is arranged side by side with a waveform instead of checking with 0/1 characters, and the change in signal is checked. This is because it is easy to see and confirm.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a verification test pattern design apparatus according to the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment shown in FIG.

FIG. 3 is a diagram showing an example of a tabular screen for inputting a test pattern according to the embodiment.

FIG. 4 is a diagram illustrating an example of a waveform format screen of a test pattern input result according to the embodiment;

FIG. 5 is a diagram showing an example of a waveform conversion rule in this embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Output device 2 Input device 3 Arithmetic processing unit 4 Data storage device 5 Test pattern creation means 41 Test pattern data 51 Input control means 52 Screen control means 53 Terminal name input means 54 Signal name input means 55 Test pattern reading means 56 Test pattern Storage means 521 Table / screen control means 522 Time chart / screen control means G1 Table / screen G11 Table / screen terminal name area G12 Table / screen test pattern area G2 Time chart / screen G21 Time chart / screen terminal name area G22 Waveform area of time chart / screen

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/3183 G06F 11/22 310 G06F 17/50

Claims (6)

(57) [Claims] 1. A verification test pattern designing apparatus for designing a test pattern for verifying an operation of an electronic circuit, comprising: input means for giving a signal input instruction to each terminal of the electronic circuit; and input from the input means. Test pattern creation means for performing test pattern creation control in accordance with the input instruction, arithmetic processing means for performing arithmetic processing of test pattern design by various instructions from the test pattern creation means, and inputting instructions from the input means. The vertical is the pattern number
Test pattern input screen in tabular format with numbers and terminal names next to terminals
And the vertical line, which is the processing result of the battle calculation processing means, is the terminal name, and the horizontal line is
Output means for displaying a time chart screen in a waveform format in which is a pattern number . Wherein said test pattern generating means, the table that displays the input control means for controlling the various means corresponding to said input instruction from the input means, the terminal name and the signal information of the test pattern input screen -Screen control means and terminal name and signal information are displayed on the time chart screen.
Time chart / screen control means for displaying in the form of a terminal, terminal name input means for creating terminal name information to be displayed from the terminal name of the input instruction received by the input means, and the input instruction received by the input means Signal input means for creating signal information to be displayed from the signals of the above, test pattern reading means for reading already created test pattern data, and test pattern storage means for saving the inputted test pattern data. The test pattern design device for verification according to claim 1, wherein: 3. A verification test pattern designing method for designing a test pattern for verifying an operation of an electronic circuit, wherein a step of inputting a signal input instruction from an input unit to each terminal of the electronic circuit is provided. Performing a test pattern creation control in accordance with the input instruction input from step (a), performing a test pattern design calculation process using various instructions by the test pattern creation control step, and inputting an instruction from the input means. The vertical is the pattern number
Test pattern input screen in tabular format with numbers and terminal names next to terminals
And the vertical line, which is the processing result of the war calculation processor, is the terminal name,
Displaying a time chart screen in the form of a waveform in which is a pattern number . Wherein the step of performing the test pattern creation control displays the steps for controlling the various steps corresponding to the input instruction from the input means, the terminal name and the signal information of the test pattern input screen Steps and terminal name and signal information are displayed on the time chart screen.
Displaying in the form of a terminal; generating terminal name information to be displayed from the terminal name of the input instruction received by the input means; and signal information to be displayed from the signal of the input instruction received by the input means. 4. The test pattern design method for verification according to claim 3, further comprising: creating a test pattern data; reading the already created test pattern data; and saving the input test pattern data. . 5. A recording medium on which a program for designing a test pattern for verifying operation of an electronic circuit is recorded, wherein a step of giving a signal input instruction from an input unit to each terminal of the electronic circuit is provided; Performing a test pattern creation control in accordance with the input instruction input from step (a), performing a test pattern design calculation process using various instructions by the test pattern creation control step, and inputting an instruction from the input means. The vertical is the pattern number
Test pattern input screen in tabular format with numbers and terminal names next to terminals
And the vertical line, which is the processing result of the battle calculation processing means, is the terminal name, and the horizontal line is
A step of displaying a time chart screen in a waveform format in which is a pattern number; and a program for executing the step. 6. The method of performing the test pattern creation control displays the steps for controlling the various steps corresponding to the input instruction from the input means, the terminal name and the signal information of the test pattern input screen Steps and terminal name and signal information are displayed on the time chart screen.
Displaying in the form of a terminal; generating terminal name information to be displayed from the terminal name of the input instruction received by the input means; and signal information to be displayed from the signal of the input instruction received by the input means. Creating the test pattern data, reading the already created test pattern data, saving the input test pattern data,
The recording medium according to claim 5, comprising: