JPH07141407A - Logical simulator and logical simulation method - Google Patents

Abstract

PURPOSE:To accelerate the speed of logical simulation by providing a second value storage means for storing the values of trace specified signals independent of a first value storage means for storing the values of the respective signals in a logic circuit and updating the contents of only the second means with the value of a generation signal when the event of the trace specific signal is generated. CONSTITUTION:Before executing simulation, a trace signal value list 22 for storing the values of the signals to be traced is provided independent of a value list 21 and every time the event for the signals to be traced is generated, the trace signal value list 22 is updated with the value of the signal. Then, every time the simulation of one user time is completed, the trace signal value list 22 is read and a traced result is written in a trace buffer. That is, by providing the trace signal value list 22 independent of the value list 21, the need of a process for judging the presence/absence of the trace specification of event generation signals in a machine time cycle accompanying the generation of the event is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulator and a logic simulation method used for verifying a logic circuit.

[0002]

2. Description of the Related Art In recent years, ASIC (Application Specific
It has been generalized that verification of logic circuits such as IC) is performed by a logic simulator, and time and economic costs have been significantly reduced compared to the conventional method of manufacturing a prototype and verifying it. . The logic simulator represents a circuit model in a hardware description language or a schematic, and simulates the logic (behavior) of this circuit model on a computer. An event driven method is a typical simulation method in this logic simulator.

The event driven method considers that the value of the signal in the circuit model has changed in the course of executing the simulation as the occurrence of the event, and only the circuit portion where the signal generated by the event is propagated. This is a method that advances the calculation. Therefore, according to this method, the number of calculations in the simulation execution can be suppressed to the necessary minimum, and the simulation can be executed efficiently.

Next, the event-driven simulation will be described with a specific example. FIG. 9 is a diagram showing an example of a circuit model to be simulated and an example of expressing this circuit model in a hardware description language. In the circuit model, IA, IB, IC, T
A, TB, and TC are signals, and 91, 92, and 93 are AND circuits. In the circuit model description, the logic of the AND circuit is represented by "&".

Now, all the signals IA, I in the circuit model
B, IC, TA, TB, and TC are initialized to 0.
If 1 is given to each of the signals IA and IB as an input value, the signal values of the signals IA and IB change from 0 to 1. This is the event occurrence. Then, the value of the event occurrence signal is registered in the current event buffer together with its signal name, as shown in FIG.

Next, it is assumed that the signal IA is read from the current event buffer and given to each AND circuit 91, 92 as an input value. As a result, each AND circuit 9
A simulation operation is executed when the signal IA (1) is input to the first and second terminals 92. In this case, each AND circuit 9
The values of the output signals TB and TC of 1 and 92 are both 0.
Since this is the same as the value 0 set as the initial value,
It is determined that the event has not occurred.

Next, when the signal IB is read from the current event buffer and input to the AND circuit 91, A
The output signal TB of the ND circuit 91 has a value of 1, and it is determined that an event has occurred. And the value of the event occurrence signal is
As shown in FIG. 11, it is registered in the next event buffer together with its signal name.

As described above, the value of each signal is read from the current event buffer, the simulation operation is sequentially executed, and the values of all event occurrence signals are registered in the next event buffer together with their signal names. When the above processing is completed for all the signals in the current event buffer, the current event buffer is updated with the contents of the next event buffer, and then the signal value is read again from this current event buffer and the same processing is executed. To do.

As described above, a series of cycle units from the start of the processing of the signals registered in the current event buffer to the end of the processing of all the signals are called machine time here.

By the way, in such a logic simulator, the value of a specific signal in the circuit model is traced (tracked) during the execution process of the simulation.
FIG. 12 is a flowchart showing the procedure of simulation including this trace processing.

First, the circuit model data is read and stored in a storage area dedicated to the circuit model data (step 1201). Next, various simulation commands input by the user are interpreted, and settings such as simulation end time, trace designation signal, test data, and simulation start instruction are accepted (step 120).
2). When the instruction to start the simulation is received, the value of the signal is first read from the current event buffer, and the simulation operation is executed from the value of the signal and the data of the circuit model (step 1205). Then, it is determined from the calculation result whether or not an event has occurred (step 1206), and when an event has occurred, the value of the event occurrence signal is registered in the next event buffer (step 1207). This process is performed for all signals registered in the current event buffer, and when this process is completed for all signals (step 120).
4) Assuming that the simulation for one machine time has ended, the value table is updated with each calculation result (value of the event occurrence signal) (step 1210). Next, it is checked whether or not the signal whose value is updated in the value table is trace-designated (step 1211). If the signal is trace-designated, the value of the signal is stored in the trace-specific storage area (trace buffer). ) Is recorded (step 1212).

After the end of the trace, the simulation of the next machine time is started. In this case, the current event buffer is updated with the contents of the next event buffer (step 1213), the process returns to step 1204, the value of the signal registered in the current event buffer is read, and the simulation operation is executed (step 120).
5). Similarly, the determination of event occurrence (step 12
06), registration in the next event buffer (step 1207), updating of the value table (step 1210), determination of trace designation (step 1211), recording of trace information (step 1212), updating of the next event buffer (step 1213). Repeat until the next event buffer becomes empty. When the empty of the next event buffer is detected (step 1208), the end of the simulation for one user time is judged to update the user time (step 1214), and the simulation for the next user time is executed. The above processing is repeated until the updated user time and the simulation end time match, and when the user time and the simulation end time match (step 1203), all the simulations are ended. In short, in this method, the signal value is traced only when an event occurs with respect to the trace-designated signal. Therefore, it is not necessary to record unnecessary trace information when the signal value does not change, and the limited storage area of the trace buffer can be effectively utilized.

However, according to this method, it is determined whether the signal is a trace-designated signal in machine time units as the event occurs, and if the event generation signal is a trace-designated signal, a value table is displayed. It is necessary to read the value of the signal from the device and record it in the trace buffer. Therefore, the cumulative total of these processing times throughout the simulation becomes considerably long, which is one of the causes for slowing down the entire simulation processing.

Especially in a CAD system using a hardware accelerator, the input / output processing occupies a very important part, and no matter how fast the simulation is realized, the input / output processing does not take time at all. It makes sense.

[0015]

SUMMARY OF THE INVENTION The present invention is intended to solve such a problem, and determines the presence / absence of trace designation of an event occurrence signal and the trace designation signal from a value table, which is performed in machine time units. A logic simulator and a logic simulation method that can eliminate the trace-related processing that causes a decrease in the simulation speed, such as reading and recording in the trace information recording area, and speed up the trace processing, and thus improve the overall simulation speed. It is intended to be provided.

[0016]

In order to achieve the above-mentioned object, a logic simulator of the present invention is a logic simulator for simulating a logic circuit, and model information storage means for storing model information of the logic circuit, and First value storage means for storing the value of each signal in the logic circuit, second value storage means for storing the value of the signal trace-designated in advance in the logic circuit, and every time test data is given. An operation means for executing a simulation of the logic circuit in an event driven manner based on the contents of the model information storage means, the first value storage means and the second value storage means, and the designating means during the simulation. When an event of the signal trace-designated by is generated, the contents of the second value storage means are updated with the value of this event occurrence signal. Further, when an event of a signal not designated for trace occurs, an updating means for updating the contents of the first value storing means with the value of the event occurrence signal and a simulation for inputting one test data are completed. And extraction means for extracting the contents of the second value storage means as trace information each time.

[0017]

That is, in the present invention, the second value storage means for storing the value of the trace-designated signal is provided independently of the first value storage means for storing the value of each signal in the logic circuit, and the simulation is performed. During execution, if an event of the signal specified by the trace occurs, the value of this event occurrence signal is used to generate the second
The content of only the value storage means of is updated. As a result, it is not necessary to perform the process of determining whether or not the trace of the event occurrence signal is specified, which is performed in machine time units. Also, each time the simulation for one test data input is completed,
The contents of the second value storage means are extracted as trace information. As a result, the output processing of the trace designation signal from the value table performed in machine time units becomes unnecessary. Therefore, according to the present invention, it is possible to speed up the entire simulation.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the system configuration of a logic simulator according to an embodiment of the present invention. In the figure, 1 is a CPU that controls the entire system.
A keyboard 2 is used for various command inputs to the logic simulator and other purposes. Reference numeral 3 denotes a display device such as a CRT, which displays trace information which is a simulation result and other information. Reference numeral 4 denotes a storage device, which is a circuit model storage area for storing the data of the circuit model, a value table for storing the values of each signal in the circuit model, a trace signal value table for storing the values of trace-designated signals, and a current event. Includes buffers, next event buffers, trace buffers, etc. Reference numeral 5 is a circuit model reading module, which takes in circuit model data into the circuit model storage area of the storage device 4. A simulator command interpretation module 6 interprets various commands input by the user through the keyboard 2 to control the execution of the simulation. 7 is a simulator operation module,
A circuit model simulation is executed using the circuit model data, test data, and the like. A result display module 8 controls to display the trace information as the simulation result on the display device 3. Reference numeral 9 denotes a trace signal value table creation module, which performs processing for creating a trace signal value table on the storage device 4. Reference numeral 10 denotes a trace signal value table reference module, which performs a process of reading the contents of the trace signal value table at each user time and writing the contents in the trace buffer.

FIG. 2 is a diagram showing the configurations of the value table and the trace signal value table and their relationship. In the figure, reference numeral 21 is a value table for registering the value of each signal in the circuit model. Value table 2
1 includes a signal name 21a, a signal value 21b, and a trace flag 21c. The trace flag 21c is set to "1". Reference numeral 22 is a trace signal value table.
This trace signal value table 22 shows the signal name 22a and the signal value 2
It consists of 2b. In the trace signal value table 22, only signal names designated for tracing, that is, only signal names for which the trace flag 21c is set in the value table 21 are registered. By registering the signal name 22a in the trace signal value table 22, the registration location of the value of this signal is limited only to the trace signal value table 22 thereafter, and the area of the value in which the trace flag 21c is set in the value table 21. Access to is prohibited. In the figure, "-" indicates that no value is entered.

FIG. 3 is a diagram showing the relationship between the trace buffer and the trace signal value table for each user time. 31 here
Is the trace buffer. The trace buffer 31 sequentially stores the signal name 22a and the signal value 22b registered in the trace signal value table 22 at each user time.

Next, the operation of the logic simulator of this embodiment will be described.

FIG. 4 is a flow chart showing the procedure of simulation including trace processing. First, when the logic simulator is started, the circuit model reading module 5
Is started, and the circuit model reading module 5 loads the circuit model data into the circuit model storage area of the storage device 4. At this time, a value table 21 as shown in FIG. 5 is created and stored in the storage device 4 (step 40).
1).

Next, the simulator command interpretation module 6 is activated. The simulator command interpretation module 6 interprets various commands input by the user using the keyboard 2 (step 402).

A specific example of this command input is shown in FIG.
In the figure, "SIMT" is a command that specifies the simulation end time, and here the simulation end time is "500". “TRACE” is a command for designating a signal to be traced, and here, IB and TC are designated as signal names by tracing. "P
ATTRENS "is a command for setting test data, and IA, IB, and IC are signals in the circuit model that give test data." 1,1,0 "" 0,0,
“1” “0,1,1” “1,1,1” is a set test data pattern, and the user time for inputting this is added to each test data. This is a command for instructing start.

In this way, when the signal to be traced is designated by the trace designation command, the simulator command interpretation module 6 displays the value table 21 as shown in FIG.
1 is set to the trace flag 21c of the corresponding signals IB and TC.

Next, the trace signal value table preparation module 9 is activated. The trace signal value table creation module 9 uses the trace flag 21c in the value table 21 as shown in FIG.
Is found to be 1 and the signal name 21a and the signal value 21b are extracted from the value table 21 to create a trace signal value table 22 (step 403). Then, the trace signal value table 22 is stored in the storage device 4.

After that, the simulation is started by inputting the GO command. The simulation is performed as follows. First, the value of a signal is read from the current event buffer, and a simulation operation is executed from the value of this signal and the data of the circuit model (step 406). Then, it is determined from the calculation result whether or not an event has occurred (step 407), and when an event has occurred, the value of the event occurrence signal is registered in the next event buffer (step 408). This calculation process is performed for all signals registered in the current event buffer, and when this process is completed for all signals (step 405), each calculation result (event generation signal The value table 21 or the trace signal value table 22 is updated with (value) (step 411). That is, the trace signal value table 22 is updated when an event occurs with respect to the signal for which trace is designated, and the value table 21 is updated when an event occurs with respect to a signal for which trace is not designated.

After that, the simulation of the next machine time is executed. That is, the current event buffer is updated with the contents of the next event buffer (step 4
12) Then, returning to step 405, the value of the signal registered in the current event buffer is read out and the simulation operation is executed (step 406). Similarly, determination of event occurrence (step 407), registration in next event buffer (step 408), value table 2
1 or update of trace signal value table 22 (step 41
Repeat 2) until the next event buffer is empty. When the empty of the next event buffer is detected (step 409), the trace signal value table reference module 10 is activated. As shown in FIG. 3, the trace signal value table reference module 10 reads the contents of the trace signal value table 22, that is, the signal name 22a and the signal value 22b, and registers them in the trace buffer 31 as a trace result (step 413). . After that, the user time is updated (step 414) and the simulation of the next user time is started. Then, the above processing is repeated until the updated user time and the simulation end time match, and when the user time and the simulation end time match (step 404), all simulations are ended.

The trace information registered in the trace buffer 31 is read by the result display module 8 after the completion of the entire simulation and is displayed on the display device 3 in the form as shown in FIG.

In short, in the logic simulator of this embodiment, the trace signal value table 22 for storing the values of the signals to be traced is provided independently of the value table 21 before the simulation is executed, and an event occurs for the signals to be traced. Each time, the trace signal value table 22 is updated with the value of this signal (the value table is not updated). Then, the trace signal value table 22 is read every time the simulation for one user time is completed, and the trace result is written in the trace buffer 31.

Therefore, according to this embodiment, the throughput of the entire simulation can be greatly improved as compared with the conventional case. That is, in the logic simulator of the present embodiment, by providing the trace signal value table 22 independently of the value table 21, the process of determining the presence / absence of trace designation of the event occurrence signal in the machine time cycle associated with the occurrence of the event is performed. It becomes unnecessary. Further, by reading the contents of the trace signal value table 22 as the trace information for each user time, it becomes unnecessary to output the trace designating signal from the value table 21 in the machine time cycle associated with the occurrence of the event. Therefore, by eliminating the trace-related processing in these machine time periods, it is possible to speed up the entire simulation.

By using this logic simulator, it becomes possible to efficiently deal with large-scale LSI design and to efficiently perform input / output processing with a hardware accelerator.

[0034]

As described above, according to the logic simulator and the logic simulation method of the present invention, the simulation speed, such as the process of determining the presence / absence of trace designation of the event occurrence signal and the output process of the trace designation signal, which are performed in machine time units, is performed. It is possible to eliminate the trace-related processing in machine time units, which causes a decrease in the, and realize a faster trace processing in place of this, and to speed up the entire simulation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of a logic simulator according to an embodiment of the present invention.

FIG. 2 is a diagram showing configurations of a value table and a trace signal value table and a relationship between them.

FIG. 3 is a diagram showing a relationship between a trace buffer and a trace signal value table for each user time.

FIG. 4 is a flowchart showing a procedure of simulation including trace processing in the logic simulator shown in FIG.

FIG. 5 is a diagram showing a value table in an initial state.

FIG. 6 is a diagram showing a specific example of command input.

FIG. 7 is a diagram showing a value table after setting a trace flag.

FIG. 8 is a diagram showing a display result of trace information.

FIG. 9 is a diagram showing an example of a circuit model to be simulated and a description example expressing this circuit model in a hardware description language.

FIG. 10 is a diagram showing a current event buffer.

FIG. 11 is a diagram showing a next event buffer.

FIG. 12 is a flowchart showing a procedure of simulation including trace processing in a conventional logic simulator.

[Explanation of symbols]

1 ... CPU, 2 ... Keyboard, 3 ... Display device, 4 ... Storage device, 5 ... Circuit model reading module, 6 ... Simulator command interpretation module, 7 ... Simulator operation module, 8 ... Result display module, 9 ... Trace signal value table Creation module, 10 ... Trace signal value table reference module, 21 ... Value table, 22 ... Trace signal value table, 31 ...
Trace buffer.

Claims (3)

[Claims] 1. A logic simulator for simulating a logic circuit, including model information storage means for storing model information of the logic circuit, and first value storage means for storing the value of each signal in the logic circuit. Second value storage means for storing the value of the signal trace-designated in advance in the logic circuit, and the model information storage means, the first value storage means, and the second value storage means each time test data is given. An operation means for executing the simulation of the logic circuit in an event driven manner based on each content of the value storage means; and a value of the event occurrence signal when an event of a signal trace-designated by the designation means occurs during the simulation execution. If the content of the second value storage means is updated with, and an event of a signal not designated for trace occurs, Updating means for updating the contents of the first value storage means with the value of the vent occurrence signal, and extraction of the contents of the second value storage means as trace information each time the simulation for the input of one test data is completed. A logic simulator comprising: 2. The logic simulator according to claim 1, further comprising: designating means for designating an arbitrary signal to be traced in the logic circuit, and the second value storing means based on the content designated by the designating means. A logic simulator further comprising setting means for setting. 3. A logic simulator for simulating a logic circuit, including model information storage means for storing model information of the logic circuit, and first value storage means for storing the value of each signal in the logic circuit. Second value storage means for storing a value of a signal trace-designated in advance in the logic circuit, and the model information storage means, the first value storage means, and the second value storage means each time test data is given. A step of executing a simulation of the logic circuit in an event driven manner based on the contents of the second value storage means; and, when an event of the trace designated signal occurs during the execution of the simulation, the value of the event occurrence signal is used. Updating the contents of the second value storage means, and an event of a signal not designated as trace occurs during simulation execution In this case, the step of updating the content of the first value storage means with the value of this event occurrence signal, and the content of the second value storage means is traced every time the simulation for one test data input is completed. And a step of extracting as information, a logic simulation method.