JPH09319604A - Testing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the amount of test modules and to reduce the input/output time of the test modules by transferring an initial value from a test data generator and generating the internal test data of a device to be tested. SOLUTION: For the inputted initial value, plural test data composed of an instruction string and data are generated corresponding to a specified rule by a test data generation means 12. In an expected value generation means 17, an operation in the case that the test data are inputted to a circuit 29 to be tested is simulated and plural expected values are generated. Then, the initial value and the plural expected values are inputted to a module input means 25 as modules. For the inputted initial value, the plural test data composed of the instruction string and the data are generated corresponding to the specified rule by the test data generation means 22. The plural test data are processed in the circuit 29 to be tested, the processing result and the plural expected values are compared in the circuit 29 to be tested and the result is displayed and outputted to a display means 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test system for an information processing device. The information processing device was created so that when the basic operations such as the information transfer to the memory, the register, the input / output device, etc., and the operation test of the single instruction were confirmed, all the operations of the circuits constituting the device could be confirmed It is tested by test software (hereinafter referred to as "test module").

Further, even when the information processing device in operation becomes defective, it is tested by the test module in order to collect the analysis information of the cause of the defect. However, the information processing device is a device that performs different circuit operations depending on the built-in software, and in particular, in the recent speeded-up information processing device, a plurality of arithmetic units are built in for speeding up, Alternatively, since many high-speed circuits such as a plurality of cache circuits are built in, it is difficult to manually generate a test module that covers a combination of different instruction sequences, data, data storage positions, and the like.

In order to solve this problem, it is necessary to automatically generate a test module by a test data generating device.

[0004]

2. Description of the Related Art Regarding the prior art, referring to FIGS. 5 to 7, (a) the configuration of a conventional test system, and (b)
The processing flow of the conventional test system will be described in this order.

[0005] In the following description, the same or corresponding portions are denoted by the same reference characters. (A) Configuration of Conventional Test System The configuration of a conventional test system will be described with reference to FIG.

In FIG. 5, 10 'is a test data generator, 20' is a device under test, 29 is a circuit under test, 30 is a first memory circuit, and 31 is a first initial circuit. A value holding unit, 32 is a first test data generating unit, 33 is a first test data holding unit, and 34 is a first test data holding unit.
Is a first expected value storage unit, 37 is an expected value generation unit, 40 is a second storage circuit, 43 is a second test data storage unit, and 44 is a second expected value storage unit. Section, 48 is a result holding section, 50 is an input circuit,
Reference numeral 60 is a processor circuit, 75 'is a module output circuit, 76 is a module input circuit, 80 is a file circuit, and 90 is a display circuit.

The test data generator 10 'comprises a first memory circuit 30, an input circuit 50, a processor circuit 60 and a module output circuit 75', and a file circuit 80.
A plurality of test data consisting of a plurality of instruction sequences and data according to a specific rule based on the initial value input from the input circuit 50, and the plurality of test data are The circuit under test 29 is simulated by simulating the operation of the circuit under test 29 when input to the test circuit 29.
Is a device that generates a plurality of data output from the device as a plurality of expected values and outputs the plurality of test data and the plurality of expected values to the file circuit 80 as a test module.

The device under test 20 'is composed of a circuit under test 29, a second memory circuit 40, a module input circuit 76 and a display circuit 90, and is connected to the file circuit 80. A plurality of test data in the test module input from 76 are output to the second test data holding unit 43, a plurality of expected values are output to the second expected value holding unit 44, and the second test data are output. The plurality of test data read from the holding unit 43 is input to the circuit under test 29, the processing result output from the circuit under test 29 is output to the result holding unit 48, and read from the result holding unit 48. This is a device in which the circuit under test 29 compares the processing result with the plurality of expected values read from the second expected value holding unit 44, and the comparison result is displayed and output by the display circuit 90.

The circuit under test 29 is connected to the second memory circuit 40, the module input circuit 76 and the display circuit 90,
This is a circuit that is operated and tested by the program stored in the second memory circuit 40.

The first memory circuit 30 is a memory circuit that is connected to the input circuit 50, the processor circuit 60, and the module output circuit 75 ', and stores programs and data for operating the processor 60.

The second memory circuit 40 is connected to the circuit under test 29, the module input circuit 76 and the display circuit 90,
The memory circuit stores a program for operating the circuit under test 29 and data.

The input circuit 50 is a circuit which is connected to the first memory circuit 30, the processor circuit 60 and the module output circuit 75 'and receives an initial value. The processor circuit 60 is a circuit that is connected to the first storage circuit 30, the input circuit 50, and the module output circuit 75 ′, operates according to a program stored in the first storage circuit 30, and outputs a test module.

The module output circuit 75 'is connected to the first memory circuit 30, the input circuit 50, the processor circuit 60, and the file circuit 80, and uses a plurality of test data and a plurality of expected values as a test module for the file circuit 80. It is a circuit that outputs to.

The module input circuit 76 is the circuit under test 2
9 is connected to the second storage circuit 40, the file circuit 80, and the display circuit 90, and transfers the test module read from the file circuit 80 to the second storage circuit 40.

The file circuit 80 is connected to the test data generator 10 'and the device under test 20', stores the test module generated by the test data generator 10 ', and the test module is the device under test 20'. Circuit that is transferred to.

The display circuit 90 is connected to the circuit under test 29, the second memory circuit 40 and the module input circuit 76,
This is a circuit for displaying and outputting the result of testing the circuit under test 29.

The first initial value holding unit 31 is an area provided in the first storage circuit 30 for holding the initial value input by the input circuit 50. The first test data generation unit 32 holds the first storage circuit 30 to operate the processor circuit 60, and generates a plurality of test data including an instruction sequence and data from the initial value based on a specific rule. Then, the program stores the plurality of test data in the first test data holding unit 33.

The first test data holding section 33 is an area provided in the first storage circuit 30 for holding a plurality of test data. The first expected value holding unit 34 is an area that is provided in the first storage circuit 30 and holds a plurality of expected values.

The first expected value generator 37 is held in the first memory circuit 30 and operates the processor circuit 60 to input the plurality of test data to the circuit under test 29. It is a program that simulates an operation, generates a plurality of expected values that are output as a result, and stores the expected values in the first expected value holding unit 34.

The second test data holding section 43 is an area provided in the second memory circuit 40 for holding a plurality of test data. The second expected value holding unit 44 is an area that is provided in the second storage circuit 40 and holds a plurality of expected values.

The result holding section 48 is provided with the second memory circuit 40, and the plurality of test data are stored in the circuit under test 29.
This is an area for holding the processing result output from the circuit under test 29 when input to the. (B) Process Flow of Test System of Conventional Example A process flow of the test system of the conventional example will be described with reference to FIGS. 6 to 7.

The input initial value is stored in the first initial value holding unit 31 by the input circuit 50. (Step S
1) The first test data generation unit 32 that operates the processor circuit 60 reads the initial value from the first initial value holding unit 31, and a plurality of tests including an instruction sequence and data based on a specific rule. Data is generated and stored in the first test data holding unit 33. (Step S2) By the expected value generation unit 37 that operates the processor 60,
A plurality of test data are read out from the first test data holding section 33, and the plurality of test data are read out from the circuit under test 2
The operation of the circuit under test 29 when input to 9 is simulated, and the results are output as a plurality of expected values and stored in the first expected value holding unit 34. (Step S3) The plurality of test data read from the first test data holding unit 33 and the plurality of expected values read from the first expected value holding unit 34 are the module output circuit 75 as a test module. Is output to the file circuit 80. (Step S4) The test module is read from the file circuit 80,
A plurality of test data are transferred to the second test data holding circuit 43 via the module input circuit 76, and a plurality of expected values are transferred to the second expected value holding circuit 44. (Step S5) The plurality of test data read from the second test data holding unit 43 is input to the circuit under test 29, and the processing result output from the circuit under test 29 is stored in the result holding unit 48. (Step S6) The processing result read from the result holding unit 48 and the second
The circuit under test 29 compares the plurality of expected values read out from the expected value holding unit 44, and if the comparison results match, the display circuit 90 indicates that the circuit under test 29 is operating normally. If the comparison result is different, the circuit under test 29 is displayed and output to the display circuit 90 indicating that the circuit under test 29 is not operating normally, and the process is terminated. (Step S7)

[0023]

As described above, the test data generator outputs a plurality of instruction sequences, data, and expected values to the file circuit as a test module, and the device under test generates a plurality of instruction sequences and data. It was necessary to input the test module consisting of the expected value from the file circuit.

However, as the internal circuit of the information processing apparatus becomes more complicated, the pattern of test modules increases, so that a large capacity file circuit for storing a large number of test modules is required, and the input to the file circuit is increased. There is a problem that the time required for output increases.

It is an object of the present invention to provide a test system in which the number of test modules is reduced and the time required for input / output of the test module is reduced in a short time with a small capacity file circuit.

[0026]

SUMMARY OF THE INVENTION The present invention focuses on the fact that test data is automatically generated from a fixed amount of initial values based on a specific rule. The same test data generating means is provided in advance in the device under test, and instead of transferring the test data as a test module from the test data generating device to the device under test, the initial value is transferred from the test data generating device to the device under test to be tested. By generating test data inside the device, the amount of test modules is reduced,
The test system is configured to reduce the input / output time of the test module.

The principle of the present invention will be described with reference to FIG. The same or corresponding parts as described in the description of the conventional example will be denoted by the same reference numerals, and the parts newly described in the present description will be described with the new reference numerals.

In FIG. 1, 10 is a test data generator, 11 is a first initial value holding means, 12 is a first test data generating means, and 13 is a first test data holding means. Yes, 14 is a first expected value holding unit, 15 is a module output unit, 16 is an input unit, 17 is an expected value generation unit, 20 is a device under test, and 21 is a second unit. Is an initial value holding means of
Is a second test data generating means, 23 is a second test data holding means, 24 is a second expected value holding means, 25 is a module input means, 26 is a display means, 28 is a result holding means, 29 is a circuit under test, and 80 is a file circuit.

The test data generating device 10 comprises a first initial value holding means 11, a first test data generating means 12, and a first test value generating means 12.
Test data holding means 13 and first expected value holding means 1
4, a module output unit 15, an input unit 16, and an expected value generation unit 17, which are connected to the file circuit 80 to generate a plurality of test data based on the input initial values. Is input to the circuit under test 29, the operation of the circuit under test 29 is simulated to generate and output a plurality of expected values, and the initial value and the plurality of expected values are used as a test module in a file circuit. 8
This is a device that outputs 0.

The device under test 20 has a second initial value holding means 21, a second test data generating means 22, a second test data holding means 23, a second expected value holding means 24 and a module input means 25. Display means 26 and result holding means 28
Connected to the file circuit 80, transfers the initial value from the file circuit 80 to the second initial value holding means 21 via the module input means 25, and outputs a plurality of expected values to the second expected value. 2 to the expected value holding means 24 to generate a plurality of test data from the initial value
Stored in the test data holding means, the plurality of test data read from the second test data holding means is input to the circuit under test 29, and the processing result output from the circuit under test 29 is stored in the result holding means 28. Result storage means 2
8 is a device for comparing the processing result read from 8 with the plurality of expected values read from the second expected value holding means 24 and displaying / outputting the comparison result on the display means 26.

The first initial value holding means 11 is the input means 1
It is a means for holding the initial value input via 6.
The first test data generating means 12 is a means for reading the initial value held in the first initial value holding means 11 to generate a plurality of test data and storing it in the first test data holding means 13.

The first test data holding means 13 has a first
It is a means for holding the test data generated by the test data generating means 12 of FIG. First expected value holding means 1
Reference numeral 4 is a means for holding a plurality of expected values generated by the expected value generating means 17. The module output means 15 is
The initial value held in the first initial value holding means 11 and the first value
It is a means for outputting the plurality of expected values held in the expected value holding means 14 of FIG.

An initial value is input to the input means 16 and the first value is input.
This means is stored in the initial value holding means 11. The expected value generating means 17 simulates the operation of the circuit under test 29 when the plurality of test data read from the first test data holding means 13 is input to the circuit under test 29, and the plurality of expected values are obtained. Is generated and output, and is set in the first expected value holding means 14.

The second initial value holding means 21 is a means for holding the initial value transferred from the file circuit 80 via the module input means 25. The second test data generation unit 22 is a unit that generates a plurality of test data from the initial value held in the second initial value holding unit and stores the test data in the second test data holding unit 23.

The second test data holding means 23 has a second
It is a means for holding a plurality of test data generated by the test data generating means 22. The second expected value holding means 24 is a means for holding a plurality of expected values transferred via the module input means 25.

The module input means 25 transfers the initial value from the file circuit 80 to the second initial value holding means 21,
It is a means for transferring a plurality of expected values to the second expected value holding means 24.

The display means 26 is a means for displaying and outputting the comparison result output from the circuit under test 29. The result holding means 28 is a means for holding the processing result output from the circuit under test 29.

The circuit under test 29 receives the plurality of test data read from the second test data holding means, outputs the processing result to the result holding means 28, and reads the result from the result holding means 28. The processing result is compared with a plurality of expected values read from the second expected value holding means 24, and the comparison result is displayed and output on the display means 26.

Next, the flow of processing will be described. The initial value input from the input unit 16 is held in the first initial value holding unit 11.

The initial value held in the first initial value holding means 11 is read by the first test data generating means 12 and a plurality of test data consisting of an instruction string and data is generated according to a specific rule. And output to the first test data holding means 13.

The expected value generating means 17 reads a plurality of test data from the first test data holding means 13 and simulates the operation of the circuit under test 29 when the test data is input to the circuit under test 29. Then, a plurality of expected values are generated and output to the first expected value holding means 14.

The initial value held in the first initial value holding means 11 and the plurality of expected values held in the first expected value holding means 14 are read by the module output means 15,
It is output to the file circuit 80.

The initial value and a plurality of expected values held in the file circuit 80 are read by the module input means 25, the initial value is transferred to the second initial value holding means 21, and the plurality of expected values are stored. It is transferred to the second expected value holding means 24.

The initial value held in the second initial value holding means 21 is read by the second test data generating means 22 and a plurality of test data consisting of an instruction string and data is generated according to a specific rule. And output to the second test data holding means 23.

The plurality of test data held in the second test data holding means 23 is read by the circuit under test 29, and the processing result output from the circuit under test 29 is stored in the result holding means 28.

The result held in the result holding means 28 and the plurality of expected values held in the second expected value holding means 24 are read by the circuit under test 29, and the comparison result is displayed on the display means 26. Is output.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG.
4A to 4C, description will be made in the order of (a) configuration of the test system according to the embodiment of the present invention, and (b) flow of processing according to the embodiment of the present invention.

The same or corresponding portions as those described in the description of the conventional example and the principle of the present invention are denoted by the same reference numerals, and portions newly described in the present description are denoted by new reference numerals. Will be explained. (A) Embodiment of the present invention Configuration of test system An example of the configuration of the test system of the present invention will be described with reference to FIG.

In FIG. 2, 10 is a test data generator, 20 is a device under test, 29 is a circuit under test, 30 is a first memory circuit, and 31 is a first initial value holding unit. Part, 32 is a first test data generation part, 33 is a first test data holding part, 34 is a first expected value holding part, 37 is an expected value generation part,
40 is a second memory circuit, 41 is a second initial value holding unit, 42 is a second test data generation unit, and 4
3 is a second test data holding unit, 44 is a second expected value holding unit, 48 is a result holding unit, 50 is an input circuit, 60 is a processor circuit, and 75 is a module output. Reference numeral 76 is a circuit, 76 is a module input circuit, 80 is a file circuit, and 90 is a display circuit.

The test data generating apparatus 10 is composed of the first memory circuit 30, the input circuit 50, the processor circuit 60 and the module output circuit 75, and is connected to the file circuit 80. Based on the input initial value, a plurality of test data consisting of an instruction sequence and data is generated according to a specific rule, and the operation of the circuit under test 29 when the plurality of test data are input to the circuit under test 29. Is simulated to generate a plurality of expected values, and the initial value and the plurality of expected values are output to the file circuit 80 as a test module.

The device under test 20 includes a circuit under test 29 and a second circuit under test.
Memory circuit 40, module input circuit 76, and display circuit 9
0, which is connected to the file circuit 80 and has an initial value of the second initial value holding unit 41 in the test module input from the module input circuit 76.
Is output to the second expected value holding unit 44, and based on the initial value read from the initial value holding unit 41, the second test data generation unit 42 performs a plurality of tests. Data is generated and the second test data holding unit 4
3, the plurality of test data read from the second test data holding unit 43 is input to the circuit under test 29, the processing result is output to the result holding unit 48, and read from the result holding unit 48. The circuit under test 29 compares the processed result and the plurality of expected values read from the second expected value holding unit 44, and the comparison result is displayed by the display circuit 90.
Is a device that is displayed and output by.

The module output circuit 75 is connected to the first memory circuit 30, the input circuit 50, the processor circuit 60, and the file circuit 80, and outputs the initial value and a plurality of expected values to the file circuit 80 as a test module. Circuit.

The module input circuit 76 is the circuit under test 2
9 is connected to the second storage circuit 40, the file circuit 80, and the display circuit 90, and transfers the test module read from the file circuit 80 to the second storage circuit 40.

The file circuit 80 is connected to the test data generator 10 and the device under test 20, and stores the test module generated by the test data generator 10.
The test module is a circuit transferred to the device under test 20.

The second initial value holding unit 41 is an area provided in the second storage circuit 40 for holding the initial value input by the module input circuit 76. The second test data generation unit 42 holds the second memory circuit 40 to operate the circuit under test 29 to generate a plurality of test data including an instruction sequence and data from the initial value based on a specific rule. It is a program for generating and storing the plurality of test data in the second test data holding unit 43. (B) Process Flow of Embodiment of the Present Invention A process flow of the test system of the present invention will be described with reference to FIGS.

The input initial value is stored in the first initial value holding unit 31 by the input circuit 50. (Step S
1) Test data generator 3 for operating the processor circuit 60
2, the initial value is read from the first initial value holding unit 31, a plurality of test data consisting of an instruction sequence and data is generated based on a specific rule, and stored in the first test data holding unit 33. To be done. (Step S2) By the expected value generation unit 37 that operates the processor 60,
A plurality of test data are read out from the first test data holding section 33, and the plurality of test data are read out from the circuit under test 2
9 is simulated, the expected value is generated, and the first expected value holding unit 34 is simulated.
Stored in. (Step S3) The initial value read from the first initial value holding unit 31 and the plurality of expected values read from the first expected value holding unit 34 are used as test modules by the module output circuit 75 by the file circuit. 80 is output. (Step S4) The test module is read from the file circuit 80,
The initial value is transferred to the second initial value holding unit 41 via the module input circuit 76, and the plurality of expected values are transferred to the second expected value holding circuit 44. (Step S5) The circuit under test 29 is operated by the second test data generation unit 42, the initial value is read from the second initial value holding unit 41, and the instruction sequence and data generated based on a specific rule are stored. A plurality of test data consisting of is generated and output to the second test data holding unit 43. (Step S6) The plurality of test data read from the second test data holding unit 43 is input to the circuit under test 29, and the processing result output from the circuit under test 29 is stored in the result holding unit 48. (Step S7) The processing result read from the result holding unit 48 and the second
The circuit under test 29 compares the plurality of expected values read from the expected value holding unit 44 of No. 1 with each other, and if the comparison results match, the display circuit 90 displays that the circuit under test 29 is operating normally. If the comparison result is different, the circuit under test 29 is displayed and output to the display circuit 90 indicating that the circuit under test 29 is not operating normally, and the process is terminated. (Step S8) In this description, the test module is temporarily set to the file circuit 80 between the test data generating device 10 and the device under test 20.
However, in the case where the amount of test modules is small and the test data generating device 10 and the device under test 20 are close to each other, it is possible to transfer the test modules without going through the file circuit 80. .

[0057]

As described above, according to the present invention, the test module output from the test data generating device and input to the device under test can be reduced to an initial value and a plurality of expected values. The file circuit that holds the data transferred between the device and the device under test has a small capacity,
There is an industrial effect that the time required for input / output of the test module can be reduced.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a flowchart (part 1) of the embodiment of the present invention;

FIG. 4 is a flowchart of an embodiment of the present invention (part 2).

FIG. 5 is a block diagram of a conventional example

FIG. 6 is a flowchart of a conventional example (No. 1)

FIG. 7 is a flowchart of a conventional example (No. 2)

[Explanation of symbols]

 10, 10 'Test data generating device 11 First initial value holding means 12 First test data generating means 13 First test data holding means 14 First expected value holding means 15 Module output means 16 Input means 17 Expected value Generation means 20, 20 ′ Device under test 21 Second initial value holding means 22 Second test data generation means 23 Second test data holding means 24 Second expected value holding means 25 Module input means 26 Display means 28 Results Holding means 29 Circuit under test 30 First memory circuit 31 First initial value holding unit 32 First test data generating unit 33 First test data holding unit 34 First expected value holding unit 37 Expected value generating unit 40 Second storage circuit 41 Second initial value holding unit 42 Second test data generation unit 43 Second test data holding unit 44 Second expected value Holding unit 48 Result holding unit 50 Input circuit 60 Processor circuit 75, 75 'module output circuit 76 Module input circuit 80 File circuit 90 Display circuit

Claims (3)

[Claims] 1. A plurality of instruction sequences and data are generated from an input initial value based on a specific rule, and a circuit operation of a circuit under test is simulated with the plurality of instruction sequences and data as inputs. An expected value is generated, a test data generation device in which the initial value and the expected value are output as a test module, and a circuit under test is incorporated, and the initial value and the expected value are input as a test module, and A plurality of instruction sequences and data are generated based on the specific rule based on the input initial value, and the result and the expected value when the instruction sequence and data are input to the circuit under test and output. A test system consisting of a device under test that is compared and the comparison result is displayed and output. 2. An input means for inputting an initial value, a first initial value holding means for holding the initial value, and a specific rule for reading the initial value from the first initial value holding means. A first test data generating means for generating a plurality of instruction sequences and data based on the first test data retaining means for retaining the plurality of instruction sequences and data; Expected value generation means for reading out a plurality of instruction sequences and data to simulate a circuit operation of the circuit under test to generate a plurality of expected values, and first expected value holding means for holding the plurality of expected values. The test system according to claim 1, further comprising a test data generation device configured to include a module output unit that outputs the initial value and the plurality of expected values as a module. 3. A module input means for inputting an initial value and a plurality of expected values as a module, a second initial value holding means for holding the initial value, and a second for holding a plurality of expected values. Expected value holding means, second test data generating means for reading the initial value from the second initial value holding means and generating a plurality of instruction sequences and data based on a specific rule, and the plurality of instruction sequences And a data, and a second test data holding means, the plurality of instruction sequences and the data are read from the second test data holding means, the processing result is output to the result holding means, and the result holding means A circuit under test that reads out the processing result, reads out the plurality of expected values from the second expected value holding means, compares them with the processing result, and outputs a comparison result, and a display that displays and outputs the comparison result. Means The test system according to claim 1, further comprising a device under test.