JP2004145670A - Method and device for generating test bench, and computer program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and device for generating a test bench, and a computer program, enabling simplifying description for generating the test bench. <P>SOLUTION: A test bench generation easing assembly language (ALET: Assembly Language to Ease Testbench) enabling specifying time for execution of a test instruction for verifying a circuit designed using a hardware description language or a system description language at a relative time from execution of one or a plurality of program instructions to be executed on the circuit for executing simulation of the circuit is developed by describing the test instruction on a program file on which the program instructions are described in an assembly language with being related to the predetermined program instructions. Part of the ALET language is extracted from the program file, and a test bench for executing the test instruction at the predetermined time starting from execution of the related program instructions is automatically generated. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for generating a test bench for simulating a circuit designed using a hardware description language or a system description language, a test bench generation apparatus for realizing the method, and a computer for the test bench generation apparatus. The present invention relates to a computer program to be realized as.
[0002]
[Prior art]
Various types of circuits such as ICs or LSIs for realizing semiconductor devices such as CPUs and memories have been developed and used in terms of their functions and scale. At present, a circuit design uses a hardware description language (hereinafter referred to as HDL), which is a language for describing hardware operation or a logical configuration, etc., according to a request for shortening a design period or facilitating verification. It has become common practice. In recent years, a circuit design method using a system description language such as C language having a higher degree of abstraction than HDL has also been developed.
[0003]
When designing a circuit using HDL or a system description language, it is necessary to perform a simulation of the operation and the logical configuration of the circuit described in the HDL or the system description language, and verify the design. FIG. 17 is a conceptual diagram showing an outline of a conventional simulation. At the time of a conventional simulation, as information, a circuit description file describing the operation and logical configuration of a circuit using HDL or a system description language, a program file describing a program to be executed by the circuit in an assembly language, and A test bench is prepared that describes the contents of the process for verifying the operation of the circuit. The test bench describes an input signal input to the circuit, a predicted value to be taken by a predetermined signal in the circuit when the circuit operates normally, and the like. In the simulation, a program file is processed by an assembler to generate a machine language file.The generated machine language file, circuit description file, and test bench are input to the simulator, and the simulator simulates the operation of the circuit. A result indicating whether the operation was successful is output. The circuit designer corrects the designed circuit based on the output result.
[0004]
[Patent Document 1]
JP 2001-306648 A
[0005]
[Problems to be solved by the invention]
Conventionally, in the simulation at the time of designing a circuit, an input signal to be input to a circuit to be designed, a predicted value to be taken by a predetermined signal in the circuit when the circuit operates correctly, and a simulation of a circuit operating at a predetermined time. A test instruction for verifying the value of the signal needs to be described in the test bench. Furthermore, the specification of the time is represented by an absolute time calculated from the start of the simulation, and the verification time must be strictly specified in accordance with the operation of the circuit. There is a problem that description is required. To create a test bench, it is necessary to describe a predicted value of a signal and the setting of an input signal in association with a test instruction specifying a time, and the amount of description of the test bench increases as the scale of a circuit increases. Creating a test bench with a complex description and a large amount of description by hand is extremely labor-intensive, and has the problem that more time must be spent writing the test bench than designing the circuit itself. .
[0006]
The present invention has been made in view of such circumstances, and an object of the present invention is to associate a test instruction with each program instruction in a program file in which a program instruction operating on a circuit is described in an assembly language. Test bench that generates test benches by extracting test instructions associated with each program instruction and generating a test bench when simulating a circuit. An object of the present invention is to provide a generation method, a test bench generation device, and a computer program.
[0007]
[Means for Solving the Problems]
A test bench generation method according to a first aspect of the present invention uses a computer having a storage unit and an operation unit to simulate the operation of a logic-designed circuit, using one or more computers to be executed on the circuit. A method for generating a test bench describing a procedure for verifying the operation of the circuit from a program file in which program instructions are described in a format that directly defines the operation of the circuit, the method comprising calculating a test bench from execution of a predetermined program instruction Storing the program file in which a test instruction for inspecting a value of predetermined information processed in the circuit at the predetermined timing in association with the program instruction is stored in a storage unit; An input signal file defining input signals to be input is stored in the storage unit, and the text file included in the program file is stored in the storage unit. The operation instruction is extracted from the program file by the operation unit while the test instruction is associated with the program instruction associated with the test instruction, the test bench file is generated by the operation unit, and stored in the storage unit. The content expressing the input signal defined in the input signal file is written into the test bench file by the arithmetic unit, and the content indicating that the program command indicates the time at which the simulation was called in the simulation is written. And writing the test instruction to the test bench file at a predetermined timing calculated from a time at which the program instruction associated with the test instruction is called in the simulation by an arithmetic unit. Is written in the test bench file by the calculation unit. To.
[0008]
The test bench generation method according to the second invention uses a computer having a storage unit and an arithmetic unit to simulate the operation of a circuit designed in HDL or a system description language, and includes a program memory therein. A method for generating, from a program file in which one or more program instructions to be executed on a circuit are described in an assembly language, a test bench describing a procedure for verifying the operation of the circuit, comprising: After storing a program file in which a test instruction for checking a value of predetermined information processed in the circuit after a predetermined clock counted from execution is described in association with the program instruction, the program file is stored in a storage unit. An input signal file defining an input signal to be input to the circuit is stored in a storage unit, and the storage unit The one or more program instructions described in the stored program file are translated into a machine language to be executed in the circuit by an arithmetic unit, and each of the program instructions translated into the machine language is An arithmetic unit obtains an address of a program memory of the circuit to be stored, and associates the test instruction included in the program file with the address at which the program instruction associated with the test instruction is stored. The operation unit extracts from the program file, generates a test bench file in the operation unit and stores it in the storage unit.The generated test bench file includes the input signal defined in the input signal file. Expressed in HDL or system description language and written by the arithmetic unit, and the input signal is In the simulation started by being input to the circuit, a description instructing to add a clock for each predetermined process is expressed in HDL or a system description language, written in the arithmetic unit, and the address is called in the simulation. A description instructing that the obtained time is expressed in the unit of the added clock is written in the test bench file in HDL or a system description language and written in the arithmetic unit, and the value of the added clock is written in the test bench. A description indicating that the test instruction is to be executed when the value obtained by adding the predetermined clock to the time at which the address associated with the instruction is called is added to the test bench file in HDL or a system description language. And written in the calculation unit.
[0009]
In order to simulate the operation of a logic-designed circuit, the test bench generation device according to a third aspect of the present invention includes one or more program instructions to be executed on the circuit and directly defines the operation of the circuit. An apparatus for generating a test bench describing a procedure for verifying the operation of the circuit from the program file described in the above, wherein the test bench is processed in the circuit at a predetermined timing calculated from execution of a predetermined program instruction. Means for storing the program file in which a test instruction for checking the value of the information is described in association with the program instruction, and means for storing an input signal file defining input signals to be input to the circuit in the simulation And transmitting the test instruction included in the program file to the program associated with the test instruction. Means for extracting from the program file, means for generating a test bench file, and expressing the input signal specified in the input signal file in the generated test bench file in a state associated with the program command. Means for writing the contents, means for writing contents indicating the time at which the program instruction was called in the simulation in a file of the test bench, and wherein the program instruction associated with the test instruction is A means for writing, in the file of the test bench, a content for instructing execution of the test instruction when the predetermined timing counted from the time of the call is reached.
[0010]
According to a fourth aspect of the present invention, there is provided a test bench generation apparatus, which simulates an operation of a circuit designed in HDL or a system description language, in which one or more program instructions to be executed on the circuit including a program memory therein A test bench describing a procedure for verifying the operation of the circuit from a program file described in assembly language, wherein the test bench is processed in the circuit after a predetermined clock counted from execution of a predetermined program instruction. Means for storing the program file in which a test instruction for checking the value of the predetermined information is described in association with the program instruction, and an input signal file defining input signals to be input to the circuit in the simulation. Means for storing, and one of the programs described in the stored program file. Means for translating the plurality of program instructions into a machine language to be executed by the circuit, and means for acquiring an address of a program memory of the circuit in which each of the program instructions translated into the machine language is stored Means for extracting the test instruction included in the program file from the program file in association with the address where the program instruction associated with the test instruction is stored, and generating a test bench file Means, means for writing the input signal specified by the input signal file in HDL or a system description language into the generated test bench file, and writing the input signal into the test bench file Clock is added for each predetermined process in the simulation started by input to Means for writing a description instructing the address in HDL or a system description language, and a description instructing to represent the time at which the address was called in the simulation in a unit of a clock added. Means for writing in a file described in HDL or a system description language, and when the value of the added clock is a value obtained by adding the predetermined clock to the time at which the address associated with the test instruction is called Means for writing a description instructing execution of the test instruction to the test bench file in HDL or a system description language.
[0011]
A computer program according to a fifth aspect of the present invention provides a computer with one or a plurality of program instructions to be executed on the circuit to directly specify the operation of the circuit in order to simulate the operation of a logic-designed circuit. A computer program for generating, from a program file described in a format, a test bench describing a procedure for verifying the operation of the circuit, wherein the computer generates a test bench within the circuit at a predetermined timing calculated from execution of a predetermined program instruction. From the program file in which a test instruction for checking the value of the predetermined information being processed is described in association with the program instruction, the test instruction is stored in a state in which the test instruction is associated with the program instruction associated with the test instruction. The extraction procedure and the test bench file A step of causing the computer to write the contents of an input signal file that defines the input signals to be input to the circuit in the simulation into a generated test bench file. A procedure for writing the content indicating the time of calling in the simulation in the file of the test bench, and a computer instructing the computer to execute the program command associated with the test command in the simulation. Writing the contents instructing execution of the test instruction when the predetermined timing is counted into a file of the test bench.
[0012]
A computer program according to a sixth aspect of the present invention is a computer program, which simulates the operation of a circuit designed in HDL or a system description language, in a computer, one or more programs to be executed on the circuit including a program memory therein. A computer program for generating a test bench describing a procedure for verifying the operation of the circuit from a program file in which instructions are described in an assembly language. From the program file describing a test instruction for checking a value of predetermined information being processed in the circuit in association with the program instruction, one or a plurality of the programs in a machine language to be executed in the circuit Instructions to translate the instructions and the computer to the machine Obtaining an address of a program memory of the circuit in which each of the program instructions translated into the program instruction is stored; and causing a computer to execute the test instruction included in the program file, the program instruction being associated with the test instruction. A procedure for extracting the test bench file from the program file in association with the address in which the program is stored, a procedure for causing the computer to generate a test bench file, A step of expressing the contents of an input signal file defining input signals to be input to the HDL or a system description language and writing the input signals to a test bench file in a computer; Specified in the simulation A procedure for writing a description instructing to add a clock for each process in HDL or a system description language, and writing the time at which the address was called in the simulation in a unit of the added clock to the computer. And writing a description instructing the test instruction to the test bench file in HDL or a system description language, and instructing the computer to call the address where the added clock value is associated with the test instruction. And writing a description instructing to execute the test instruction when the value is the value obtained by adding the predetermined clock to the test time, in a file of the test bench in HDL or a system description language. It is characterized by the following.
[0013]
The inventor has determined that each program instruction written in assembly language corresponds to each operation performed by the circuit, and that the program instruction written in assembly language to be executed in the circuit is Focusing on the fact that the time at which the program instruction is executed in the circuit can be strictly defined, and by describing the test instruction necessary for the test bench in association with the program instruction described in the assembly language, the verification of the circuit can be performed. A test bench generation facilitating assembly language (ALET language: Assembly Language to Ease Testbench) that can easily specify the time to be performed has been developed.
[0014]
In the first, third, and fifth aspects of the present invention, a format for directly defining the operation of a circuit, that is, not a so-called high-level language for collectively defining a series of operations performed by a circuit, but an individual operation performed by the circuit is defined one by one. Using a program file in which test instructions in the ALET language are described in association with program instructions written in a so-called lower-level language, referring to a time at which the program instructions are called in the simulation, and executing the program at a predetermined timing calculated from the time. A test bench is generated that includes a description to execute a test instruction associated with the instruction. This eliminates the need to describe the test instruction execution time in absolute time when generating a test bench.The test instruction is executed relative to the program instruction written in a format that directly defines the circuit operation. The execution time can be specified.
[0015]
According to the second, fourth and sixth aspects of the present invention, a program file in which a test instruction in an ALET language is described in association with a program instruction in an assembly language is used, and an address of a memory in which the program instruction is stored in a simulation. A test bench including a description to execute a test instruction associated with the program instruction after a predetermined clock counted from the time with reference to the time at which is called. This eliminates the need to describe the test instruction execution time in absolute time when generating the test bench, and makes it relative to the program instruction written in assembly language corresponding to each operation of the circuit. The time at which the test instruction is executed can be specified by the number of clocks.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be specifically described with reference to the drawings showing the embodiments.
FIG. 1 is a conceptual diagram showing an outline of the present invention. According to the test bench generation method of the present invention, a program file 141 in which a program instruction to be executed in a circuit to be simulated is described in an assembly language and a signal to be input to the circuit for verifying the operation of the circuit are defined as information. The input signal file 142 is prepared. In the program file 141, a test instruction for verifying a value of predetermined information processed in a circuit for generating a test bench is described in an ALET language in association with an assembly language program instruction. The computer program 20 of the present invention for generating a test bench includes an assembler program and an ALET compiler program. The assembler generates, from the program file 141, a machine language file 143 obtained by translating a program instruction described in an assembly language into a machine language, and an intermediate file 144 extracted from a description part of the ALET language. The ALET compiler generates a test bench 145 from the generated machine language file 143, the generated intermediate file 144, and the input signal file 142. In the simulation method according to the present invention, a circuit description file that describes an operation and a logical configuration of a circuit using HDL or a system description language, a machine language file 143, and a generated test bench 145 are used. Is executed by a simulator for executing a program instruction described in a machine language file on the circuit described in (1) to verify a value described in a test bench, and outputs a simulation result. Note that a conventionally existing simulator can be used as the simulator.
[0017]
FIG. 2 is a block diagram showing a configuration of the test bench generation device of the present invention. The test bench generation device 1 is configured using a computer, and is a calculation unit according to the present invention, which performs a calculation, and a storage unit according to the present invention, which stores temporary information generated by the calculation. , An external storage device 13 such as a CD-ROM drive, and an internal storage device 14 such as a hard disk. The computer program 20 according to the present invention is externally stored from a recording medium 2 such as a CD-ROM. The computer program 20 is read by the device 13, the read computer program 20 is stored in the internal storage device 14, the computer program 20 is loaded into the RAM 12, and processing necessary for the test bench generation device 1 is executed based on the loaded computer program 20. The test bench generation device 1 further includes an input device 15 such as a keyboard or a mouse, and an output device 16 such as a liquid crystal display or a CRT display, and receives an operation from an operator such as data input. Has become.
[0018]
Further, the test bench generation device 1 includes a communication interface 17, downloads the computer program 20 according to the present invention from the server device 3 connected to the communication interface 17, and executes the processing by the CPU 11. Is also good.
[0019]
The internal storage device 14 is a program that is input from the input device 15 by an operation of the operator, read from an external storage medium in the external storage device 13, or downloaded from the external server device 3 via the communication interface 17. A file 141 and an input signal file 142 are stored. Further, the internal storage device 14 stores a machine language file 143 and an intermediate file 144 generated during the processing of the present invention, and stores a test bench 145 generated by the present invention.
[0020]
Next, the ALET language developed by the inventor will be described.
1. Description place of ALET language
The description of the ALET language is described in the comment part of the assembly language. Note that comments in assembly language are generally described below ";".
1.1 “; ￥” (semicolon and yen mark)
When the comment part of the assembly language starts with “; ￥”, it means that the description in the ALET language format starts.
1.2 ";"
If the comment part of the assembly language starts with ";" instead of ";@", it is a normal assembly language comment part.
1.3 "//" (two slash characters)
If “//” is described after the place of the description in the ALET language format, that is, “; ￥”, the description after “//” is a comment part of the ALET language.
[0021]
2. Required information
Before the delay and assert statements described below, the following three statements must be made.
2.1 "@pc": Designation of processor program counter
In the circuit to be simulated, the location where the program counter of the processor exists is specified.
2.2 “＠”: Processing sensitivity list
The sensitivity list is a description in HDL or a system description language that specifies which event of which signal the process execution depends on, and specifies a reference clock of a process for performing circuit verification. Basically, it specifies the clock input to the circuit.
2.3 "｀ ＠": Processing execution condition
Specify the conditions under which the circuit verification process is executed. Specifies the first machine cycle of the processor. Before specifying the processing execution condition, it is necessary to specify the program counter of the processor with "@pc".
[0022]
3. "#": Specify delay time
Specifies the time at which the test instruction will be performed. By describing the number of clocks following “#” and “# 5c;”, the number of clocks is counted from the time when the immediately preceding assembly language program instruction is executed for the first time, and after 5 clocks or the like. , Which means to proceed to the description in the ALET language format.
[0023]
4. Display function
4.1 “asrt ()”: assert statement
By describing “asrt (condition);”, when the immediately preceding assembly language program instruction is executed at the time of this description, it is determined whether the condition is positive or false, and If false, it means to stop the simulation and output that the condition is false. By describing the predicted value in the conditional expression, a test for comparing the value of the information processed by the circuit with the predicted value can be performed.
4.2 “disp ()”: Display sentence
By describing "disp (character string);", it means that the character specified by the character string is displayed when the immediately preceding assembly language program instruction is executed at the time of this description.
4.3 “dump ()”: Dump statement
By describing “dump (signal name);”, it means that the state of the signal specified by the signal name is displayed when the immediately preceding assembly language program instruction is executed at the time of this description. .
[0024]
5. Definition statements and reserved words
5.1 "@def": Definition sentence
By describing "$ def definition name value, expression or character string", in the description of the ALET language after this definition, the definition name is replaced with the value, expression or character string specified thereafter. means.
5.2 Reserved words
In the following description, since the assembly language and the ALET language are closely related, the ALET language compiler substitutes appropriate values.
INST ... Instruction information stored in ROM.
OPR1 ... Information of operand 1 stored in ROM.
OPR2 ... Information of operand 2 stored in ROM.
ADR: ROM address. Indicates the address where INST is located in the machine language file 3.
Note that the ROM described here is a memory that stores a program instruction included in a circuit to be simulated.
[0025]
6. Description method
6.1 Multiple descriptions on the same line
The description of the ALET language starting with "@" (at mark) and "@" (accent grab) cannot be described at the same time on one line, but multiple descriptions of delay and assert statements are allowed. Those in which plural descriptions are allowed are separated from each other by ";".
6.2 Time overlap
In the ALET language, time overlap of a plurality of test instructions is also possible.
[0026]
Next, an example of a circuit designed in HDL or a system description language will be described. FIG. 3 is a block diagram illustrating an example of a circuit described in a circuit description file and to be simulated. The processor 41, which is a circuit described in the circuit description file, is named nr8d, and includes a CPU 42 named ncpu, a RAM 43, and a ROM 44. The processor 41 is given an instance name of U0, and the ncpu 42 is given an instance name of U1. The instance name is a label name assigned to make a plurality of identical components (modules) available in HDL or a system description language. The reset signal rst51 and the clock signal clk52 are input to the ncpu42. When the reset signal 51 is input, the ncpu 42 is reset. A data bus 53 connected to each other is provided between the ncpu 42 and the RAM 43 and the ROM 44, and exchanges data with each other via the data bus 53. Further, an address bus 54 is provided in parallel with the data bus 53, and the ncpu 42 designates, via the address bus 54, an address indicating which part of the RAM 43 and the ROM 44 to read data.
[0027]
The ncpu 42 includes an instruction register irh # reg 45, a controller 46, a program counter proccnt 47, an arithmetic and logic unit ALU 48, and a general-purpose register 49. The controller 46 internally includes a cycle state register cstate 461, and the general-purpose register 49 internally includes a W register W # reg 491, a BL register BL # reg 492, and a BH register BH # reg 493. The instruction register irh # reg 45 fetches an instruction from the data bus 53 and stores it. The controller 46 interprets the instruction stored in the instruction register irh # reg 45 and controls the entire ncpu 42. The program counter progcnt 47 is instructed by the controller 46 how much to advance the counter, and outputs the result to the address bus 54. The arithmetic and logic unit ALU 48 fetches data from the data bus 53 and the general-purpose register 49, calculates the fetched data, and outputs the calculated result to the data bus 53 or the general-purpose register 49.
[0028]
When a register in the ncpu 42 is specified, it is necessary to specify a hierarchical structure. Therefore, in the simulation environment, the W register W # reg 491 stores U0. U1. W # reg and BL register BL # reg 492 store U0. U1. BL # reg, BH register BH # reg 493 stores U0. U1. BH # reg, the program counter progcnt47 is U0. U1. progcnt, cycle state register cstate 461 is U0. U1. cstate, the instruction register irh # reg45 is U0. U1. irh # reg and the reset signal rst51 are U0. U1. rst, clock signal clk52 is U0. U1. It is expressed as clk.
[0029]
Next, a description example of the ALET language is shown. FIG. 4 is a diagram illustrating an example of the program file 141 described in the assembly language and the ALET language. The left half in the figure is the part of the assembly language, and the part described below the right half ";￥" is the part of the ALET language. Lines 401 to 406 are ALET language definition statements, and line 401 is U0. U1. It is defined that proccnt is omitted and written as cpupc. U1. cstate is cpucst, and line 403 is U0. U1. clk is cpulk, line 404 is U0.clk. U1. irh # reg is cpuirh, and line 405 is U0. U1. BL # reg is cpubl, line 406 is U0. U1. It is defined that W # reg is abbreviated as cpuw and written. Line 407 is a comment sentence in assembly language.
[0030]
Lines 408 to 410 are mandatory description items of the ALET language. The line 408 indicates that the program counter of the processor 41 to be simulated is cpupc, that is, U0. U1. progcnt47. Line 409 specifies that the asrt sentence after line 412 is executed at the timing of negative (cpulk). negative (cpulk) is cpulk, that is, U0. U1. This means that clk operates when a falling edge is detected. The line 410 indicates that cpucst == 14′h0001 holds, that is, U0. U1. Only when cstate becomes equal to a 14-bit numerical value of 0001 in hexadecimal is meant to execute the asrt statement in the line 412 and thereafter. Line 411 is a description in assembly language, and sets a label of MAIN. Labels are used when jumping in assembly language.
[0031]
"MOV 10h, W" in the part before ";$" in the line 412 is an assembly language program instruction, which means that a constant of 10 in hexadecimal, that is, 16 in decimal is transferred to the W register W # reg 491. ing. The part of “asrt (cpupc == ADR);” after “; ￥” in the line 412 is an asrt statement in the ALET language. When the MOV instruction in the assembly language on the same line is executed, cpupc, that is, U0. U1. This means a test instruction for performing a test (assert) as to whether the proccnt 47 is the same as the address ADR of the ROM 44, and displaying an error if incorrect. A line 413 indicates a test instruction in which “asrt (cpucst == 14′h0002);” is performed one clock after the execution of the ALET language test instruction in the line 412. That is, U0. U1. Test whether cstate 461 is equal to a 14-bit number that is 0002 in hexadecimal. Further, the row 414 has a value of cpuirh, that is, U0. U1. Whether or not irh # reg 45 is equal to the instruction INST (here, indicating the MOV instruction in row 412, and transferring from a constant (10h = 10 in hexadecimal) to the W register 491, INST is 32 in hexadecimal) Means a test instruction to test. Further, the line 415 stores the cpucst, that is, U0. U1. This means a test instruction for testing whether or not cstate 461 is equal to a 14-bit numerical value of 0004 in hexadecimal. Row 416 contains cpucst, ie, U0... 1 clock after the execution of the test instruction in row 415. U1. This means a test instruction for testing whether or not cstate 461 is equal to a 14-bit numerical value of 0008 in hexadecimal. Row 417 contains cpucst or U0 .1 clock one clock after execution of the test instruction in row 416. U1. This means a test instruction for testing whether or not cstate 461 is equal to a 14-bit numerical value of 0001 in hexadecimal. Further, row 418 contains cpuw, ie, U0. U1. A test instruction for testing whether W # reg 491 is equal to the first operand OPR1 (here, the first operand of the MOV instruction in row 412, which is a constant 10h, that is, 10 in hexadecimal) is meant.
[0032]
“MOV W, BL” in line 419 before “; ￥” is a program instruction in assembly language, which means that the data of the W register 491 is transferred to the BL register 492 in hexadecimal. The part of “asrt (cpupc == ADR);” after “; ￥” in the line 419 is an asrt statement in the ALET language. When the MOV instruction in the assembly language on the same line is executed, cpupc, that is, U0. U1. This means a test instruction for testing whether or not the proccnt 47 is the same as the address ADR of the ROM 44. Row 420 contains cpubl or U0. 3 clocks after the execution of the test instruction in row 419. U1. BL # reg 492 is cpuw, that is, U0. U1. This means a test instruction for testing whether or not the value is equal to W # reg491.
[0033]
Lines 421 to 425 describe an assembly language program instruction.
Line 421 indicates a program instruction for transferring a hexadecimal constant of 02 to the W register 491. The line 422 indicates a program instruction for transferring the value of the W register 491 to the BH register 493. Line 423 represents a program instruction for transferring a constant of 0AA in hexadecimal (that is, 170 in decimal) to the W register 491. The line 424 indicates a program command for transferring the value of the W register 491 to the memory designated by the B register, that is, the BL register 492 and the BH register 493, that is, the ROM 43 and the RAM 44. Line 425 means do nothing.
[0034]
Next, a description example of the input signal is shown. FIG. 5 is a diagram showing an example of the contents of the input signal file 142. The input signal file 142 is described in Verilog-HDL language. It may be described in another HDL or system description language. The description 501 in the figure specifies how a circuit to be simulated is related to the test bench 145, and relates the processor 41 of nr8d to the test bench 145 of nr8d # test.
[0035]
The description 502 sets an input signal to be input to the processor nr8d41, which is a circuit to be simulated. Only the operation of the clock t # clk and the reset t # rst and the initial values of other input signals are described, whereby the location of the circuit portion to be verified or the input each time the time changes. There is no need to rewrite signal information.
[0036]
The description 503 indicates that signal or register information is to be written to a file in order to output a signal waveform. If it is not necessary to output a signal waveform, this description is unnecessary. Description 504 specifies the end time. Here, it is specified that the simulation is ended after 1,000,000 ns.
[0037]
Next, the procedure of the test bench generation method of the present invention will be described based on a flowchart. FIG. 6 is a flowchart illustrating a procedure of processing performed by the test bench generation device of the present invention. The CPU 11 of the test bench generation device 1 loads the computer program 20 into the RAM 12, and performs assembler processing according to the loaded computer program 20 (S1). FIG. 7 is a flowchart showing the procedure of the assembler process in step S1. The CPU 11 reads the program file 141 stored in the internal storage device 14 according to the computer program 20 loaded in the RAM 12 and stores the read program file 141 in the RAM 12 (S11). Translated into words, and a machine language file 143 is generated (S12). Next, the CPU 11 extracts, from the machine language file 143, an address of a memory stored when each of the program instructions translated into the machine language is executed according to the computer program 20 loaded into the RAM 12 (S13). The program file 141 is extracted from the program file 143 by associating the parts described in the ALET language with the addresses extracted for the program instructions associated with the respective parts (S14), and the extracted ALET language parts are written. An intermediate file 144 is generated (S15), and the process returns to main.
[0038]
FIG. 8 is a diagram showing an example of the contents of the generated intermediate file 144, which is the contents of the intermediate file 144 generated from the program file 143 shown in FIG.
Each description of the ALET language described in the program file 143 is extracted, and the number in the second column shown in the drawing is a number indicating from which line of the program file 143 the ALET language description of each line was extracted. It is. The number in the first column is an address associated with each row, and is a memory address stored when an assembly language program instruction associated with the ALET language description of each row is executed.
[0039]
Next, the CPU 11 stores the machine language file 143 and the intermediate file 144 generated by the assembler processing in the internal storage device 14 according to the computer program 20 loaded into the RAM 12 (S2), and generates the test bench 145 from the intermediate file 144. The processing of the ALET compiler is performed (S3), the generated test bench 145 is stored in the internal storage device 14 (S4), and the processing is terminated.
[0040]
9 to 12 are flowcharts showing the procedure of the processing of the ALET compiler in step S3. The CPU 11 reads the machine language file 143, the intermediate file 144, and the input signal file 142 from the internal storage device 14 into the RAM 12 according to the computer program 20 loaded into the RAM 12 (S301), and writes the necessary information into the file on the test bench 145. Is generated (S302), and the contents of the input signal file 142 are written to the generated test bench 145 (S303). FIG. 13 is a diagram illustrating an example of the content of the test bench 145 to be generated. The test bench 145 is described in Verilog-HDL language. Note that it may be described in another HDL or system description language. The content of the input signal file 142 is written in the description 1301 in the figure, and the information of the input signal is defined in the test bench. The description 1302 defines a file pointer of a file to which a result of the simulation is written. The description 1303 defines a register that counts the number of clocks serving as times in the simulation. Description 1304 defines an array that stores the times at which the program instructions stored in memory were called in the simulation. The description 1305 instructs the file pointer to specifically open the file.
[0041]
Next, the CPU 11 acquires one line of data from the intermediate file 144 stored in the RAM 12 according to the computer program 20 loaded in the RAM 12, stores the data in a predetermined character array (S304), and determines whether the data has been acquired. (S305), and if the data cannot be obtained (S305: NO), it is determined that the processing has been completed up to the last line of the intermediate file 144, the end portion of the file is written to the test bench 145 (S306), and ALET is executed. Terminates the processing of the compiler and returns the processing to the main.
[0042]
If the data has been obtained in step S305 (S305: YES), the CPU 11 obtains information such as an address associated with the description of the obtained line in the ALET language according to the computer program 20 loaded in the RAM 12 (step S305). S307). Next, the CPU 11 determines, according to the computer program 20 loaded into the RAM 12, whether or not the head description of the acquired line in the ALET language is a description of “$ def” (S308), and describes the description of “$ def”. (S308: YES), the information of the definition of the character string is stored in the structure array def [] (S309), the process returns to step S304, and the description of the next line of the intermediate file 144 is obtained. I do. If the description is not “$ def” (S308: NO), the CPU 11 next sets the first description of the acquired line in the ALET language to “$ pc” according to the computer program 20 loaded into the RAM 12. It is determined whether there is any data (S310). If the description is "$ pc" (S310: YES), the information on the definition of the program counter is stored in a predetermined character string pcstr (S311), and the process is performed. Returning to S304, the description of the next one line of the intermediate file 144 is acquired.
[0043]
If the description is not “$ pc” in step S310 (S310: NO), the CPU 11 next sets the description at the top of the ALET language of the acquired line to “$” according to the computer program 20 loaded into the RAM 12. Is determined (S312). If the description is “$” (S312: YES), the CPU 11 next determines whether the description “$” is the first description according to the computer program 20 loaded into the RAM 12. (S313) If the description of “$” is not the first description but a plurality of descriptions (S313: NO), an error indicating that the sensitivity list is defined redundantly is output (S314). ), Forcibly terminate the process If the description of “$” is the first description (S313: YES), the CPU 11 then stores the definition in the structure array def [] according to the computer program 20 loaded in the RAM 12. It is determined whether or not the character string is included in the acquired line (S315). If the character string in which the definition is stored is not included (S315: NO), the process proceeds to step S317. If a character string whose definition is stored is included (S315: YES), the character string is replaced according to the definition (S316), a sensitivity list is written to the test bench 145 (S317), and the sensitivity list is written. Is written into the test bench 145 (S318), and the process returns to step S304 to write the description of the intermediate file 144. Get the description of the line. A description 1306 in FIG. 13 is for writing a sensitivity list, and defines a reference clock so that the fall of the clock signal is used as a time reference in the simulation. The description 1307 indicates that a register for counting the number of clocks serving as times in the simulation is incremented.
[0044]
If the description is not “$” in step S312 (S312: NO), the CPU 11 next sets the description at the top of the ALET language of the acquired line to “$” according to the computer program 20 loaded into the RAM 12. Is determined (S319). If the description is “$” (S319: YES), the CPU 11 next determines whether the description “$” is the first description in accordance with the computer program 20 loaded into the RAM 12. It is determined (S320), and when the description of "@" is not the first but a plurality of descriptions are made (S320: NO), an error indicating that the processing execution condition is defined redundantly is output. (S321), and the process is forcibly terminated. When the description of “$” is the first description (S320: YES), the CPU 11 next stores the information of the definition of “$ pc” according to the computer program 20 loaded in the RAM 12 in advance. It is determined whether or not it is stored in the character string pcstr (S322). If the information of the definition of “@pc” is not stored (S322: NO), an error indicating that the program counter is not set Is output (S323), and the process is forcibly terminated. If the information of the definition of “@pc” has been stored (S322: YES), the CPU 11 next executes the character whose definition is stored in the structure array def [] according to the computer program 20 loaded into the RAM 12. It is determined whether or not the column is included in the acquired row (S324). If the column does not include a character string whose definition is stored (S324: NO), the process proceeds to step S326. If a character string whose definition is stored is included (S324: YES), the character string is replaced according to the definition (S325), and a processing execution condition is written to the test bench 145 (S326). When the condition is satisfied, the time at which the program instruction indicated by the program counter is called is associated with the value of the program counter at that time. Kino write a description to be stored clock values to the test bench 145 (S327), the process returns to step S304, and acquires the description of the next line of the intermediate file 144. A description 1308 in FIG. 13 sets processing execution conditions. A description 1309 indicates that the address indicated by the program counter at that time is stored in an array for storing the time at which the program instruction stored in the memory is called in the simulation. It indicates that the clock value at that time is substituted as the called time.
[0045]
If the description is not “$” in step S319 (S319: NO), the CPU 11 next writes the description from the acquired line to “;” in accordance with the computer program 20 loaded into the RAM 12. It is acquired (S328), and it is determined whether or not the leading description of the acquired part is the description of "#" (S329). If the description is “#” (S329: YES), the CPU 11 then determines whether “$ pc”, “$”, and “$” have already been set according to the computer program 20 loaded into the RAM 12. It is determined (S330) whether it is not set, and if it is not set (S330: NO), an error indicating that any of "$ pc", "$", and "$" is not set is output ( S331), the process is forcibly terminated. If “$ pc”, “$”, and “$” have already been set in step S330 (S330: YES), the delay of the delay is associated with the address associated with the acquired row. The number of delayed clocks is added by the number of clocks indicated by the description and stored (S332), and the process proceeds to step S352.
[0046]
In step S329, if the description at the top of the acquired part is not the description of “#” (S329: NO), the CPU 11 then writes the description of the acquired part in accordance with the computer program 20 loaded into the RAM 12. It is determined whether or not the description is an asrt statement (S333). If the description is an asrt statement (S333: YES), it is determined whether “$ pc”, “$”, and “$” have already been set. It is determined (S334) whether it is not set or not (S334: NO), the process proceeds to step S331, an error is output, and the process is forcibly terminated. If “$ pc”, “$”, and “$” have already been set in step S334 (S334: YES), the CPU 11 next executes the asrt statement according to the computer program 20 loaded into the RAM 12. The conditional expression as an argument is obtained (S335), and it is determined whether or not the character string whose definition is stored in the structure array def [] is included in the obtained part (S336). If the stored character string is not included (S336: NO), the process proceeds to step S338, and if the stored character string is included (S336: YES), the character string is used. Is replaced according to the definition (S337), and the clock is obtained by adding the stored delay clock to the value of the clock associated with the address associated with the acquired row. At the time of the check, the description of the time specification to be verified is written to the test bench 145 (S338), and the description to compare the predetermined value with the predicted value according to the conditional expression is written to the test bench 145 (S339). , The process proceeds to step S352. The description 1310 in FIG. 13 indicates that the verification process is performed when a predetermined clock is added from the time when the predetermined address is called, and the program instruction associated with the row 412 shown in FIG. An instruction to perform verification when a time obtained by adding a delay clock 0 to a time when an address 0032 which is a memory address stored in the simulation is called is shown. The description 1311 indicates that a predetermined value is compared with a predicted value according to a conditional expression, and an error should be output if the predetermined value is different from the predicted value. The portion of the description 1312 corresponding to each of the plurality of test instructions shown in FIG. 4 includes, like the portion of the description 1311, an instruction to compare a predetermined value with a predicted value at a predetermined time. Is described. In FIG. 13, a specific description of the description 1312 is omitted.
[0047]
In step S333, if the description of the acquired part is not the description of the asrt statement (S333: NO), the CPU 11 then changes the description of the acquired part to the description of the dump statement in accordance with the computer program 20 loaded into the RAM 12. It is determined whether or not the description is a description (S340). If the description is a description of a dump statement (S340: YES), a signal name which is an argument of the dump statement is obtained (S341), and is stored in the structure array def []. It is determined whether or not the character string whose definition is stored is included in the acquired part (S342). If the character string whose definition is stored is not included (S342: NO), The process proceeds to step S344, and if a character string whose definition is stored is included (S342: YES), the character string is replaced according to the definition (S343). Is a clock obtained by adding the stored delay clock to the value of the clock associated with the address associated with the acquired row, and a description of the time specification to be processed is sent to the test bench 145. Write (S344), a description to output information of the signal of the acquired signal name is written in the test bench 145 (S345), and the process proceeds to step S352.
[0048]
If it is determined in step S340 that the description of the obtained part is not a description of a dump statement (S340: NO), the CPU 11 then changes the description of the obtained part to a description of the disp statement in accordance with the computer program 20 loaded into the RAM 12. It is determined whether the description is a description (S346). If the description is not a disp statement (S346: NO), the process proceeds to step S352. If it is a description of a disp statement (S346: YES), the CPU 11 next acquires a character string as an argument of the disp statement according to the computer program 20 loaded into the RAM 12 (S347), and obtains a structure array def [ It is determined whether or not the character string whose definition is stored is included in the acquired part (S348). If the character string whose definition is stored is not included (S348: NO) ), The process proceeds to step S350. If a character string whose definition is stored is included (S348: YES), the character string is replaced in accordance with the definition (S349), and the time is set to the acquired line. In the case of a clock obtained by adding the stored delay clock to the value of the clock associated with the address associated with Write to bench 145 (S350), writes a description to be output the acquired character string to the test bench 145 (S351), determines whether there is obtained and that the line to the remaining description (S352). If there is a remaining description in the acquired line (S352: YES), the process returns to step S328 to acquire the description from the acquired line to the next ";" If there is no remaining description (S352: NO), the process returns to step S304 to acquire the description of the next one line of the intermediate file 144.
[0049]
As described in detail above, in the present invention, a program file in which a test instruction in the ALET language is described in association with a program instruction in an assembly language is used, and a time at which the program instruction is called in the simulation is referred to. After a predetermined clock counted from the time, a test bench 145 including a description to execute a test instruction associated with the program instruction is generated. This eliminates the need to describe the test instruction execution time in absolute time when generating the test bench, and makes it relative to the program instruction written in assembly language corresponding to each operation of the circuit. The time at which the test instruction is executed can be described by time.
[0050]
The test bench 145 generated according to the present invention is read by a computer loaded with a simulator program, and the computer further reads a machine language file 143 and a circuit description file, and is written in the circuit description file according to the simulator program. A simulation for executing the program instruction described in the machine language file 143 on the circuit and executing the test instruction described in the test bench 145 is performed.
[0051]
FIG. 14 is a flowchart showing the contents of the processing described in the test bench 145 shown in FIG. The computer that performs the simulation increments the clock, which is a unit of time in the simulation, according to the test bench 145 (S51), determines whether or not the processing execution condition is satisfied (S52). If the processing execution condition is not satisfied, (S52: NO), the process proceeds to step S61. If the process execution condition is satisfied (S52: YES), the program counter of the circuit described in the circuit description file is monitored (S53), and the address indicated by the program counter is set. The current clock value is stored as the associated time, that is, the time when the program instruction at the address is called (S54). The computer then refers to the time associated with the corresponding address, i.e., the time at which the program instruction associated with the test instruction was invoked, and the current clock value adds a predetermined number of clocks to the time. It is determined whether or not the value is the same (S61). If the value is the same (S61: YES), the test instruction is executed (S62). If the clock value is different (S61: NO). , The process proceeds to the next step of step S62. Next, the computer performs the same processing as in step S61 and step S62 for each of the described test instructions, and then determines whether or not the condition for terminating the simulation is satisfied (S70). If the termination condition is not satisfied (S70: NO), the process returns to step S51, and the clock is incremented. If the termination condition is satisfied (S70: YES), the process ends. .
[0052]
FIG. 15 is a schematic diagram showing a waveform of a process of performing a simulation on the processor 41 using the test bench 145. Assume that the MOV instruction of the assembly language program instruction described in row 412 of FIG. The ADR of the MOV instruction at this time is 32 in decimal. In this case, as indicated by reference numeral 1512 in the figure, when the program counter indicates 32 in decimal, the asrt statement in the ALET language in line 412 in FIG. 4 is executed. The asrt statement is cpupc, that is, U0. U1. A test is performed to determine whether progcnt47 is equal to ADR, in which case cpupc, ie, U0. U1. The test passes because both progcnt 47 and ADR point to 32 in decimal.
[0053]
Next, the portion 1513 shown in the figure is tested according to the description of the row 413 in FIG. Further, according to the description of the row 414 in FIG. 4, the portion 1514 shown in the figure is tested. At this time, the MOV instruction is an instruction for transferring a constant to the W register, and the machine language is 32 in hexadecimal. Therefore, INST is replaced by hexadecimal number 32, and the test passes in this case as well. Similarly, the description of the row 1515 shown in FIG. 4 is used to test the portion 1515 shown in the figure, and the description of the row 416 shown in FIG. According to the description in the row 417, the portion 1517 shown in the figure is tested. In each case the test passes. According to the description in the row 418 of FIG. 4, the portion 1518 shown in the figure is tested, and the test also passes because OPR1 has the same meaning as the first operand 10h (10 hexadecimal).
[0054]
Next, the MOV instruction of the assembly language program instruction is stored at the address 34 in decimal in the memory according to the description of the line 419 in FIG. At this time, the ADR is 34 in decimal. Here, since the time series of the ALET language starts from each instruction of the assembly language, when the program counter of the processor 41 points to 34 in decimal and satisfies the condition designated by “@”, At the time of 1501 shown in FIG. 15, the test instruction of the ALET language is executed, and the portion 1519 shown in FIG. 15 is tested. In line 419 of FIG. 4, this test passes because both are 34 in decimal because the program counter of processor 41 specifies to test for ADR pointing to the address of the ROM. . Similarly, according to the description of the row 420 in FIG. 4, the portion 1520 shown in FIG. 15 is tested, and in this case, the test also passes.
[0055]
As described above, even when the time at which the test instruction is executed is before or after, the time at which the test instruction is executed can be specified by describing the test instruction in the ALET language in association with the program instruction of interest. Specification becomes easy. In addition, since a test instruction can be described independently in association with the operation of a specific part in a circuit, the present invention can be applied to a processor that performs pipeline processing.
[0056]
FIG. 16 is a characteristic diagram showing a description amount necessary for creating a test bench. The horizontal axis indicates the number of test items by the test bench, and the vertical axis indicates the size of the file that needs to be manually input for creating the test bench in units of bytes. Compared to the conventional method that required inputting a huge amount of files as the number of test items increased, the present invention greatly reduced the size of the file required to be input, and the input required as the number of test items increased. The rate of increase in file size is also very small. Therefore, by using the present invention, the labor and time required to create a test bench can be significantly reduced.
[0057]
In the present embodiment, an example is described in which an intermediate file is created by assembler processing and a test bench is generated by ALET compiler processing based on the created intermediate file. However, the present invention is not limited to this form. Alternatively, a mode may be used in which a test bench is generated at once without generating an intermediate file. In addition, the mode of using the method of continuously executing the assembler processing and the ALET compiler processing has been described. However, the processing is terminated once when the assembler processing is completed, and again after receiving an instruction from an operator or the like. An embodiment using a method of performing the processing of the ALET compiler may be used. Further, in the present embodiment, the program instructions described in the program file are described in the assembly language, and the form in which the test bench is generated from the program file has been described. When program instructions are described in a programming language, that is, a so-called low-level language that defines individual operations performed by a circuit, instead of a so-called high-level language that collectively defines a series of operations performed by a circuit, the circuit operates in a separate operation. Since the execution time can be clearly defined, a test bench may be generated from a program file in which program instructions are described in another program language other than the assembly language.
[0058]
【The invention's effect】
In the first, third and fifth aspects of the present invention, the operation of the circuit is directly defined, that is, the individual operation performed by the circuit is not defined collectively but a series of operations performed by the circuit. Using a program file in which a test instruction in the ALET language is described in association with the described program instruction, the program instruction is referred to at the time when the program instruction is called in the simulation, and is associated with the program instruction at a predetermined timing calculated from the time. A test bench including a description for executing the test instruction is generated. This eliminates the need to describe the test instruction execution time in absolute time when generating a test bench.The test instruction is executed relative to the program instruction written in a format that directly defines the circuit operation. The execution time can be easily specified. In addition, the size of a file that needs to be manually input to generate a test bench is significantly reduced, and the labor and time required to create a test bench can be significantly reduced.
[0059]
According to the second, fourth and sixth aspects of the present invention, a program file in which a test instruction in an ALET language is described in association with a program instruction in an assembly language is used, and an address of a memory in which the program instruction is stored in a simulation. A test bench including a description to execute a test instruction associated with the program instruction after a predetermined clock counted from the time with reference to the time at which is called. This eliminates the need to describe the test instruction execution time in absolute time when generating the test bench, and makes it relative to the program instruction written in assembly language corresponding to each operation of the circuit. The time at which the test instruction is executed can be specified by the number of clocks. In addition, the present invention significantly reduces the size of files that need to be manually input to generate a test bench, and significantly reduces the labor and time required to create a test bench. It has excellent effects.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram showing an outline of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a test bench generation device according to the present invention.
FIG. 3 is a block diagram illustrating an example of a circuit described in a circuit description file to be simulated;
FIG. 4 is a diagram showing an example of a program file described in an assembly language and an ALET language.
FIG. 5 is a diagram showing an example of the contents of an input signal file.
FIG. 6 is a flowchart showing a procedure of a process performed by the test bench generation device of the present invention.
FIG. 7 is a flowchart showing a procedure of assembler processing in step S1.
FIG. 8 is a diagram illustrating an example of the contents of a generated intermediate file.
FIG. 9 is a flowchart showing a procedure of processing of the ALET compiler in step S3.
FIG. 10 is a flowchart showing a procedure of processing of the ALET compiler in step S3.
FIG. 11 is a flowchart showing a procedure of processing of the ALET compiler in step S3.
FIG. 12 is a flowchart illustrating a procedure of processing of the ALET compiler in step S3.
FIG. 13 is a diagram illustrating an example of the contents of a test bench to be generated.
FIG. 14 is a flowchart showing the contents of processing described in the test bench shown in FIG.
FIG. 15 is a schematic diagram showing waveforms of processing in which a simulation is performed on a processor using a test bench.
FIG. 16 is a characteristic diagram showing a description amount necessary for creating a test bench.
FIG. 17 is a conceptual diagram showing an outline of a conventional simulation.
[Explanation of symbols]
1 Test bench generator
11 CPU (arithmetic unit)
12 RAM (storage unit)
2 Recording media
20 Computer programs

Claims (6)

In order to simulate the operation of a logic-designed circuit, one or more program instructions to be executed on the circuit are directly defined by using a computer having a storage unit and an operation unit. A method for generating a test bench describing a procedure for verifying the operation of the circuit from a program file described in a format
A test instruction for checking a value of predetermined information processed in the circuit at a predetermined timing calculated from execution of a predetermined program instruction is stored in a storage unit in a storage unit, wherein the test file describes a test instruction in association with the program instruction. ,
An input signal file defining an input signal to be input to the circuit in the simulation is stored in a storage unit,
The test instruction included in the program file is extracted by the operation unit from the program file in a state where the test instruction is associated with the program instruction associated with the test instruction,
The test bench file is generated by the arithmetic unit and stored in the storage unit,
In the generated test bench file, the content expressing the input signal specified in the input signal file is written by an arithmetic unit,
A content indicating that the program instruction indicates a time called in the simulation is written in a file of the test bench by an arithmetic unit,
When the predetermined timing calculated from the time at which the program instruction associated with the test instruction is called in the simulation comes, the content indicating the execution of the test instruction is calculated in the test bench file. A test bench generation method characterized by writing in a section. In order to simulate the operation of a circuit designed in a hardware description language or a system description language, a computer having a storage unit and an operation unit is used to execute a circuit to be executed on the circuit including a program memory therein. Or a method of generating a test bench describing a procedure for verifying operation of the circuit from a program file in which a plurality of program instructions are described in an assembly language,
After a predetermined clock counted from the execution of the predetermined program instruction, storing the program file in which a test instruction for checking a value of predetermined information processed in the circuit in association with the program instruction is stored in a storage unit. ,
An input signal file defining an input signal to be input to the circuit in the simulation is stored in a storage unit,
The one or more program instructions described in the program file stored in the storage unit are translated into a machine language to be executed by the circuit by an arithmetic unit, and the program instructions translated into a machine language The address of the program memory of the circuit in which each of
The test instruction included in the program file is extracted by the arithmetic unit from the program file in association with the address at which the program instruction associated with the test instruction is stored,
The test bench file is generated by the arithmetic unit and stored in the storage unit,
In the generated test bench file, the input signal specified in the input signal file is expressed in a hardware description language or a system description language and written by an arithmetic unit,
In the test bench file, a description instructing to add a clock for each predetermined process in the simulation started when the input signal is input to the circuit is expressed in a hardware description language or a system description language. Write in the arithmetic unit,
The description indicating that the address is called in the simulation in the unit of the added clock in the simulation is expressed in the test bench file in the hardware description language or the system description language, and the calculation unit writing,
When the value of the added clock is a value obtained by adding the predetermined clock to the time at which the address associated with the test instruction is called, a description indicating that the test instruction is to be executed is described in the test bench. A test bench generation method characterized in that the file is written in a hardware description language or a system description language and written by a calculation unit in the file. In order to simulate the operation of a logic-designed circuit, one or more program instructions to be executed on the circuit are described from a program file in which the operation of the circuit is directly specified. An apparatus for generating a test bench describing a procedure for verifying the operation of
Means for storing the program file in which a test instruction for checking a value of predetermined information processed in the circuit at a predetermined timing calculated from execution of a predetermined program instruction is described in association with the program instruction;
Means for storing an input signal file defining input signals to be input to the circuit in the simulation;
Means for extracting the test instruction included in the program file from the program file in a state where the test instruction is associated with the program instruction associated with the test instruction;
Means for generating test bench files;
Means for writing the content representing the input signal defined in the input signal file to the generated test bench file,
Means for writing, in a file of the test bench, a content indicating that the program instruction indicates a time called in the simulation,
When the program instruction associated with the test instruction is at the predetermined timing calculated from the time when the program instruction is called in the simulation, the content indicating that the test instruction is to be executed is written to the test bench file. And a means for generating a test bench. In order to simulate the operation of a circuit designed in a hardware description language or a system description language, one or a plurality of program instructions to be executed on the circuit including a program memory therein are described in an assembly language. An apparatus for generating a test bench describing a procedure for verifying operation of the circuit from a program file,
Means for storing the program file in which a test instruction for checking a value of predetermined information processed in the circuit after a predetermined clock counted from execution of the predetermined program instruction is described in association with the program instruction;
Means for storing an input signal file defining input signals to be input to the circuit in the simulation;
Means for translating one or more of the program instructions described in the stored program file into a machine language to be executed by the circuit;
Means for obtaining an address of a program memory of the circuit in which each of the program instructions translated into machine language is stored;
Means for extracting the test instruction included in the program file from the program file in association with the address where the program instruction associated with the test instruction is stored;
Means for generating test bench files;
Means for writing the input signal specified by the input signal file in a hardware test language or a system description language in a generated test bench file,
In the test bench file, a description instructing to add a clock for each predetermined process in the simulation started when the input signal is input to the circuit is expressed in a hardware description language or a system description language. Means for writing
Means for writing a description instructing to represent the time at which the address was called in the simulation in a unit of a clock added to the test bench file in a hardware description language or a system description language,
When the value of the added clock is a value obtained by adding the predetermined clock to the time at which the address associated with the test instruction is called, a description indicating that the test instruction is to be executed is described in the test bench. A means for expressing and writing the file in a hardware description language or a system description language to the file. In order to simulate the operation of a logic-designed circuit, a computer writes one or more program instructions to be executed on the circuit from a program file describing the operation of the circuit in a format that directly defines the operation of the circuit. A computer program for generating a test bench describing a procedure for verifying the operation of the circuit,
From the program file, a test instruction for checking a value of predetermined information being processed in the circuit at a predetermined timing calculated from execution of a predetermined program instruction is described in association with the program instruction. Extracting a test instruction in a state associated with the program instruction associated with the test instruction;
Steps to have the computer generate the test bench file,
A procedure for causing a computer to write the contents of an input signal file that defines input signals to be input to the circuit in the simulation into a generated test bench file;
A procedure for causing a computer to write, in a file of the test bench, a content indicating that the program instruction indicates a time at which the program instruction was called in the simulation,
The test bench is provided with a content for instructing a computer to execute the test instruction when the predetermined timing counted from the time at which the program instruction associated with the test instruction is called in the simulation is reached. Computer program for writing to a file. In order to simulate the operation of a circuit designed in a hardware description language or a system description language, a computer describes one or more program instructions to be executed on the circuit including a program memory therein in an assembly language. A computer program for generating a test bench describing a procedure for verifying the operation of the circuit from a program file having
From the program file, a test instruction for checking a value of predetermined information processed in the circuit after a predetermined clock counted from execution of a predetermined program instruction is described in association with the program instruction. A step of translating one or a plurality of the program instructions into a machine language to be executed by the circuit, and obtaining, by a computer, an address of a program memory of the circuit in which each of the program instructions translated into the machine language is stored. And the steps to
Causing the computer to extract the test instruction included in the program file from the program file in association with the address where the program instruction associated with the test instruction is stored;
Steps to have the computer generate the test bench file,
A procedure for causing the computer to write the contents of an input signal file defining input signals to be input to the circuit in the simulation in a generated test bench file in a hardware description language or a system description language, and
In the test bench file, a description instructing the computer to add a clock for each predetermined process in the simulation started by inputting the input signal to the circuit is described in a hardware description language or a system description language. To write and write in
A description that instructs the computer to represent the time at which the address was called in the simulation in the unit of the added clock is written in the test bench file in a hardware description language or a system description language. And the steps to
A description instructing the computer to execute the test instruction when the value of the added clock is a value obtained by adding the predetermined clock to the time at which the address associated with the test instruction is called, And writing the test bench file expressed in a hardware description language or a system description language in a file of the test bench.

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