JP2727941B2 - Failure analysis method for integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit and, more particularly, to an integrated circuit having a failure location specifying circuit which makes it easy to locate a failure location when the integrated circuit fails.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. 62-21573 discloses that
In order to diagnose the failure of the flip-flop circuit, the chain of flip-flop circuits is divided into an arbitrary number of circuit groups. However, in such an integrated circuit, when a clock signal distribution circuit fails, some or all of the flip-flop circuits in the circuit stop operating,
It is difficult to identify the failure location. Also, in a scan path circuit, which is one of the test circuits of an integrated circuit that has been widely used in the past, it has been difficult to specify a failure location of a failure in a clock signal distribution circuit.

[0003]

In the prior art integrated circuit, when a clock signal distribution circuit fails, it is difficult to specify the location of the failure. An object of the present invention is to specify a failure point of a clock signal distribution circuit.

[0004]

SUMMARY OF THE INVENTION Failure of the integrated circuit of the present invention
The analysis method is based on the cascade connection of multiple flip-flops.
The shift operation of the plurality of flip-flops.
A scan path for sequentially reading data;
From each output line provided for each flip-flop.
Output selection means for selecting and reading the output of the flop
In the method for analyzing a failure of an integrated circuit including
Reading the data from the source, and selecting the output.
Means for storing data in each of the plurality of flip-flops.
Reading from the scan path.
And the data read from the output selection means.
Compare the data of each of the multiple flip-flops
Obtaining a failure location.

[0005]

[0006]

[0007]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention is:
Internal clock signal generator 6 for generating an internal clock signal
A scan path input terminal 1 for scanning and inputting data from outside the internal test signal generator 7 for generating an internal test pattern signal in response to the clock signal from the internal clock signal generator 6, and a clock signal from the outside Signal input terminal 3 for selecting an external clock signal and an internal clock signal, and for inputting a selection signal for selecting a scan path input signal and an internally generated test pattern, and an input from this terminal 2 The selector 8 selects and outputs the scan path input signal from the scan path input terminal 1 and the internally generated test pattern from the internal test signal generator 7 according to the selected signal, and the internal according to the selection signal input from the selection signal input terminal 2. From the internal clock signal from the clock signal generator 6 and the clock signal input terminal A selector 9 for selecting and outputting one of an external clock signal, a clock distribution circuit 13 for distributing a clock signal selected by the selector 9, and a shift signal input for externally inputting a shift signal for performing a shift operation Terminal 4, this shift signal input terminal 4
Shift signal line 14 for transmitting the shift signal from
A group of cascade-connected flip-flops 10 for storing a signal from a selector and shifting a signal stored by a clock signal from a clock distribution circuit 13 and a shift signal from a shift signal line, the last flip-flop of a certain flip-flop group Connected to the first flip-flop of the other flip-flop group and a scan path output terminal 1
7 includes a scan path connection line 19 connecting the flip-flop 7 to the last flip-flop of the path and a scan path output terminal 17. One of the features of one embodiment of the present invention is that an address data input terminal 5 for externally inputting address data;
An address decoder 11 for explaining an address inputted from the address data input terminal, an address signal line 16 for transmitting an output of the address decoder, and a flip-flop output signal line 15 for transmitting an output signal of a flip-flop 10 constituting a scan path. , A selector 12 for selecting the output of the flip-flop 10 in accordance with an address signal supplied via an address signal line 16, and a selector output terminal 18 for outputting a selection result of the selector 12.

Next, the operation of one embodiment of the present invention will be described in detail.

A plurality of flip-flops 10 performing a shift operation when a shift signal input from a shift signal input terminal 4 is in a shift state are connected in series so as to form a shift register. A signal input from the scan path data input terminal 1 or an internally generated test signal is input to the first flip-flop of the row of flip-flops via a selector 8 for selecting a scan path signal and an internally generated test pattern signal. You. The last flip-flop is connected to the scan data output terminal 17. Each flip-flop receives a clock signal externally input from a clock signal input terminal 3 or a clock signal generated by an internal clock signal generator 6 to select and output an external clock signal and an internal clock signal. Via the clock distribution circuit 13. A selection signal for selecting an external clock signal and an internal clock signal and a selection signal for selecting a scan path signal and an internally generated test pattern signal are input from an input terminal 2 and input to the selectors 8 and 9. By the shift operation of each flip-flop, the scan path data or the internally generated test data input from the scan path input terminal 1 connects the flip-flop row to the scan path connection line 19.
Through the scan path data output terminal 17. At this time, the output of each flip-flop is collected by the selector 12 which decodes the address signal input from the address input terminal 5 by the address decoder 11 and outputs the signal of the flip-flop selected by the address signal, and corresponds to the address. The signal of the flip-flop is output to the selector output terminal 18.

In this embodiment, it is assumed that the clock distribution circuit 13 applied to the left three flip-flops in the upper stage operates normally and a failure occurs in the clock distribution circuit 13 applied to the right one of the upper flip-flops. I do. At this time, normal scan path test data can be output from the left three flip-flops of the flip-flop output lines 15 of the upper flip-flop, but no clock is supplied to the rightmost flip-flop of the upper flip-flop. The entered ska campus data is not stored. Therefore, the scan path data to be input is not output to the uppermost rightmost flip-flop. As a result, if the output data from the selector output terminal 18 is inspected, a part of the failure of the clock distribution circuit 18 can be found more than the individual output of the flip-flop.

That is, by outputting a direct output from the flip-flop 10 to the outside in addition to the scan path data connection line 19, data of an arbitrary flip-flop that has been operated even when the clock signal distribution circuit has failed can be transferred. By reading the information, the failure location can be easily specified. That is, the flip-flops whose data do not match when the data of the flip-flop row are read out in order are failure points of the clock distribution system.

In this embodiment, an internal clock generator 6 and an internal test signal generator 7 are added so that an external clock signal and a scan test signal are not required at the time of testing, but these are omitted. It is clear that there is no problem in identifying the failure location. When the scale of the test circuit becomes large, the outputs of some flip-flops are collected in the selector 12, so that the scale of the test circuit can be reduced. In some cases, even without the address data input terminal 5, the address decoder 11, and the selector 12, a predetermined function can be obtained by outputting the output of the flip-flop to the outside.

[0014]

As described above, according to the integrated circuit of the present invention, a flip-flop in which a scan data input terminal, a scan data output terminal, and a plurality of flip-flops are connected in series to form a shift resist and connected in series A flip-flop that operates when the input of the first flip-flop in the flip-flop row is connected to the scan data input terminal and the output of the last flip-flop in the flip-flop row is connected to the scan data output terminal and the shift signal is in the shift state , A shift signal input terminal, and a selector for inputting a signal from all or some outputs of the flip-flops of the flip-flop row and selecting and outputting a flip-flop corresponding to an arbitrary externally applied address signal And output the signal output from the selector to the outside of the integrated circuit Output terminal to output data from the flip-flop directly to the outside in addition to data output by the scan path connection, thereby reading data from an arbitrary flip-flop even when the clock signal distribution circuit breaks down. By confirming, it is possible to easily specify the failure location. Further, by providing a decoder for decoding an address signal in the integrated circuit, the number of input terminals of address data for selecting an arbitrary flip-flop can be reduced. A clock generation circuit, a test pattern generation circuit, a selector for selecting a clock signal output from the clock generation circuit and a clock signal input from the outside in the integrated circuit, and outputting the selected signal to the integrated circuit; By having a selector for selecting a test pattern signal output from the circuit and a signal input from the scan path data input terminal and outputting the selected signal to the integrated circuit, the test can be performed without requiring a clock signal or a test data signal from outside. There is an effect that can be done.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 scan path input terminal 2 selection signal input terminal 3 clock signal input terminal 4 shift signal input terminal 5 address data input terminal 6 internal clock signal generator 7 internal test signal generator 8 selector 9 selector 10 flip-flop 11 address decoder 12 selector 13 clock distribution circuit 14 shift signal line 15 flip-flop output signal line 16 address signal line 17 scan path output terminal 18 selector output terminal 19 scan path connection line

Claims (1)

(57) [Claims] 1. A cascade connection of a plurality of flip-flops
And the plurality of flip-flops are shifted by a shift operation.
A scan path for sequentially reading out the
From the output lines provided for each of the number of flip-flops.
Output selection means for selecting and reading the output of the flip-flop;
Reading the data from the scan path in the integrated circuit failure analysis method including:
And the plurality of flip-flops by the output selecting means.
Reading the respective data of the scan path, and the data read from the scan path and the output selection.
Of the plurality of flip-flops read from the selection means.
A step of comparing the data with each other to determine a failure location;
A failure analysis method for an integrated circuit, comprising: