JP3057192B2 - Logic simulation support system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention executes verification of hardware such as a printed circuit board or an application specific integrated circuit (hereinafter referred to as ASIC) on a general-purpose engineering workstation (hereinafter referred to as EWS). The present invention relates to a logic simulation support system to be executed. More specifically, the present invention relates to a logic simulation support system in which a method of displaying data obtained as a result of a logic simulation is devised.

[0002]

2. Description of the Related Art In recent years, with the reduction in cost and speed of general-purpose EWS and logic simulators, printed circuit boards, AS
Verification of hardware and software of ICs and the like (these are collectively referred to as target circuits) is being performed by logic simulation. FIG. 7 is a diagram showing a configuration example of a target circuit to be verified. The target circuit is composed of two target circuit 1 ₁ and 1 _2. Target circuit 1
_1, 1 in _2, 2 _1, 2 ₂ target circuit ₁ 1, 1 ₂ nuclei become generic CPU, 3 _1, 3 ₂ ROM for storing programs,
4 _1, 4 ₂ RAM, 5 _1, 5 ₂ for storing data is a user logic became circuit portion to fabricate the user. The user logics 5 ₁ and 5 ₂ are, for example, signal processing circuits including A / D converters and the like, and read from the general-purpose CPUs 2 ₁ and 2 _2.
Write access is enabled.

When the hardware and software of the target circuit shown in FIG. 7 are verified by logic simulation, a virtual model of the target circuit as shown in FIG. 8 is created. In FIG. 8, 11 ₁ and 11 ₂ are target circuit models, 1
2 ₁ and 12 ₂ are general-purpose CPU models, 13 ₁ and 13 ₂ are ROM
Model, 14 _1, 14 ₂ RAM model, 15 _1, 15 ₂ is user logic model, each object circuit ₁ 1,
1 _2, general purpose _{CPU2 1, 2 2, ROM3 1} , 3 2, RAM
4 _1, 4 _2, which is a virtual model of the user logic 5 _1, 5 _2. These models are implemented in software. A logic simulation is performed using the target circuit model as shown in FIG. 8, and the hardware and software of the target circuit are verified. For example, as a result of compiling a source file described in the C language using a C compiler, object codes formed of “0” and “1” patterns are respectively stored in ROM models 13 ₁ and 13 ₂ at the start of logic simulation. to download. Downloaded program general purpose CPU model 12 _1, 12 ₂ are respectively executed. The source file is an application program created by the user, and the C compiler is provided by the user.

[0004] One of the major issues for shortening the hardware development period is how efficiently the above-described logic simulation can be performed. Conventionally,
When performing hardware verification while checking signal waveforms by logic simulation, when displaying signal data required for verification in the target circuit model on the output waveform screen of the CRT display device, the number of output waveform screens that can be displayed simultaneously In the example of the target circuit model shown in FIG. 8, the signal data is divided into two groups for each target circuit model and displayed in order to display the waveform easily. That is, the signal data, and the signal data necessary for verification of the target circuit model 11 in _1, divided into groups and the signal data necessary for validation of the target circuit model 11 in _2, as shown in FIG. 9 the data for each group And output waveform screens # 1 and # 2, respectively. In the screen of FIG. 9, CLK is a clock for giving operation timing, XAS is a negative logic address strobe signal, HA is a host address, and XRW is a negative logic read / write signal. "16'hffff"
This data is provided as a default when the host address HA is not determined. Output waveform screen # 1, # 2
Are provided with, for example, a “PAUSE” button and a “RUN” button, respectively. By pressing the “PAUSE” button, the updating of the waveform of each output waveform screen is paused, and by pressing the “RUN” button, Updating of the waveform on the output waveform screen can be resumed. As described above, in the conventional display screen, updating of the output waveform screen can be stopped or restarted independently for each screen.

However, in the conventional display screen, if it is desired to stop updating the two output waveform screens at the same time, first press the "PAUSE" button of the output waveform screen # 1 and then press the "PAUSE" button of the output waveform screen # 2. You have to take steps to press the "button. For this reason, the screen at the time of stoppage is shown in FIG.
As shown in (1), the output simulation screens # 1 and # 2 have different simulation times for the waveforms. Therefore,
There is a problem that the waveform must be checked in consideration of the time lag between the two screens, and the waveform cannot be checked efficiently. In FIG. 10, the “PAUSE” button changes from “□” to “■” by being pressed.
Also, when it is desired to resume updating of two output waveform screens at the same time, it is necessary to take the procedure of first pressing the "RUN" button of the output waveform screen # 1 and then pressing the "RUN" button of the output waveform screen # 2. No. Therefore, as shown in FIG. 11, the screen at the time of resumption is a screen in which the simulation time of the waveforms of the output waveform screens # 1 and # 2 is shifted, and has the same problem as the case of the stop. Each time the simulation is stopped and restarted, the time lag between the two output waveform screens is accumulated. That is, in the conventional example, the waveform cannot be checked efficiently, which causes a problem that the efficiency of the logic simulation is reduced.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is intended for verifying hardware of a plurality of target circuit models while confirming signal waveforms by logic simulation. A display area for displaying an output waveform screen is provided for each target circuit model, and the update and stop of the waveform can be collectively stopped and restarted for all the display areas, thereby confirming the signal waveform. An object of the present invention is to realize a logic simulation support system in which the efficiency of a logic simulation for verifying hardware of a target circuit model is improved.

[0007]

According to the present invention, there is provided a processing control unit having a CPU, a keyboard and a mouse connected to the processing control unit, a CRT display device for displaying, and a disk storing various data and programs. A logic simulation support system configured to verify hardware of a plurality of target circuits by a logic simulation, wherein a file stored on the disk is configured,
A plurality of target circuit models that respectively simulate the functions of the plurality of target circuits, and the plurality of target circuit models are taken from the disk as input files, and hardware verification of the plurality of target circuit models is performed by logic simulation. A general-purpose logic simulator to be performed, grouping means for grouping signal data and simulation time data necessary for verification in a plurality of target circuit models obtained as a result of the logic simulation for each target circuit model, and the grouping means. Storage means for sequentially storing the grouped signal data and simulation time data on the disk; read means for reading the signal data and simulation time data stored on the disk by the storage means in groups; By means The CRT for each target circuit model by the signal data and the simulation time data read in groups to the waveform timing chart from disk
The display is displayed in different display areas of the display device, and the waveform time chart displayed in each display area is updated as the logic simulation progresses. By controlling the display means, the display time is independently controlled for each display area. Individual stop / restart means for stopping and restarting the updating of the waveform time chart, and batch stop / restart for controlling the display means to collectively stop and restart the updating of the waveform time chart displayed in the entire display area. And a logic simulation support system.

[0008]

According to the present invention, the general-purpose logic simulator verifies the hardware of a plurality of target circuit models by logic simulation. Signal data and simulation time data required for verification in a plurality of target circuit models obtained as a result of the logic simulation are grouped by the target circuit model by the grouping means.
The grouped data is sequentially stored on the disk. The data stored on the disk is read out in groups. The display means displays the read data as a waveform time chart in a different display area of the CRT display device for each target circuit model. The waveform time chart displayed in each display area is updated as the logic simulation progresses. The individual stop / resume means independently stops and restarts updating of the waveform time chart for each display area by controlling the display means. The batch stop / resume unit controls the display unit to stop and restart the update of the waveform time chart displayed in the entire display area in a batch.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG.
FIG. 1 is a diagram showing a configuration example of hardware for realizing a logic simulation support system according to the present invention. This hardware configuration example corresponds to an EWS installed in a computer system, and includes a CRT display device 20, a keyboard 30, a mouse 40, a disk 50, and a processing control unit 60. The CRT display device 20 includes a graphic,
Waveforms, characters, and the like are displayed in a display area on the screen, and the keyboard 30 is for inputting characters, symbols, and the like. The mouse 40 is used to specify a menu, an area, and the like. The disk 50 stores the following information and the like. Circuit information for logic simulation Program information for operating the circuit Logical function of each element used in circuit information Library etc. including electrical specifications Software for general-purpose logic simulator General-purpose CPU model, ROM model, RAM described later Model and User Logic Model The processing control unit 60 has a CPU 61, mainly executes a logic simulation, and stores the result of the simulation on the disk 50 or displays the result on the CRT display device 20. The processing control unit 60 includes a start unit 62, a stop unit 63, a restart unit 64, a grouping unit 65, a storage unit 66, a read unit 67, a display unit 68, an individual stop / restart unit 69, and a collective stop / restart unit 70. Is provided. Detailed operations of these means will be described later.

The system of the present invention is a system for verifying hardware of a target circuit as shown in FIG.
A virtual model of the target circuit shown in FIG. 8 is prepared, and the hardware of the target circuit is verified by logic simulation using the model.

FIG. 2 is a functional block diagram of the system of FIG. The same components as those shown in FIG. 2 are denoted by the same reference numerals. In FIG. 2, the general-purpose CPU models 12 ₁ and 12 ₂ , the ROM models 13 ₁ and 13 ₂ , the RAM models 14 ₁ and 14 _2, and the user logic models 15 ₁ and 15 ₂ form a file. Is stored. 16 is a general-purpose logic simulator, during execution of the logic simulation, a general purpose CPU model 12 _1, 12 _2, ROM Model 1
3 _1, 13 _2, RAM model 14 _1, 14 ₂ and takes in the user logic model 15 _1, 15 ₂ as the input file, performs logical simulation to verify the hardware of the target circuit model configured by these models. The general-purpose logic simulator 16 corresponds to software for a general-purpose logic simulator stored in the disk 50. The starting means 62, the stopping means 63, and the resuming means 64
Instructions for starting, stopping, and restarting the logic simulation are given. The grouping means 65 includes two target circuit models 11 ₁ and 11 ₂ obtained as a result of the logic simulation.
The signal data and the simulation time data required for the verification are divided into groups for each target circuit model. The storage unit 66 sequentially stores the signal data and the simulation time data grouped by the grouping unit 65 in the disk 50. The reading means 67 reads the signal data and the simulation time data stored in the disk 50 by the storage means 66 in groups. The display means 68 displays the disk 50 by the reading means 67.
, The signal data and the simulation time data read in groups are displayed as waveform time charts in different display areas of the CRT display device 20 for each target circuit model. The waveform time chart displayed in each display area is updated as the logic simulation progresses. The individual stop / resume unit 69 controls the display unit 68 to stop and restart the update of the waveform time chart independently for each display area. The batch stop / resume unit 70 controls the display unit 68 to stop and restart the update of the waveform time chart displayed in the entire display area in a batch.

Here, the operation of the system according to the present invention will be described. FIG. 3 is a flowchart showing a processing procedure when verifying hardware of a target circuit model by logic simulation using the system according to the present invention. Hereinafter, the processing procedure will be described. (A1) to (A10) in the description of the processing procedure correspond to the processing A1 to A10 in the flowchart of FIG. 3, respectively. (A1) The general-purpose logic simulator 16 is started. This activation is performed by the start means 62. When the general-purpose logic simulator 16 is started, first, the processing control unit 60 first executes the target circuit models 11 ₁ and 11 ₂ , a library for circuit information,
A signal file or the like in which a plurality of signal names in the target circuit model required for verification registered in advance are written from the disk 50 and input to the general-purpose logic simulator 16 to start logic simulation. (A2) When the logic simulation is started, the general-purpose logic simulator 16 stores the signal data necessary for the verification together with the simulation time data in accordance with the contents of the signal file as the simulation execution result.
In the disk 50. The stored signal data and simulation time data are stored in a grouping unit 6.
Grouped by 5 into two groups,
The storage means 66 stores the grouped signal data and simulation time data. (A3) At the same time, the reading means 67 reads the grouped signal data and simulation time data from the disk 50. (A4) The read signal data and simulation time data are displayed by the display means 68 in the form of a waveform time chart on the display area of the CRT display device 20 as output display screens # 1 and # 2. In this case, the signal data and the simulation time data grouped into two groups become display data of output display screens # 1 and # 2, respectively. FIG. 4 shows the CRT display device 2 at this time.
It is a figure showing an example of a screen of 0. In the screen of FIG.
K1 and CLK2 are the target circuit models 11 ₁ and 11 ₂ , respectively.
, XAS1 and XAS for giving the operation timing of
2 each target circuit model 11 _1, 11 ₂ of the negative logic of the address strobe signal, HA1, HA2, respectively target circuit model 11 _1, 11 ₂ of the host address, XRW
Reference numerals 1 and XRW2 denote negative logic read / write signals of the target circuit models 11 ₁ and 11 ₂ , respectively. Output display screen # 1 of FIG. 4 displays the simulation result of the target circuit model 11 ₁ from the simulation time 0 to T10. The simulation result is displayed in the form of a waveform time chart. Similarly, the output display screen # 2 of FIG.
From simulation time 0 displaying a simulation result of the target circuit model 11 ₂ to T10. As the simulation progresses, the waveform time charts of the output display screens # 1 and # 2 are updated every moment. (A5) Check whether the output display screen has reached the first verification location. (A6) When the output display screen reaches the first verification point, the “PAUSE” button in the command operation screen in the screen of the CRT display device 20 is clicked with the mouse 40. In response to this, the collective stop / restart means 70 collectively stops updating the waveforms of the output display screens # 1 and # 2. During this time, the simulation itself is being executed without stopping. This processing is performed by the batch stop / resume means 70. FIG. 5 is a diagram showing an example of the screen of the CRT display device 20 at this time. "PAUSE" button B clicked in FIG.
1 changes from “□” to “■”. FIG output display screen # 1 of 5 is displaying a simulation result of the target circuit model 11 ₁ in a section from the simulation time T11 to T20. Similarly, the output display screen # 2 in FIG.
Simulation and displays the simulation result of the target circuit model 11 _second interval from time T11 to T20. (A7) Next, verification by first confirming the waveform is performed using the output display screens # 1 and # 2 in FIG. In the screen example of FIG. 5, the setup times t _s1 and t of the host addresses HA1 and HA2 when the address strobe signals XAS1 and XAS2 in the output display screens # 1 and # 2 change from “1” to “0”. Verify that _s2 matches the specified time. (A8) When the first verification is completed, the CRT display device 20
Is clicked with the mouse 40 on the "RUN" button in the command operation screen in the screen of FIG. In response to this, the batch stop / resume means 70 releases the batch stop of the update performed so far, and restarts the update of the waveforms of the output display screens # 1 and # 2 collectively. FIG. 6 is a diagram showing an example of the screen of the CRT display device 20 at this time. In FIG. 6, "clicked"
The “RUN” button B2 is “■.” (A9) After that, all the verification points are confirmed by repeating the same procedure (A10) The logic simulation ends.

In the embodiment, similarly to the conventional example,
"PAUSE" button and "" for each output display screen # 1, # 2
RUN "buttons are provided for each of these" RUN "buttons.
The update and stop of the waveform may be independently stopped and restarted for each output display screen by pressing the “PAUSE” button and the “RUN” button, and such processing is performed by the individual stop / resume means 69. The “PAUSE” button B1 And "RUN" button B
2, and "P" provided for each of the output display screens # 1 and # 2.
The "AUSE" button and the "RUN" button each have an attribute. Based on the attribute of the pressed button, all output display screens are collectively stopped and restarted of display waveform update, and the output display screen is displayed. In this embodiment, when the update of the waveform is stopped and restarted independently, the timing at which the "PAUSE" button is pressed is delayed and the displayed waveform when the update is stopped deviates from the desired verification position. By clicking another command (not shown) in the command operation screen, the waveforms of the output display screens # 1 and # 2 can be displayed shifted to the front and back with respect to the time axis. Is obtained from the data stored in the disk.Although the embodiment has described the case where two output waveform screens # 1 and # 2 are displayed, the present invention is not limited to this. In this case, the number of target circuit models is also 3. In the embodiment, the case where the signal waveform to be displayed is only the digital waveform has been described, but the present invention is not limited to this, and the signal waveform to be displayed is not limited to this. It may be an analog waveform only or both a digital waveform and an analog waveform.

[0014]

According to the present invention, when verifying the hardware of a target circuit model while confirming a signal waveform by a logical simulation, data obtained as a result of the logical simulation is grouped for each target circuit model. After storing it on the disk, it is read out and displayed. Therefore, for the display area provided for each target circuit model for displaying the output waveform screen, not only can the display waveform updating be stopped and restarted independently for each display area, but also the entire display area can be displayed. The updating and updating of the display waveform can be stopped and restarted collectively. As a result, the simulation time does not deviate between the display areas even if the update of the waveform is stopped and restarted for all the display areas. From this, it is possible to easily confirm the signal waveform without considering a shift in the simulation time between the display regions. From the above, it is possible to improve the efficiency of the logic simulation for verifying the hardware of the target circuit model while checking the signal waveform.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of hardware for realizing a logic simulation support system according to the present invention.

FIG. 2 is a functional block diagram of the system of FIG. 1;

FIG. 3 is a flowchart for explaining the operation of the system according to the present invention.

FIG. 4 is a diagram showing an example of a screen displayed in the system according to the present invention.

FIG. 5 is a diagram showing an example of a screen displayed in the system according to the present invention.

FIG. 6 is a diagram showing an example of a screen displayed in the system according to the present invention.

FIG. 7 is a diagram illustrating a configuration example of a target circuit.

FIG. 8 is a diagram showing a virtual model of the target circuit of FIG. 7;

FIG. 9 is a diagram showing an example of a screen displayed in a conventional system.

FIG. 10 is a diagram showing an example of a screen displayed in a conventional system.

FIG. 11 is a diagram showing an example of a screen displayed in a conventional system.

[Explanation of symbols]

11 ₁ , 11 ₂ Target circuit model 12 ₁ , 12 ₂ General-purpose CPU model 13 ₁ , 13 ₂ ROM model 14 ₁ , 14 ₂ RAM model 15 ₁ , 15 ₂ User logic model 16 General-purpose logic simulator 20 CRT display device 30 Keyboard 40 Mouse 50 disk 60 processing control unit 61 CPU 62 starting means 63 stopping means 64 resuming means 65 grouping means 66 storing means 67 reading means 68 displaying means 69 individual stopping / resuming means 70 collective stopping / resuming means

────────────────────────────────────────────────── ─── Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G06F 17/50 G01R 13/20 G01R 13/28 JICST file (JOIS)

Claims (1)

(57) [Claims] 1. A processing control unit having a CPU, a keyboard and a mouse connected to the processing control unit, and a CR for displaying.
A logic simulation support system comprising a T display device and a disk storing various data and programs, and verifying hardware of a plurality of target circuits by a logic simulation. None, a plurality of target circuit models that respectively simulate the functions of the plurality of target circuits, and the plurality of target circuit models taken from the disk as input files, and a hardware simulation of the plurality of target circuit models is performed by logic simulation. A general-purpose logic simulator for performing verification; grouping means for grouping signal data and simulation time data necessary for verification in a plurality of target circuit models obtained as a result of the logic simulation for each target circuit model; Guru by means Storage means for sequentially storing the divided signal data and simulation time data on the disk; read means for reading out the signal data and simulation time data stored on the disk by the storage means in groups; The signal data and the simulation time data read from the disk in groups by the reading means are converted into a waveform time chart to form the CR for each target circuit model.
A display means for displaying in a different display area of the T display device and updating the waveform time chart displayed in each display area with the progress of the logic simulation; Individual stop / restart means for stopping and restarting the update of the waveform time chart; and collectively stopping the stop and restart of the update of the waveform time chart displayed in the entire display area by controlling the display means. A logic simulation support system comprising: a restart unit.