JPH04333171A - Device for simulation - Google Patents

Abstract

PURPOSE:To increase operation speed and to reduce the load of a computer by executing a simulation in such a way that all or a part of a logic circuit is constituted by means of hardware on the gate array of EPLD. CONSTITUTION:Gate array 5 is constituted by EPLD(erasable and programmable logic device) which electrically programs the connection of and between logic elements and also erases it. Control by a gate array programmer 4 from the computer 1 with an interface(I/F) 3 erases past information on gate array 5, then, the logic circuit is constituted. Therefore, an output is immediately obtained from an output terminal in such a way that software only inputs input signal pattern data to the input terminal without the necessity of the simulation. In this case, a part of the objective circuit simulates in the circuit on gate array 5 and the others execute the simulation by software.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit simulation apparatus.

0002

2. Description of the Related Art FIG. 4 is a block diagram showing the configuration of a conventional digital logic circuit simulation apparatus.
(abbreviated as U), and the simulation is performed on CPU2.
It is program-controlled and executed entirely in software.

10 in FIG. 5 is an example of a logic circuit to be simulated, and 11 is software modeling data of the target circuit 10. In FIG. That is, the target circuit 10
The operation can be expressed in software using modeling data 11.

FIG. 7 is a flowchart showing a conventional method, and 71 to 77 indicate each step. Load the modeling data created in advance for the target circuit 10 (
Step 72) Save input signal pattern data to file 7
4 into the CPU 2, and the software executes the simulation shown in the modeling data 11 in FIG.
Output 1 is determined and written to the file 75 shown in FIG. 7 as output signal result data. The program step to be set is determined by the modeling data 11 and the input signal pattern data 74, and when the numerical values of the setting step and the execution step match, the simulation ends and the output signal result is displayed on the display. (Step 77).

[0005]

[Problem to be Solved by the Invention] The problem to be solved is that since all simulations are performed using software in conventional simulation devices, the processing speed is
The problem is that the more complex the target circuit 10 is, the longer the processing time will be. Further, there is a problem in that a large load is applied to the CPU 2 to perform this simulation, and when the computer 1 is operated in multitasking, the processing speed of other programs is also affected. The present invention has been made to solve this problem, and an object of the present invention is to provide a simulation device that can reduce the load on the CPU and quickly execute simulation processing.

[0006]

[Means for Solving the Problems] The most important feature of the simulation apparatus according to the present invention is that all or part of the target circuit is constructed using a programmable gate array.

[0007]

In the present invention, by configuring all or part of the target circuit using a programmable gate array, it is possible to improve the speed of simulation and reduce the load on the CPU.

[0008]

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 4 is a gate array programmer, and 5 is a gate array. The gate array 5 is an EPLD (erasab) in which logic elements and connections between logic elements can be electrically programmed and erased.
le and programmable lo
gic device). External I/
The portion consisting of the F3, gate array programmer 4, and gate array 5 is tentatively referred to as a simulation accelerator.

For example, if the target circuit 10 is as shown in FIG. , the logic circuit shown in FIG. 2 can be constructed. By configuring such a logic circuit, you can immediately obtain an output from the output terminal by simply inputting the input signal pattern data to the input terminal in Figure 2, without the need for software simulation. .

However, it is easier to configure the gate array 5 and the gate array programmer 4 by limiting the number of types of logic circuits that can be configured in the gate array 5. 5 may not always be possible. In such a case, part of the target circuit will be simulated by the circuit on the gate array 5, and the rest will be simulated by software.

FIG. 6 is a flowchart showing the operation of the present invention, and 61 to 69 and 81 to 84 indicate each step. Part or all of the model represented by the loaded modeling data is configured on the gate array 5 in steps 63 and 64. The embodiment shown in FIG. 6 shows a case where some models are configured in the gate array 5. Other models are processed in software at step 66. In step 65, the simulation accelerator is called and the processes in steps 81 to 83 are executed.

The input signal pattern data is divided into data to be input to the gate array 5 (temporarily referred to as the first type of input signal) and other data (temporarily referred to as other input signals). Processed by step 81 or step 66. Further, the output of the data processed in step 83 is outputted in step 66 as an intermediate output.
Similarly, the output of the data processed in step 66 may be sent to step 81 as an intermediate output, but in the embodiment shown in FIG. 6, the output of software processing is input to the hardware. This shows the case where there is no problem. As described above, part of the output of step 66 and the output of step 83 is converted into output signal result data 8.
It becomes 8. Note that steps 68 and 69 are similar to steps 76 and 77 in FIG.

FIG. 3 is a block diagram showing another embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and 31
, 32 are external I/Fs, 41 and 42 are gate array programmers, and 51 and 52 are gate arrays. Compared to the device shown in FIG. 1, the device shown in FIG. 3 is equipped with multiple sets of simulation accelerators, so
It is possible to configure a more complex hardware model and further reduce the load on the CPU 2.

[0014]

As described above, the simulation apparatus of the present invention has advantages such as being able to quickly execute logic circuit simulation and reducing the load on the CPU.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a connection diagram showing a logic circuit configured in the gate array of the present invention.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional device.

FIG. 5 is a diagram showing a simulation target circuit and its modeling data.

FIG. 6 is a flowchart showing the operation of an embodiment of the present invention.

FIG. 7 is a flowchart showing the operation of a conventional device.

[Explanation of symbols]

1. Calculator 2 CPU 3 External I/F 4 Gate array programmer 5 Gate array 10 Target circuit 11 Modeling data

Claims (1)

[Claims] 1. A gate array capable of electrically programming and erasing logic elements and connections between logic elements under external control; a gate array programmer for controlling programming and erasing of the gate array;
Means for configuring all or part of a logic circuit to be simulated in the gate array via the gate array programmer, and means for configuring pattern data of input signals to be input to the logic circuit to be simulated in the gate array. Separating into a first type of input signal and other input signals, which are input signals to a logic circuit configured in the first type,
A simulation device comprising means for inputting the first type of input signal to the logic circuit and simulating the other input signals under program control.