JPH10326188A - Resource competition check device, assemble device, link device, instruction pipeline simulation device, resource competition check method, and medium recording resource competition check program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resource competition check device that can automatically check a resource competition and that can shorten the period for developing a program. SOLUTION: The resource competition check device 30 is provided with a starting point information setting part 36 for extracting an instruction to become the object of resource competition based on the kinds of instructions and extracting the number of stages to become the object of resource competition for this instruction and a tract part 37 for judging whether or not the resource competition is to occur based on the address and stage number of instruction extracted by the starting point information setting part 36.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU (Central Processing Unit) operated by an instruction pipeline,
Regarding resource conflicts of microcode such as a DSP (Digital Signal Processor), in particular, a resource conflict check device, an assembling device, a link device, an instruction pipeline simulation device, and a resource conflict for detecting in advance a resource conflict occurring in an instruction pipeline The present invention relates to a check method and a medium recording a resource conflict check program.

[0002]

2. Description of the Related Art In recent years, various functions have been improved in hardware technology and software technology in order to realize a high-performance computer. Examples of the hardware technology include improvement of a clock frequency of a processor such as a CPU and a DSP. In software technology, there is an advance in compiler technology for reducing the number of execution instruction steps of an object program.

Along with these techniques, pipeline control, which is a technique for reducing the average number of execution cycles per instruction, is one of the most important techniques.

[0004]

In the instruction pipeline system, it is ideal to execute one instruction every one machine cycle. However, in reality, a phenomenon called pipeline disturbance such as resource contention occurs. This phenomenon includes, for example, contention for access requests to the same cache memory and contention due to use of the same arithmetic unit. If microcode is not created so that this phenomenon does not occur, there arises a problem that an intended operation cannot be realized with actual hardware or a performance is reduced.

[0005] The present invention has been made to solve the above problems, and the objects of claims 1 to 4 are as follows.
An object of the present invention is to provide a resource conflict check device capable of automatically determining whether or not resource conflict occurs.

It is an object of the present invention to provide an assembling apparatus capable of automatically determining whether or not resource contention occurs.

It is an object of the present invention to provide a link device capable of automatically determining whether or not resource contention occurs.

An object of the present invention is to provide an instruction pipeline simulation apparatus capable of automatically determining whether or not resource contention occurs.

An object of the present invention is to provide a resource conflict check method capable of automatically determining whether or not resource conflict occurs.

[0010] It is an object of the present invention to provide a medium recording a resource conflict check program capable of automatically determining whether or not resource conflict occurs.

[0011]

According to a first aspect of the present invention, there is provided a resource contention check device for extracting an instruction to be subjected to resource contention based on the type of an instruction. Stage number extracting means for extracting the number of stages to be subjected to resource contention of the instruction, and resource contention based on the address of the instruction extracted by the instruction extracting means and the number of stages extracted by the stage number extracting means. Conflict determination means for determining whether or not it occurs.

The contention determination means determines whether or not a resource contention occurs based on the address of the resource contention target instruction and the number of resource contention target stages. It is possible to extract points at which resource contention occurs in the pipeline.

According to a second aspect of the present invention, there is provided a resource contention checking device according to the first aspect, wherein the contention determining means starts tracing from the address of the instruction extracted by the instruction extracting means, and sets the number of stages. Tracing means for tracing the number of stages extracted by the extracting means to extract a checkpoint of resource conflict, and checking means for extracting a point at which resource conflict occurs based on the checkpoint extracted by the tracing means And

According to a third aspect of the present invention, there is provided a resource conflict checking apparatus according to the first or second aspect, wherein the resource conflict checking apparatus further registers an instruction for registering information on a target instruction of resource conflict. The instruction extracting means extracts the target instruction of the resource conflict from the information registered in the instruction registering means based on the type of the instruction, and the stage number extracting means extracts the resource conflict of the instruction extracted by the instruction extracting means. Is extracted from the information registered in the instruction registration means.

According to a fourth aspect of the present invention, there is provided a resource conflict checking apparatus according to any one of the first to third aspects, wherein the instruction extracting means is configured to determine whether the resource is determined based on a type of an instruction constituting the microcode. Extract the instruction that is the target of the conflict.

According to a fifth aspect of the present invention, there is provided an assembling apparatus for converting an assembly language program into a machine language, and a program instruction written in the assembly language converted by the assembly processing module. Instruction extraction means for extracting an instruction to be subjected to resource contention based on the type; stage number extraction means to extract the number of stages to be subjected to resource contention of the instruction extracted by the instruction extraction means; A conflict determining unit for determining whether or not resource conflict occurs based on the address of the instruction extracted by the extracting unit and the number of stages extracted by the stage number extracting unit;

The conflict determining means determines whether or not a resource conflict occurs based on an instruction to be subjected to resource conflict in the program described in the assembly language and the number of stages to be subject to resource conflict. Before converting a program written in assembly language into a machine language, it is possible to extract points where resource conflict occurs.

According to a sixth aspect of the present invention, there is provided a link device, comprising: link processing means for converting a program converted into a machine language into an object code; and a type of instruction of the program converted into the object code by the link processing means. Instruction extraction means for extracting an instruction to be subjected to resource contention, a stage number extraction means to extract the number of stages to be subjected to resource contention of the instruction extracted by the instruction extraction means, and an instruction extraction means. A conflict determining means for determining whether resource conflict occurs based on the address of the extracted instruction and the number of stages extracted by the stage number extracting means.

The contention determination means determines whether or not resource contention occurs based on the address of an instruction to be subjected to resource contention in the program converted into the object code and the number of stages to be subjected to resource contention. Therefore, it is possible to extract a point at which resource contention occurs before converting a program converted into a machine language into an object code.

According to a seventh aspect of the present invention, there is provided an instruction pipeline simulation apparatus, comprising: a debug unit for updating an instruction in a program; and an instruction to be subjected to resource contention based on a type of the instruction of the program updated by the debug unit. Instruction extraction means for extracting the number of stages, the number of stages for extracting the number of stages to be subjected to resource contention of the instruction extracted by the instruction extraction means, and the address and the stage of the instruction extracted by the instruction extraction means Contention determination means for determining whether or not resource contention occurs based on the number of stages extracted by the number extraction means, and simulation means for simulating the operation of the program updated by the debug means in the instruction pipeline. Simulation means.

The instruction, which is determined by the conflict determining means to cause resource conflict, can be updated by the debugging means. Therefore, the operation in the instruction pipeline can be simulated by the program in which the location where the resource conflict occurs is improved.

According to another aspect of the present invention, there is provided an instruction pipeline simulation apparatus for updating an instruction in a program and a stage for advancing an operation of the program updated by the debug unit in the instruction pipeline one stage at a time. A processing unit; and a contention determination unit configured to determine whether or not a resource contention occurs in the one-stage operation performed by the stage processing unit.

The contention determination means determines whether or not resource contention occurs during one-stage operation in the instruction pipeline, so that it is possible to extract a portion where resource contention occurs during simulation of the instruction pipeline. Become.

According to a ninth aspect of the present invention, there is provided a resource contention checking method, comprising the steps of: extracting an instruction to be subjected to resource contention based on an instruction type; and extracting the number of stages to be subjected to resource contention of the extracted instruction. And determining whether or not resource contention occurs based on the extracted instruction address and the extracted number of stages.

According to a tenth aspect of the present invention, there is provided a medium on which a resource contention check program is recorded, wherein an instruction to be subjected to resource contention is extracted based on an instruction type, and a stage to be subjected to resource contention of the extracted instruction. Extracting a number, and determining whether or not resource contention occurs based on the address of the extracted instruction and the extracted number of stages.

[0026]

FIG. 1 is a diagram showing the appearance of a resource contention checking device according to the present invention. The resource conflict check device includes a computer body 1, a graphic display device 2, a magnetic tape device 3, a magnetic tape 4, a keyboard 5, a mouse 6, a CD-ROM (Compact Disk-Reat).
Only Memory) device 7, CD-ROM 8, and communication modem 9. The resource conflict check program is supplied by a recording medium such as the magnetic tape 4 or the CD-ROM 8. The resource conflict check program is executed by the computer main body 1, and the operator checks the resource conflict by operating the keyboard 5 or the mouse 6 while watching the graphic display device 2. Further, the resource conflict check program may be supplied to the computer main body 1 via a communication modem by another computer via a communication line.

FIG. 2 is a block diagram showing the configuration of the resource contention checking device of the present invention. The computer main body 1 shown in FIG. 1 has a CPU 10 and a ROM (Read Only Memory).
y) 11, a RAM (Random Access Memory) 12 and a hard disk 13 are included. The CPU 10 includes a graphic display device 2, a magnetic tape device 3, a keyboard 5, a mouse 6, a CD-ROM device 7, a communication modem 9,
The processing is performed while inputting / outputting data to / from the OM 11, the RAM 12, or the hard disk 13. Magnetic tape 4
Alternatively, the resource conflict check program recorded on the CD-ROM 8 is
Alternatively, the data is temporarily stored in the hard disk 13 via the CD-ROM device 7. The CPU 10 has a hard disk 13
A resource conflict check program from RAM 12
To check for resource conflicts. Hereinafter, a resource conflict check device according to each embodiment of the present invention will be described.
2 and the configuration block diagram of the resource conflict check device shown in FIG. 2 are common to each embodiment.

[First Embodiment] FIG. 3 is a diagram showing a schematic configuration of a resource conflict check apparatus according to a first embodiment of the present invention. The resource contention checking device includes an input unit 31 to which microcode is input, a resource contention check unit 32 for checking resource contention of instructions constituting the microcode, and a result output by the resource contention check unit 32. Output unit 33,
And storage unit 34 for storing information of various tables
including.

The input unit 31 includes a microcode input unit 35 to which a microcode is input. The resource conflict check unit 32 extracts an instruction that requires a resource conflict check from the instructions constituting the microcode input to the input unit 31, and starts information such as the address of the instruction and the number of stages in which the conflict may occur. , A tracing unit 37 for tracing based on the starting point information set by the starting point information setting unit 36, and a checking unit for determining whether or not a resource conflict occurs. 38. The storage unit 34 includes an instruction information storage table 39 for storing instructions constituting the microcode and instructions fetched next to the instructions,
A resource conflict check correspondence table 40 for storing check items and the number of stages of instructions that may cause resource conflict, a start point information storage table 41 for storing start point information set by the start point information setting unit 36, and a resource conflict And a checkpoint setting table 42 for storing checkpoints and check items of an instruction in which an error occurs.

The microcode input unit 35 stores the instructions constituting the input microcode in the instruction information storage table 39. The starting point information setting unit 36 receives the instructions constituting the microcode input to the microcode input unit 35, stores information of instructions fetched in the next cycle of each instruction in the instruction information storage table 39, By referring to the resource conflict check correspondence table 40, an instruction that needs to be checked for resource conflict is extracted, and the address of the instruction, the check item, and the number of stages where the conflict can occur are stored in the start point information storage table 41.
And stores it in the stack as trace start point information in the trace unit 37.

The tracing unit 37 traces from the address of the instruction to the number of stages where resource contention can occur, based on the start point information stored in the stack by the start point information setting unit 36, and sets the checkpoint as a checkpoint. Set in table 42. The check unit 38 determines whether or not resource contention occurs based on the checkpoint set by the trace unit 37, and outputs the determination result to the output unit 33.

FIG. 4 is a flowchart showing a processing procedure of the resource conflict check device according to the first embodiment of the present invention. First, the microcode input unit 35 inputs a command constituting a microcode, and stores the command in the command information storage table 39 (S1). Start point information setting unit 36
Adds the information of the instruction fetched in the next cycle to the instruction information storage table 39 based on the instruction stored in the instruction information storage table 39. Then, by referring to the resource conflict check correspondence table 40, an instruction that requires a resource conflict check is extracted, the check item of the instruction, the number of stages where a conflict can occur is extracted from the resource conflict check correspondence table 40, and the starting point information is stored. The information is stored in the table 41 and also stored in the stack as trace start point information (S2).

Next, based on the instruction stored in the stack in step S2, the tracing unit 37 traces, from the address of the instruction, the number of stages in which resource contention occurs, and sets a checkpoint as a trace result to a checkpoint. It is stored in the table 42 (S3). Then, the checking unit 38 determines whether or not resource contention occurs based on the checkpoint set in step S3 (S4). Finally, the output unit 33 outputs the result of the determination in step S4.

FIG. 5 is a flowchart for explaining step S1 of FIG. 4 in more detail. The microcode input unit 35 stores the instructions constituting the input microcode in the instruction information storage table 39. The start point information setting unit 36 determines an instruction to be fetched next from the instruction and the address of the instruction as shown in FIG. 6, and stores the instruction in the instruction information storage table 39 (S11).

FIG. 7 is a flowchart showing the processing procedure of step S2 in FIG. 4 in more detail. The start point information setting unit 36 fetches one instruction from the instruction information storage table 39 (S21), and when there is no instruction to be fetched, judges that all instructions have been processed (S22, Yes), and proceeds to step S3 in FIG. The process proceeds to. If the instruction fetched in step S21 is not the last instruction (S22,
No), it is determined whether or not the instruction is an instruction to be checked for resource conflict.

If the instruction is an instruction to be checked for resource conflict (S23, Yes), a check item for resource conflict and the number of stages at which resource conflict can occur are set in the start point information storage table 41, and the information is stacked. And the process proceeds to step S25. If the fetched instruction is not a resource conflict check target instruction (S
23, No), the information of the instruction to be fetched next is stored in the instruction information storage table 39, and the process returns to step S21 to repeat the above processing.

FIG. 8 is a flowchart for explaining the processing procedure of step S3 in FIG. 4 in more detail. First, one start point information is taken out of the stack (S31). If the stack is empty (S32, Yes), the process proceeds to step S4 in FIG. If the stack is not empty (S32,
No), the check item is taken out of the stack (S3
3), it is determined whether or not there is a check item (S3)
4).

When there is no check item in the stack (S3
4, No), returning to step S31 and repeating the above processing. If there is a check item in the stack (S3
(4, Yes), trace the number of stages where resource contention can occur from the address of the instruction (S35), register this point as a checkpoint in the checkpoint setting table 42 (S36), return to step S33, and perform the above processing. Is repeated.

FIG. 9 is a flowchart for explaining the processing procedure of step S4 in FIG. 4 in more detail. First, the check unit 38 extracts checkpoint information from the checkpoint setting table 42 (S41). If there is no checkpoint in the checkpoint setting table 42 (S42, No), the process proceeds to step S5 in FIG. If there is a checkpoint in the checkpoint setting table 42 (S42, Yes), check items are extracted (S43).

If there is no check item in the check point setting table 42 (S44, No), step S41
Return to and repeat the above processing. If there is a check item in the checkpoint setting table 42 (S44, Y
es), it is checked whether or not resource contention occurs based on the checkpoint (S45), and the process returns to step S43 and repeats the above processing.

Next, the specific processing of the resource conflict check device when the microcode shown in FIG. 10 is input to the microcode input unit 35 will be described with reference to the contents of various tables shown in FIGS. I will explain it.

When an instruction constituting the microcode shown in FIG. 10 is input, the microcode input unit 35 stores the address and the instruction in the instruction information storage table shown in FIG. In addition, the start point information setting unit 36 stores the information of the next fetched instruction in the instruction information storage table 39, as shown in FIG. 12, based on the instructions constituting the microcode of FIG.

In the instructions shown in FIG.
The MV instruction at the address is an instruction in which a write conflict occurs in three stages as shown in FIG. The ADD instruction at address 1 is an instruction in which contention for an arithmetic unit occurs when the number of stages is five and write competition occurs when the number of stages is six as shown in FIG.

First, the microcode input unit 35 is configured as shown in FIG.
The microcode indicated by 0 is input, and the address and the instruction shown in FIG. 12 are stored in the instruction information storage table 39 (S11).

The start point information setting unit 36 extracts the MV instruction at address 0 from the instruction information storage table 39 (S21). The start point information setting unit 36 refers to the resource conflict check correspondence table 40 shown in FIG.
It is determined that the V instruction is an instruction to be checked for resource conflict (S23, Yes), and as shown in FIG. 13, an address "0", an instruction "MV", and a check item "write conflict" are stored in the start point information storage table 41. , And the number of stages “3” are set and stored in the stack (S24).

Since the instruction fetched next to the MV instruction at address 0 is an ADD instruction, ADD is stored in the instruction information storage table 39 as the next fetched instruction (S25). Then, returning to step S21, the ADD instruction at address 1 is taken out from the instruction information storage table 39 (S21). The start point information setting unit 36 refers to the resource conflict check correspondence table 40 to
It is determined that the instruction is an instruction to be checked for resource conflict, and an address “1”, an instruction “ADD”, a check item “operation unit conflict”, and the number of stages “5” are stored in the start point information storage table 41. Further, since the ADD instruction is an instruction that may cause a write conflict, the check item “write conflict” and the number of stages “6” are set in the start point information storage table 41 and stored in the stack (S24). Then, the start point information setting unit 36 stores the JA instruction as the instruction fetched next to the ADD instruction in the instruction information storage table 3.
9 (S25).

Next, the starting point information setting unit 36 extracts the JA instruction at address 2 from the instruction information storage table 39 (S2).
1). By referring to the resource conflict check correspondence table 40, the start point information setting unit 36 determines that the JA instruction is not a resource conflict check target instruction (S23,
No), the fetched MV instruction at address 5 is stored in the instruction information storage table 39 (S25).

The above processing is repeated, and the starting point information setting unit 36
Are the instruction information storage table 39 shown in FIG.
3. The start point information storage table 41 shown in FIG.
Respectively. FIG. 14 shows information stored in the stack at this time.

Next, the tracing unit 37 extracts the starting point information G1 from the stack (S31). And the tracing unit 3
7 takes out a write conflict corresponding to G1 as a check item (S33). Then, the tracing unit 37 traces from the address 0 by the number of stages 3 and registers the checkpoint “2” in the checkpoint setting table 42 as a point where a write conflict may occur. Trace part 3
7 traces based on the information of the next fetched instruction stored in the instruction information storage table shown in FIG.

Next, the trace unit 37 outputs G
The start point information of No. 2 is extracted (S31), the ADD instruction is traced (S35), and the checkpoints "6" and "7" of the arithmetic conflict and the write conflict, which are the check items, are stored in the checkpoint setting table 42. It is registered (S36).

Similarly, the trace unit 37 fetches the MV instruction of G3 from the stack (S31), performs tracing (S35), and sets the checkpoint "7" of the MV instruction in FIG.
5, the information is registered in the checkpoint setting table 42 (S36).

Next, the check section 38 extracts the data of the check point "2" from the check point setting table 42 (S41). Since there is only one data with a checkpoint of “2” in the checkpoint setting table 42, it is determined that resource contention does not occur (S45). Also, since there is only one checkpoint “6” data in the checkpoint setting table 42, it is determined that no resource contention occurs at the checkpoint “6”. However, the data of the checkpoint "7" is stored in the checkpoint setting table 42.
Since there are two items, "write conflict" of the ADD instruction and "write conflict" of the MV instruction, they are extracted as points at which resource conflict occurs (S45).

The output unit 33 outputs the point at which the resource conflict extracted by the check unit 38 occurs (S
5). Then, the process ends.

In the present embodiment, an example has been described in which an instruction constituting microcode is used as an object to be checked for resource conflict. However, an instruction created in a normal assembler language or a program compiled from a program created in a high-level language is used. Etc. can be applied.

As described above, the resource contention checking device according to the present embodiment can automatically check for resource contention, which has conventionally been performed manually, so that the development period of microcode can be reduced. It became.

[Second Embodiment] FIG. 16 is a block diagram showing a schematic configuration of a resource conflict check device according to a second embodiment of the present invention. The resource conflict check device according to the present embodiment differs from the resource conflict check device according to the first embodiment shown in FIG. 3 only in that a resource conflict information input unit 43 is added to the input unit. Therefore, the reference numeral of the input unit in the present embodiment is set to 31 '. Further, the configuration and functions of the other parts are the same as those of the resource conflict check device in the first embodiment shown in FIG. 3, and thus detailed description will not be repeated.

FIG. 17 is a flowchart for explaining the details of the processing procedure (step S1 in FIG. 4) in the input unit 31 'of the resource conflict check device according to the present embodiment. First, the microcode input unit 35 inputs a command constituting a microcode, and the resource conflict information input unit 43 inputs resource conflict information (S12). The resource conflict information is information for updating the contents of the resource conflict check correspondence table 40 shown in FIG. 11, and can be easily changed when the number of stages or check items in which resource conflict may occur is changed. Information.

Next, the microcode input unit 35 inputs the instructions constituting the microcode into the instruction information storage table 39.
To be stored. The resource conflict information input unit 43 stores the resource conflict information in the resource conflict check correspondence table 40 (S13). Then, the process proceeds to step S2 in FIG. 4 to perform the following processing.

The resource conflict information input unit 43 reads the contents of the resource conflict check correspondence table 40 shown in FIG.
When the information is updated to the resource conflict check information shown in FIG. 18, the processing in steps S2 to S4 in FIG.
Are stored in the start point information storage table 41, and the checkpoints shown in FIG. 20 are stored in the checkpoint setting table. As shown in the information stored in the checkpoint setting table 42 in FIG.
Since there are no duplicate check points, the check unit 38
Outputs that no resource contention occurs, and outputs
Will output that effect.

As described above, the resource contention checking apparatus according to the present embodiment can easily change the number of stages or check items where resource contention can occur and check again. Development time can be shortened.

[Third Embodiment] FIG. 21 is a block diagram showing a schematic configuration of an assembling apparatus according to a third embodiment of the present invention. The assembling apparatus includes an assembly processing unit 52 for converting a program described in an assembly language into a machine language, and a resource conflict checking device 30 for determining whether or not resource conflict occurs.
Resource conflict check device 30 has the same configuration and function as resource conflict check device 30 in the first embodiment shown in FIG. 3, and thus detailed description will not be repeated.

The program described in the assembly language is input to the resource conflict check device 30 to determine whether or not resource conflict occurs. The program described in the assembly language is stored in the assembly processing unit 52.
Is converted into a machine language and input to the link device 53. The link processing unit 54 in the link device 53 generates and outputs an object code from the input machine language.

As described above, the assembler according to the present embodiment can simultaneously check for resource conflicts when writing a program in assembler language.
The program development period can be shortened.

[Fourth Embodiment] The assembling apparatus according to the fourth embodiment has the same structure as that of the assembling apparatus according to the third embodiment shown in FIG. However, the resource conflict check device is different only in that it is the resource conflict check device 30 'in the second embodiment shown in FIG. Therefore, detailed description of the configuration and functions of the overlapping portions will not be repeated.

The assembling apparatus according to the present embodiment includes:
In addition to the effects described in the third embodiment, there is an effect that the operation of the instruction pipeline can be easily changed.

[Fifth Embodiment] FIG. 22 shows a fifth embodiment.
2 is a block diagram showing a schematic configuration of a link device in FIG. The link device 56 includes a link processing unit 54 for generating an object code from the input machine language, and a resource conflict check device 30 for determining whether resource conflict occurs.

The link processing unit 54 in the link device 56
An object code is generated from the machine language input from the assembling device 55. The generated object code is input to the resource conflict check device 30, and it is determined whether resource conflict occurs. As described above, the link device 56 according to the present embodiment can check whether or not a resource conflict occurs for the entire object code.

For example, the microcode shown in FIG.
When the microcode shown in FIG. 10 is input to the link device 56, an object code shown in FIG.
The resource conflict check device 30 can detect that a write conflict occurs between the ADD instruction at address 0 and the MV instruction at address 3 of the object code in FIG.

As described above, the link device according to the present embodiment makes it possible to determine whether or not resource contention occurs for the entire generated object code, thereby shortening the microcode development period. Becomes possible.

Sixth Embodiment A link device according to a sixth embodiment of the present invention has the same configuration as the link device according to the fifth embodiment shown in FIG. However, the only difference is that the resource conflict check device is replaced with the resource conflict check device 30 'in the second embodiment shown in FIG. Therefore, detailed description of the same configurations and functions will not be repeated.

The link device according to the present embodiment has an effect that the operation in the instruction pipeline can be easily changed in addition to the effect described in the fifth embodiment.

[Seventh Embodiment] FIG. 25 is a block diagram showing a schematic configuration of an assembling apparatus and a link apparatus according to a seventh embodiment of the present invention. Assembling device 51
Since the assembling device in the third embodiment shown in FIG. 21 and the link device 56 have the same configuration and function as the link device in the fifth embodiment shown in FIG. 22, detailed description will not be repeated. With the configuration shown in FIG. 25, it is possible to check resource conflicts when creating a program in assembly language, and to check resource conflicts for the entire generated object code.

[Eighth Embodiment] An assembling apparatus and a link apparatus according to an eighth embodiment of the present invention have the same configurations as the assembling apparatus and the link apparatus according to the seventh embodiment shown in FIG. However, the only difference is that the resource conflict check device 30 is replaced by the resource conflict check device 30 'in the second embodiment shown in FIG. Therefore, detailed description of the same configurations and functions will not be repeated.

The assembling apparatus and link apparatus according to the present embodiment have an effect that the operation of the instruction pipeline can be easily changed in addition to the effect described in the seventh embodiment.

[Embodiment 9] FIG. 26 shows a ninth embodiment.
FIG. 2 is a block diagram showing a schematic configuration of an instruction pipeline simulation device in FIG. The instruction pipeline simulation device includes a debug unit 62 for updating instructions in a program, a simulation unit 63 for simulating the operation of the instruction pipeline, and a resource for determining whether or not a resource conflict occurs. A conflict checking device 30 is included. Resource conflict check device 3
0 has the same configuration and function as the resource conflict check device in the first embodiment shown in FIG. 3, and therefore, detailed description will not be repeated.

The programmer executes the created program and debugs the program while referring to the display of the contents of the register and the like. The program updated by the debug unit 62 is input to the resource conflict check device 30, and checks for resource conflict as described in the first embodiment. Then, when the debugging is completed, the programmer inputs the created program to the simulation section 63 to simulate the operation of the instruction pipeline.

As described above, the instruction pipeline simulation apparatus according to the present embodiment has an effect that a resource conflict can be checked when a program is changed, and the program after the resource conflict check can be simulated.

[Tenth Embodiment] The instruction pipeline simulation apparatus according to the tenth embodiment has the same configuration as the instruction pipeline simulation apparatus according to the ninth embodiment shown in FIG. However, the only difference is that the resource conflict check device 30 is replaced with the resource conflict check device 30 'in the second embodiment shown in FIG. Therefore, since the configuration and function of the overlapping part are the same, detailed description will not be repeated.

The instruction pipeline simulation apparatus according to the present embodiment has an effect that the operation of the instruction pipeline can be easily changed in addition to the effect described in the ninth embodiment.

[Eleventh Embodiment] FIG. 27 is a block diagram showing a schematic configuration of an instruction pipeline simulation apparatus according to an eleventh embodiment of the present invention. The instruction pipeline simulation device includes a debug unit 62 for updating instructions constituting microcode, and a simulation unit 72 for simulating the operation of the instruction pipeline. The simulation unit 72
Includes an instruction setting unit 73 for setting the instruction at the address indicated by the program counter, and an instruction analysis unit 74 for analyzing the processing of each stage in the instruction pipeline.

FIG. 29 is a flowchart showing a processing procedure of the instruction pipeline simulation apparatus according to the eleventh embodiment of the present invention. First, the instruction setting unit 73 sets 0 to the program counter (S50). The instruction setting unit 73 reads an instruction from the address indicated by the program counter (S51), and determines whether or not there is an instruction (S51).
52).

If there is no instruction at the address indicated by the program counter (S52, No), the process ends. Also,
If there is an instruction at the address indicated by the program counter (S
52, Yes), and registers the read instruction in the list (S
53). Then, the instruction setting unit 73 increments the value of the program counter (S54).

Next, the instruction analysis unit 74 extracts an instruction from the list (S55), and determines whether there is an instruction whose analysis has not been completed (S56).

When there is no instruction whose analysis has not been completed (S56, No), the instruction analyzer 74 returns to step S51 and repeats the above processing. In addition, the instruction analysis unit 74 determines that there is an instruction whose analysis has not been completed (S56, Ye
s) The processing corresponding to the instruction is executed (S57). Then, the instruction analysis unit 74 determines whether or not a resource conflict occurs in the analysis of the instruction (S58).

The instruction analysis unit 74 sets the processing of the next stage (S59), and determines whether or not the processing of the instruction in the instruction pipeline has been completed (S60).

When the processing of the instruction in the instruction pipeline is completed (S60, Yes), the instruction is deleted from the list (S61), and the process returns to step S55 to repeat the above processing. If the processing of the instruction in the instruction pipeline is not completed (S60, No), step S55
And the above processing is repeated.

Next, the processing of the flowchart shown in FIG. 29 will be specifically described with reference to FIG. FIG.
11H is a diagram illustrating processing of each stage in the instruction pipeline of the instruction of the program illustrated in FIG.

(1) First Cycle (PC = 0) First, 0 is set in the program counter (S50).
Then, the instruction setting unit 73 extracts the MV instruction from the address 0 (S51). The instruction setting unit 73 registers the MV instruction in the list (S53), and increments the program counter (S54). The state of each stage in the instruction pipeline at this time is as shown in FIG.

(2) Second cycle (PC = 1) The instruction setting section 73 takes out the ADD instruction from the address 1 indicated by the program counter (S51), and registers the ADD instruction in the list (S53). The instruction analyzing unit 74 extracts the MV instruction from the list (S55), and outputs the second MV instruction corresponding to the MV instruction.
Stage processing is performed (S57). At this point, the state of each stage in the instruction pipeline is as shown in FIG.

(3) Third Cycle (PC = 2) The instruction setting section 73 reads the JA instruction from the address 2 indicated by the program counter (S51) and registers the JA instruction in the list (S53). The instruction analysis unit 74 calculates the MV from the list.
The instruction is fetched (S55), and the process of the third stage of the MV instruction is performed (S57). Since the processing of the MV instruction ends in the third stage, the instruction analysis unit 74 deletes the MV instruction from the list (S61). The instruction analysis unit 74 extracts the ADD instruction from the list (S55), and performs the second stage processing of the ADD instruction (S57). The state of each stage in the instruction pipeline at this time is shown in FIG.
(C).

(4) Fourth Cycle (PC = 3) The instruction setting section 73 reads the NOP instruction from the address 3 indicated by the program counter (S51), and registers the NOP instruction in the list (S53). The instruction analysis unit 74 extracts the ADD instruction from the list (S55), and performs the third stage processing of the ADD instruction (S57). The instruction analysis unit 74
Extracts the JA instruction from the list (S55), and performs the second stage processing of the JA instruction (S57). The instruction analyzer 74 sets 5 in the program counter by processing the JA instruction. Also, since the JA instruction is an instruction that ends in the second stage, the instruction analyzer 74 deletes the JA instruction from the list. The state of each stage in the instruction pipeline at this time is as shown in FIG.

(5) Fifth Cycle (PC = 5) The instruction setting section 73 takes out the MV instruction from the address 5 indicated by the program counter (S51), and registers the MV instruction in the list (S53). The instruction analysis unit 74 reads the AD from the list.
The D instruction is fetched (S55), and the process of the fourth stage of the ADD instruction is performed. The instruction analysis unit 74 extracts the NOP instruction from the list (S55), and performs the second stage processing of the NOP instruction. Since the NOP instruction is an instruction to end the processing in the second stage, the instruction analysis unit 74 deletes the NOP instruction from the list (S61). The state of each stage in the instruction pipeline at this time is shown in FIG.
It becomes what is shown in.

(6) Sixth Cycle (PC = 6) The instruction setting section 73 reads the NOP instruction from the address 6 indicated by the program counter (S51), and registers the NOP instruction in the list (S53). The instruction analysis unit 74 extracts the ADD instruction from the list (S55), and performs the fifth stage processing of the ADD instruction (S57). The instruction analysis unit 74
Extracts the MV instruction from the list (S55), and performs the second stage processing of the MV instruction (S57). The state of each stage in the instruction pipeline at this time is shown in FIG.
(F).

(7) Seventh Cycle (PC = 7) The instruction setting section 73 reads the NOP instruction from the address 7 indicated by the program counter (S51), and registers the NOP instruction in the list (S53). The instruction analysis unit 74 extracts the ADD instruction from the list (S55), and performs the processing of the sixth stage of the ADD instruction. Since the ADD instruction ends the processing in the sixth stage, the instruction analysis unit 74 deletes the ADD instruction from the list (S61). Further, the instruction analyzing unit 74 extracts the MV instruction from the list (S55), and outputs the third MV instruction.
Stage processing is performed (S57). Instruction analysis unit 74
Is the third stage write of the MV instruction and the sixth stage of the ADD instruction.
Detects a conflict with the stage write,
The result is output (S58). The instruction analysis unit 74
Retrieves the NOP instruction from the list (S55),
The processing of the second stage of the instruction is performed (S57). NOP
Since the instruction is an instruction to end the processing in the second stage,
The instruction analysis unit 74 deletes the NOP instruction from the list (S
61). The state of each stage in the instruction pipeline at this time is shown in FIG.

(8) Eighth Cycle (PC = 8) The instruction setting section 73 reads the NOP instruction from the address 8 indicated by the program counter (S51), and registers the NOP instruction in the list (S53). The instruction analysis unit 74 extracts the NOP instruction from the list (S55), and performs the second stage processing of the NOP instruction (S57). Since the NOP instruction ends the processing in the second stage, the instruction analyzing unit 74 deletes the NOP instruction from the list (S61).

(9) Ninth Cycle (PC = 9) The instruction setting section 73 detects that an instruction is not stored at the address 9 indicated by the program counter (S52, N).
o), the process ends.

As described above, the instruction pipeline simulation apparatus according to the present embodiment simulates the processing in the instruction pipeline while analyzing the instructions, so that it is possible to detect data-dependent resource conflicts. It becomes possible.

[Twelfth Embodiment] FIG. 28 is a diagram showing a schematic configuration of an instruction pipeline simulation apparatus according to a twelfth embodiment of the present invention. Resource conflict check device 30 has the same configuration and function as resource conflict check device in Embodiment 1 shown in FIG. 3, and thus detailed description will not be repeated. The debug unit 62 and the simulation unit 72 are the same as those of the eleventh embodiment shown in FIG.
Has the same configuration and function as the debug section and the simulation section of the instruction pipeline simulation apparatus in the above, and therefore detailed description will not be repeated.

The instruction pipeline simulation apparatus according to the present embodiment is capable of detecting data-independent resource conflicts as described in the first embodiment, and is capable of detecting data conflicts described in the eleventh embodiment. It is possible to detect resource conflicts that depend on each other.

[Embodiment 13] Embodiment 1 of the present invention
The instruction pipeline simulation device in 3
This is the same as the configuration and function of the instruction pipeline simulation device according to the twelfth embodiment shown in FIG.
However, the resource conflict check device is different only in that it is replaced with the resource conflict check device 30 'in the second embodiment shown in FIG.

The instruction pipeline simulation apparatus according to the present embodiment has an effect that the operation of the instruction pipeline can be easily changed in addition to the effect described in the twelfth embodiment.

[0102]

According to the resource contention check device of the first to fourth aspects, whether or not resource contention occurs is determined based on the address of the instruction and the number of stages to be subjected to resource contention. Resource conflicts, which had been manually checked in the past, can be automatically performed, and the program development period can be shortened.

According to the assembling apparatus of the present invention, whether or not resource contention occurs is determined based on the instruction address and the number of stages for which resource contention occurs. Resource conflicts occurring in certain programs can be detected at an early stage.

According to the link device of the sixth aspect, it is determined whether or not resource contention occurs based on the address of the instruction and the number of stages that are the target of resource contention of the instruction. Resource conflicts occurring in object code can be detected early.

According to the instruction pipeline simulating apparatus of the present invention, whether or not resource contention occurs is determined on the basis of the address of the instruction and the number of stages subject to resource contention of the instruction. This makes it possible to appropriately determine whether or not resource contention occurs at the time of debugging of a program, and it is possible to detect resource contention at an early stage of program development.

According to the instruction pipeline simulating apparatus of the eighth aspect, the operation of the program in the instruction pipeline is advanced one stage at a time to determine whether or not resource contention occurs. It is possible to detect whether or not resource contention occurs.

According to the resource contention checking method of the ninth aspect, it is determined whether or not resource contention occurs based on the address of the instruction and the number of stages to be subjected to the resource contention of the instruction. Resource conflicts, which had been manually checked, can now be performed automatically, shortening the program development period.

According to the medium in which the resource contention check program according to claim 10 is recorded, whether or not resource contention occurs is determined based on the address of the instruction and the number of stages to be subjected to the resource contention of the instruction. As a result, resource conflicts, which had been manually checked in the past, can now be performed automatically, and the program development period can be shortened.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an appearance of a resource contention checking device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a resource contention checking device according to the present invention.

FIG. 3 is a block diagram illustrating a configuration of a resource conflict check device according to Embodiment 1 of the present invention.

FIG. 4 is a flowchart showing a processing procedure of the resource conflict check device according to the first embodiment.

FIG. 5 is a flowchart illustrating details of step S1 in FIG. 4;

FIG. 6 is a diagram for explaining an instruction information storage table.

FIG. 7 is a flowchart illustrating details of step S2 in FIG. 4;

FIG. 8 is a flowchart illustrating details of step S3 in FIG. 4;

FIG. 9 is a flowchart illustrating details of step S4 in FIG. 4;

FIG. 10 is a diagram illustrating an example of a microcode.

FIG. 11 is a diagram illustrating an example of a resource conflict check correspondence table.

FIG. 12 is a diagram illustrating an example of an instruction information storage table.

FIG. 13 is a diagram showing an example of the contents of a start point information storage table.

FIG. 14 is a diagram illustrating a stack.

FIG. 15 is a diagram showing an example of the contents of a checkpoint setting table.

FIG. 16 is a block diagram illustrating a schematic configuration of a resource conflict check device according to a second embodiment of the present invention.

FIG. 17 is a flowchart illustrating details of step S1 in FIG. 4;

FIG. 18 is a diagram illustrating an example of resource conflict check information.

FIG. 19 is a diagram illustrating an example of start point information.

FIG. 20 is a diagram illustrating an example of a check point.

FIG. 21 is a view showing a third embodiment and a fourth embodiment of the present invention;
FIG. 2 is a block diagram illustrating a schematic configuration of an assembling apparatus in FIG.

FIG. 22. Fifth and sixth embodiments of the present invention
2 is a block diagram showing a schematic configuration of a link device in FIG.

FIG. 23 is a diagram illustrating an example of a microcode.

FIG. 24 is a diagram illustrating an example of a microcode object code.

FIG. 25 is a view showing a seventh embodiment and an eighth embodiment of the present invention;
1 is a block diagram illustrating a schematic configuration of an assembling apparatus and a link apparatus in FIG.

FIG. 26 is a block diagram showing a schematic configuration of an instruction pipeline simulation device according to a ninth embodiment of the present invention.

FIG. 27 is a block diagram showing a schematic configuration of an instruction pipeline simulation device according to an eleventh embodiment of the present invention.

FIG. 28 is a block diagram showing a schematic configuration of an instruction pipeline simulation device according to the twelfth and thirteenth embodiments of the present invention.

FIG. 29 is a flowchart showing a processing procedure of the instruction pipeline simulation device according to the eleventh embodiment of the present invention.

FIG. 30 is a diagram showing the state of each stage in the instruction pipeline.

[Explanation of symbols]

1 Computer main body, 2 Graphic display device, 3 Magnetic tape device, 4 Magnetic tape, 5 Keyboard, 6 Mouse, 7 CD-ROM device, 8 CD
-ROM, 9 communication modem, 10 CPU, 11 RO
M, 12 RAM, 13 hard disk drive, 30,
30 'resource conflict check device, 31 input unit, 3
2 Resource conflict check section, 33 output section, 34 storage section, 35 microcode input section, 36 start point information setting section, 37 trace section, 38 check section, 39 instruction information storage table, 40 resource conflict check correspondence table, 41 start point information Storage table, 42 checkpoint setting table, 43 resource conflict information input unit, 51, 55 assembling device, 52 assembly processing unit, 53, 56 link device, 54 link processing unit,
61, 71, 81 instruction pipeline simulation device, 62 debug unit, 63, 72 simulation unit, 73 instruction setting unit, 74 instruction analysis unit.

Claims (10)

[Claims] An instruction extraction unit for extracting an instruction to be subjected to resource contention based on a type of the instruction; and an instruction extraction unit to extract the number of stages to be subjected to resource contention of the instruction extracted by the instruction extraction unit. Stage number extracting means, and conflict determining means for determining whether resource conflict occurs based on the address of the instruction extracted by the instruction extracting means and the number of stages extracted by the stage number extracting means. And a resource conflict checking device. 2. The contention determination means starts tracing from an address of an instruction extracted by the instruction extraction means, and traces the number of stages extracted by the number of stages extraction means to extract a checkpoint of resource contention. 2. The resource conflict check device according to claim 1, further comprising: a trace unit for performing a check, and a check unit for extracting a point at which a resource conflict occurs based on the check point extracted by the trace unit. 3. The resource conflict checking device further includes an instruction registering unit for registering information of a target instruction of the resource conflict, wherein the instruction extracting unit extracts the target instruction of the resource conflict based on a type of the instruction. Extracting from the information registered in the instruction registering means, the stage number extracting means determines the number of target stages of resource conflict of the instruction extracted by the instruction extracting means from the information registered in the instruction registering means. The resource conflict check device according to claim 1, wherein the resource conflict check device extracts the resource conflict. 4. The resource contention checking device according to claim 1, wherein said instruction extraction means extracts an instruction to be subjected to resource contention based on a type of an instruction constituting the microcode. 5. An assembly processing means for converting a program described in an assembly language into a machine language, and a resource conflict based on an instruction type of a program written in an assembly language converted by the assembly processing means. An instruction extraction unit for extracting a target instruction; a stage number extraction unit for extracting a target number of stages for resource contention of the instruction extracted by the instruction extraction unit; An assembling apparatus comprising: a contention determination unit configured to determine whether resource contention occurs based on the address of the instruction and the number of stages extracted by the stage number extraction unit. 6. A link processing means for converting a program converted into a machine language into an object code, and a resource contention target based on a type of an instruction of the program converted into the object code by the link processing means. Instruction extraction means for extracting instructions; stage number extraction means for extracting the number of stages to be subjected to resource contention of the instructions extracted by the instruction extraction means; A link device comprising: conflict determination means for determining whether resource contention occurs based on an address and the number of stages extracted by the stage number extraction means. 7. Debugging means for updating an instruction in a program, instruction extracting means for extracting an instruction to be subjected to resource contention based on an instruction type of the program updated by the debugging means, A stage number extracting unit for extracting the number of stages to be subjected to resource contention of the instruction extracted by the instruction extracting unit; an address of the instruction extracted by the instruction extracting unit and the number of stages extracted by the stage number extracting unit An instruction including: conflict determination means for determining whether or not resource contention occurs based on the number of stages; and simulation means for simulating an operation in an instruction pipeline of a program updated by the debug means. Pipeline simulation device. 8. A debugging means for updating an instruction in a program, a stage processing means for advancing an operation in an instruction pipeline of the program updated by the debugging means one stage at a time, An instruction pipeline simulation apparatus comprising: a contention determination unit configured to determine whether resource contention occurs in the one-stage operation performed. 9. A step of extracting an instruction to be subjected to resource contention based on the type of the instruction; a step of extracting the number of stages to be subjected to resource contention of the extracted instruction; Determining whether or not a resource conflict occurs based on the address and the extracted number of stages. 10. A step of extracting an instruction to be subjected to resource contention based on a type of the instruction; a step of extracting the number of stages to be subjected to resource contention of the extracted instruction; Determining whether or not a resource conflict occurs based on the address and the extracted number of stages.