JP4503203B2 - Method and apparatus for creating test program for evaluating information processing apparatus, and program describing processing for the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method and apparatus for creating a test program for evaluating an information processing apparatus, and more particularly, to a method and apparatus for creating a benchmark program.
[0002]
[Prior art]
Various information processing apparatuses (mainly computers) are usually subjected to various performance evaluations before shipping. For example, at the time of hardware development, the logic of the CPU to be mounted on the information processing apparatus is verified using a logic simulator or the like. In addition, when the apparatus is completed, the performance of the entire apparatus is evaluated by measuring the processing time when the apparatus executes a standard program. The latter evaluation is often called “benchmark test”, and the program used in the benchmark test is called “benchmark program”.
[0003]
[Problems to be solved by the invention]
However, since the logic simulator is mainly intended for logic verification, the function for evaluating the performance of the information processing apparatus is not sufficient. For example, since an OS (Operating System) cannot normally be installed in a logic simulator, the operation when an application is executed on the OS cannot be evaluated using the logic simulator. Further, since the logic simulator cannot normally connect an external device such as an external memory, it cannot evaluate an operation including an I / O instruction.
[0004]
On the other hand, in the benchmark test, a predetermined program (benchmark program) is executed using the completed information processing apparatus, so that the execution speed and the like can be measured. However, the processing executed in the existing benchmark test is generally relatively simple, and it is difficult to evaluate the performance when an application program to be actually used is executed. Therefore, if the performance when an application program to be actually used is accurately evaluated, it is necessary to actually execute the application program. However, in this case, it is usually necessary to perform a test with an external device connected to the information processing apparatus to be evaluated. For example, when evaluating an operation when a database application program is executed, it is necessary to perform a test in a state where an external storage device is connected to the information processing apparatus. For this reason, considerable time and cost are required to perform the test.
[0005]
In addition, since the benchmark test is performed after the information processing apparatus to be evaluated is completed, if it is found that a certain level of performance cannot be obtained at that time, the effort required for the design change becomes very large. That is, the product development time becomes longer.
[0006]
Thus, conventionally, it was impossible to accurately evaluate the performance of the information processing apparatus before completion.
An object of the present invention is to enable accurate evaluation of the performance of an information processing apparatus before it is completed.
[0007]
[Means for Solving the Problems]
The method of the present invention is a method for creating a test program for evaluating an information processing apparatus, and includes instructions executed by the processor when an original program is executed using a computer having a processor and a memory. Detects the contents of access to the memory, stores the detected information in time series as execution history information, and creates a load module format program that reproduces the instruction execution sequence executed by the computer based on the execution history information To do.
[0008]
The load module format program includes not only instructions when the original program is executed but also memory access contents. Therefore, when this load module is given to the information processing apparatus to be evaluated, the apparatus can faithfully reproduce the operation of the computer. Further, assuming that an OS is installed in the computer, the load module includes instructions for the OS. Therefore, even if the OS is not installed in the information processing apparatus to be evaluated, the operation of the computer can be reproduced.
[0009]
According to another aspect of the present invention, there is provided a test program creation method comprising: an instruction code corresponding to an instruction executed by the processor when an original program is executed using a computer having a processor and a memory; and an instruction related to the instruction Information, binary data written to or read from the memory, and access information representing access contents to the memory are detected, and the detected information is stored as execution history information in time series, and the execution history information Is written in a time series and the instruction code is written in a memory space prepared in advance based on the instruction information and the binary data is written on the basis of the access information to create a load module format program.
[0010]
Also in this method, basically, the operation of the computer is faithfully reproduced in the information processing apparatus to be evaluated, as in the above-described method.
In the above method, when the first instruction, which is an instruction that cannot be executed by the device to which the test program is provided, is executed by the computer, a processing routine that substitutes for the operation of the computer caused by the first instruction A program may be created and written to the memory space, and an instruction for calling the processing routine program may be written to the memory space instead of the first instruction. In this case, since an instruction that cannot be executed by the information processing apparatus to be evaluated is replaced with a processing routine program that can be executed by the information processing apparatus to be evaluated, the operation of the computer is faithfully reproduced in the information processing apparatus to be evaluated.
[0011]
In the above method, the computer executes a second instruction that is an instruction that may cause different operations when executed by the computer and when executed by a device to which the test program is given. In this case, the condition referred to by the processor when the second instruction is executed in the computer is written to the memory space, and an instruction for calling the condition is written to the memory space instead of the second instruction. It may be. In this case, even if the execution speed or the operating environment of the computer and the information processing apparatus to be evaluated are different from each other, consistency is achieved between them, so that the operation of the computer is faithfully performed in the information processing apparatus to be evaluated. It is reproduced.
[0012]
Further, in the above method, when the first operation, which is an operation that cannot be performed by the apparatus to which the test program is applied, is performed by the computer, the computer executes the first operation in the vicinity of the timing at which the first operation is performed. The third instruction, which is the changed instruction, is replaced with an instruction for switching the instruction sequence and written to the memory space, a processing routine program for substituting the first operation is created and written to the memory space, and the instruction sequence is switched. You may make it link a command and the said processing routine program. In this case, since the operation that cannot be executed by the information processing apparatus to be evaluated is replaced with a processing routine program that can be executed by the information processing apparatus, the operation of the computer is faithfully reproduced in the information processing apparatus to be evaluated.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating an overview of a program creation method according to the present embodiment. In this embodiment, a test program for evaluating the information processing apparatus is created. Specifically, a test program for evaluating the performance of a computer (mainly computer hardware) is created. Hereinafter, this program is referred to as a “benchmark program”.
[0014]
The original program execution machine 1 is realized by a computer in which a predetermined operating system (OS) is installed, and executes a given application program. Then, each time each instruction is executed or each time the memory is accessed, execution history information 2 is created by accumulating information representing the operation in time series. Note that a program (including an OS) executed by the original program execution machine 1 may be referred to as an “original program”.
[0015]
The analysis tool 3 analyzes the execution history information 2 and generates basic data 4 and correction data 5. Here, the basic data 4 is data that reproduces an instruction execution sequence executed by the original program execution machine 1. The correction data 5 is data for correcting the basic data 4. The correction data 5 is processed into an appropriate state by the correction tool 6.
[0016]
The benchmark program 7 includes basic data 4 and correction data 5 processed by the correction tool 6. The benchmark program 7 is a load module that represents an operation in the original program execution machine 1.
[0017]
The simulator 8 is an alternative device of the information processing device to be evaluated, and is given a benchmark program 7 and operates according to it. The simulator 8 may be an information processing apparatus before completion, a logic simulator, or the like. The simulator 8 does not necessarily have an OS installed. Furthermore, it is assumed that no external device is connected to the simulator 8.
[0018]
The benchmark program 7 is a load module and is given to the simulator 8. Here, the load module includes not only the instruction sequence of the application program executed by the original program execution machine 1 but also the instruction sequence of the OS installed in the original program execution machine 1. Therefore, even when the OS is not installed in the simulator 8, when the benchmark program 7 is given, the instruction sequence executed by the original program execution machine 1 is reproduced in the simulator 8. When an operation related to an external device occurs in the original program execution machine 1, the operation is expressed in a format that can be processed by the simulator 8 using the correction data 5. Therefore, the operation related to the external device can be evaluated using the simulator 8 to which no external device is connected.
[0019]
FIG. 2 is a configuration diagram of the original program execution machine 1. The original program execution machine 1 includes at least a CPU (Central Processing Unit) 11 and a memory 12.
[0020]
The CPU 11 executes a program stored in the memory 12 to receive data, perform an operation using the data, and provide a series of operations until outputting the operation result. Note that the CPU 11 includes a plurality of registers.
[0021]
The memory 12 is a storage area accessed by the CPU 11, and stores the OS program 13, the application program 14, and various data. Here, the OS program 13 is not particularly limited, but an OS program that is the same as or compatible with the OS to be installed in the information processing apparatus to be evaluated is used. The application program 14 is preferably executed by the information processing apparatus to be evaluated.
[0022]
The tracer 15 detects the operation of the CPU 11 and access to the memory 12 and outputs the detection results in time series. In the example shown in FIG. 2, the tracer 15 is stored in the memory 12, but may be provided in another storage area.
[0023]
The external device 21 is a device connected to the original program execution machine 1, and is an input device such as an external storage device or a keyboard.
FIG. 3 is a flowchart showing the operation of the tracer 15. This process is activated every time the CPU 11 executes some process or every time the memory 12 is accessed.
[0024]
In step S1, it is checked whether or not an instruction is executed by the CPU 11. Here, the “instruction” includes not only an instruction of the application program 14 but also an instruction associated with the OS processing. If the instruction is executed by the CPU 11, a corresponding instruction record is created in step S2. Here, the instruction record includes, for example, the following information.
・ Instruction code
-Instruction storage address (real address, logical address)
-Write destination register information
-Write destination address (real address, logical address)
・ Write data length
Reference register information
・ Reference address (real address, logical address)
・ Reference data length
The “instruction code” is an instruction itself given to the CPU 11 and is expressed in machine language. This instruction code is obtained, for example, by extracting a data string written in an instruction register provided in the CPU 11. “Instruction storage address” is an address where the instruction is stored. “Write destination register information” identifies a register to which data is to be written by the instruction. The “write destination address” and “write data length” are an address at which the data is written and the data length of the data when the data is written to the memory 12 by the instruction. “Reference register information” identifies a register whose data should be referred to by the instruction. “Reference address” and “reference data length” are the address at which the data is stored and the data length of the data, respectively, when the data in the memory 12 is referred to by the instruction. The method of detecting “instruction storage address” to “reference data length” can be realized by existing technology.
[0025]
In step S3, it is checked whether or not the register included in the CPU 11 has been updated. If one or more registers are updated, a corresponding register record is created in step S4. Here, the register record includes, for example, information for identifying the updated register and data (register value) newly written in the register.
[0026]
In step S5, it is checked whether or not an interrupt to the CPU 11 has occurred. If an interrupt to the CPU 11 occurs, a corresponding interrupt record is created in step S6. Here, in this embodiment, the interrupt is assumed to be an I / O interrupt, a program interrupt, an external interrupt, a privilege (SVC) interrupt, or the like. An example of an interrupt record corresponding to each interrupt is shown below.
I / O interrupt
・ PSW value before interrupt occurrence
・ Interrupt code
Program interruption
・ PSW value before interrupt occurrence
・ Instruction length
・ Interrupt code
-Code to determine exception type
・ Phenomenon identification code
External interrupt
・ PSW value before interrupt occurrence
・ Instruction length
・ Phenomenon identification code
Privileged (SVC) interrupt
・ PSW value before interrupt occurrence
-PSW value after an interrupt occurs
・ Instruction length
・ Phenomenon identification code
In step S7, it is checked whether or not the memory 12 has been accessed. Here, the access includes an operation of writing data in the memory 12 and an operation of referring to data stored in the memory 12. When the memory 12 is accessed, a corresponding memory data record is created in step S8. Here, the memory data record is composed of the following information, for example.
・ Real address
・ Memory data
·Data length
・ Access type
The “real address” represents the accessed real address. “Memory data” is data written to the memory 12 or data read from the memory 12. “Data length” indicates the data length of data written to the memory 12 or data read from the memory 12. “Access type” identifies writing or reference.
[0027]
In step S9, it is checked whether or not an instruction for updating various tables managed by the OS has been executed. Here, it is assumed that it is checked whether or not an instruction for updating the address conversion table has been executed. In the address conversion table, information for converting a logical address recognized by the CPU 11 into a real address on the memory 12 is registered. If an instruction to update the address conversion table is executed, a corresponding table reference record is created in step S10. Here, the table reference record includes, for example, the following information.
・ Supported operation
・ Translation address
・ Table address
·Data length
“Corresponding operation” represents an operation that requested address translation, and identifies instruction fetch, data reference, and data write. The “translation address” is a set of logical address and real address related to the conversion process. The “table address” is an address where the referenced address conversion table is stored. “Data length” is the data length of the data converted by the referenced address conversion table.
[0028]
In step S11, it is checked whether key information has been set. The key information is information for managing each page constituting the storage area, and is used by the OS. If key information is set, a corresponding key information record is created in step S12. Here, the key information record includes, for example, the following information. The key information may be derived from a memory record, an instruction record, and a register value.
・ Access side key information
・ Instruction code
Access type (instruction fetch, operand read, operand write, operand number)
・ Memory access logical address
・ Real memory access address
・ Segment table start address
-Segment table entry number
·Data length
In this way, when the original program is executed by the CPU 11, the tracer 15 detects instructions, memory data, related information, and the like, and creates corresponding records. The records created one after another by the tracer 15 are stored in time series as the execution history information 2.
[0029]
When the CPU 11 executes an instruction, the tracer 15 creates an instruction record corresponding to the instruction. For example, when a memory access occurs due to the instruction, the memory data record corresponding to the memory access is generated. Create at the same time. That is, when one instruction is executed by the CPU 11, the tracer 15 creates one or a plurality of records corresponding to the instruction.
[0030]
In the above example, a corresponding memory data record is created when the memory 12 is accessed. However, when certain data stored in the memory 12 is referenced (read), the analysis tool 3 The memory data record may be created only when the data is first referred to.
[0031]
Furthermore, when the memory 12 is updated according to a certain instruction, if the updated contents can be easily estimated, the analysis tool 3 may create another record instead of the memory data record. For example, in the case of a simple load instruction that only loads memory data stored in the memory 12 into a register, only a register record may be created instead of creating a memory data record. In this case, the operand address of the load instruction (reference address of the memory 12) is registered in this register record. At this time, the value stored in the load destination register after execution of the load instruction is registered in the register record, but this value matches the memory data stored in the operand address of the load instruction. The update content may be derived from the instruction record.
[0032]
FIG. 4 is an example of the execution history information 2. The execution history information 2 is managed using a record number when stored in a file or the like. That is, each record created by the tracer 15 is stored with a record number assigned in the order of creation. Each record is given a record type. In this embodiment, “01”, “02”, and “03” are assigned to “instruction record”, “register record”, and “memory data record”, respectively. The information detected by the tracer 15 is stored as execution information as it is. In this embodiment, for example, an instruction record is stored in a record identified by “record number = 453”. Specifically, “01” is set as the record type of this record, and further, an instruction code, various addresses, a data length, and the like detected by the tracer 15 are stored as execution information.
[0033]
In the above-described embodiment, information necessary for creating the execution history information 2 is collected by moving the tracer 15 on the actual machine, but may be collected by other methods. For example, necessary information may be collected using an architecture simulator. Further, the information necessary for creating the execution history information 2 varies depending on the device to be evaluated. That is, the information to be collected is determined depending on the OS installed in the evaluation target device, the instruction architecture of the CPU mounted in the evaluation target device, the system configuration of the evaluation target device, and the like.
[0034]
The execution history information 2 created as described above is analyzed by the analysis tool 3. Hereinafter, the operation of the analysis tool 3 will be described.
The analysis tool 3 analyzes each record of the execution history information 2 one by one in order, and writes the result in the initial memory space 30 shown in FIG. The initial memory space 30 includes a basic memory space 31 and a correction memory space 32. Here, the basic memory space 31 is a storage area having the same size as the real space of the memory 12 provided in the original program execution machine 1. The basic data 4 and the correction data 5 shown in FIG. 1 are written in the basic memory space 31 and the correction memory space 32, respectively.
[0035]
The analysis tool 3 also includes a register group 33 for reflecting information registered in the register record. The register group 33 includes the same number of registers as the CPU 11 of the original program execution machine 1 and is used when data is written to the initial memory space 30.
[0036]
The analysis tool 3 sequentially writes the results obtained by analyzing each record of the execution history information 2 in the basic memory space 31. For example, when extracting the instruction record, the analysis tool 3 uses the “instruction code” registered in the record as a key and the “instruction storage address (real address)” registered in the record as a key. Write to the corresponding area in space 31. At this time, if there is data accompanying the “instruction code”, the information is written in an area following the “instruction code”. As a result, the instruction code of the instruction executed by the original program execution machine 1 is written into the basic memory space 31. At this time, the instruction code exists at the same address in the memory 12 and the basic memory space 31.
[0037]
For example, in the example shown in FIG. 6, the store instruction stored in the address “aaaa” of the memory 12 provided in the original program execution machine 1 is executed, and an instruction record corresponding to the store instruction is created. Then, this instruction record is analyzed, and a store instruction is written in the address “aaaa” of the basic memory space 31 accordingly.
[0038]
When writing the instruction code to the basic memory space 31 as described above, if some data has already been stored in the corresponding area, the analysis tool 3 does not execute the writing process. Here, the function of prohibiting overwriting can be realized, for example, by providing a table for managing the basic memory space 31 in units of bytes and using the table to manage whether data is stored in each area. is there.
[0039]
Similarly, when the analysis tool 3 extracts a memory data record from the execution history information 2, the “memory data” registered in the record is used as a key with the “real address” registered in the record as a key. Write to the corresponding area in the memory space 31. As a result, the same memory data exists at the same address in the memory 12 and the basic memory space 31 of the original program execution machine 1.
[0040]
Other types of records will be described later with reference to flowcharts shown later.
As described above, the analysis tool 3 analyzes the execution history information 2 to reflect the contents of the memory 12 of the original program execution machine 1 in the basic memory space 31 of the initial memory space 30. In this case, the same result can be obtained by copying the contents of the memory 12 to the basic memory space 31 at an arbitrary time.
[0041]
By the way, the benchmark test of the present embodiment assumes that the performance of an evaluation target information processing apparatus is checked before the information processing apparatus is completed. Therefore, when testing a device to be evaluated, a simulator (simulator 8 shown in FIG. 1) having the same specifications as that of the device is prepared, and evaluation is performed by causing the simulator 8 to execute the benchmark program of this embodiment. The performance of the target device is estimated. Here, the simulator 8 includes a CPU included in the information processing apparatus to be evaluated or a processor equivalent thereto, but it is also assumed that the OS is not installed. Further, it is assumed that an external device is not connected to the simulator 8. For this reason, the simulator 8 cannot execute a part of instructions or processing executed by the original program execution machine 1.
[0042]
In the program creation method of this embodiment, among the instructions / processes executed by the original program execution machine 1, instructions / processes that cannot be executed by the simulator 8 are replaced with instructions / processes that can be executed by the simulator 8, thereby solving the above problem. Plan. Hereinafter, this replacement process may be referred to as “correction”. The correction data 5 shown in FIG. 1 is used for this correction process.
[0043]
In the following embodiment, asynchronous interrupts (including I / O interrupts), I / O instructions, and instructions that refer to dynamic information are taken as instructions or processes that require correction.
Asynchronous interrupt (part 1)
Here, it is assumed that in the original program execution machine 1, the memory 12 is updated by an I / O interrupt from the external device 21 (new data is written in the memory 12).
[0044]
Asynchronous interrupts occur independently of the execution of OS instructions or application program instructions. In other words, the memory 12 is updated by the I / O interrupt while the job is being executed. At this time, this memory update is recognized by the occurrence of an I / O interrupt when viewed from the job being executed.
[0045]
By the way, when the memory 12 is updated by an I / O interrupt, the tracer 15 creates a corresponding interrupt record and memory data record. For this reason, the analysis tool 3 should basically execute a process of updating the initial memory space 30 according to these records. However, in practice, if the contents of the memory data record are reflected in the initial memory space 30, the same result as the memory update executed in the original program execution machine 1 should be obtained.
[0046]
FIG. 7 is a diagram for explaining processing of the analysis tool 3 when a memory update due to an I / O interrupt occurs. In this embodiment, in the original program execution machine 1, data A is written to the address “bbbb” of the memory 12 by an I / O interrupt from the external device 21, and an interrupt record and a memory data record corresponding to the data A are created. In this case, data A is written to the address “bbbb” of the basic memory space 31 according to the contents of the memory data record.
[0047]
As described above, in the original program execution machine 1, the data A is written to the address “bbbb” of the memory 12 by the interruption from the external device 21. On the other hand, data A is written in advance at address “bbbb” of the basic memory space 31.
[0048]
Here, the data stored in the initial memory space 30 is finally used as a benchmark program. Specifically, instructions stored in the basic memory space 31 are sequentially executed by the simulator. At this time, assuming that the initial memory space 30 is created as shown in FIG. 7, the data A is already stored in the address “bbbb” of the basic memory space 31 at the start of the benchmark test. . This state is equivalent to the data A being written to the address “bbbb” regardless of the instruction stored in the basic memory space 31. That is, this state is substantially equivalent to data A being written at address “bbbb” by an I / O interrupt from the external device 21. Therefore, the memory update by the I / O interrupt is realized by reflecting the contents of the memory data record in the initial memory space 30. That is, even when the external device 21 cannot be connected to the simulator 8, the same result as that when the external device 21 is connected in the benchmark test can be obtained. There may be a case where data A1 different from data A exists at address "bbbb", and the data A1 is changed to data A by an I / O interrupt later. In this case, the update is reflected on the memory 31 when the I / O instruction is generated.
I / O instruction
Here, it is assumed that the I / O instruction is executed in the original program execution machine 1 and the memory 12 is updated accordingly. This I / O instruction is, for example, an instruction that reads data from the external device 21 and writes it to the memory 12.
[0049]
When an I / O instruction is executed in the original program execution machine 1, the tracer 15 creates an instruction record corresponding to the I / O instruction. Further, when the memory 12 is updated in accordance with this command, a memory data record including the updated memory data is created. Further, information updated by executing the I / O instruction (for example, register value, condition code, etc.) is registered in the corresponding record.
[0050]
The analysis tool 3 writes necessary information in the initial memory space 30 based on each record. Specifically, the memory data and various information updated by the I / O instruction are written in the correction memory space 32 as correction data. The analysis tool 3 generates an interrupt attribute instruction instead of the I / O instruction and writes it to the corresponding address in the basic memory space 31. Here, this interrupt attribute command is a command for processing the correction data previously stored in the correction memory space 32.
[0051]
FIG. 8 is a diagram for explaining processing of the analysis tool 3 when a memory update by an I / O instruction occurs. In this example, in the original program execution machine 1, the data B is written to the "dddd" address by executing the I / O instruction stored in the "cccc" address of the memory 12. At this time, the tracer 15 creates a corresponding record. The analysis tool 3 first writes the data B into a predetermined area in the correction memory space 32 using the memory data record. In FIG. 8, only the data B is written in the correction memory space 32, but actually other related information is also stored together. Subsequently, the analysis tool 3 creates a processing routine program (sub-p) corresponding to the I / O instruction and writes it in a predetermined area in the correction memory space 32. This processing routine program describes the following processing.
A process of writing the data B stored in the correction memory space 32 to the “dddd” address in the basic memory area 31
A process for updating the register or the like according to other related information stored in the correction memory space 32
Further, the analysis tool 3 writes an interrupt attribute command at the address “cccc” of the basic memory space 31. That is, an interrupt attribute instruction is written instead of the I / O instruction. Here, the interrupt attribute instruction is an instruction having an attribute for generating an interrupt, and a processing routine program stored in the correction memory space 32 can be called.
[0052]
When the benchmark program created as described above is given to the simulator 8, the following operations are realized. That is, the simulator 8 executes the instructions stored in the basic memory space 31 in order. Then, when the interrupt attribute instruction set in FIG. 8 is executed, the processing routine program stored in the correction memory space 32 is started. Then, by this processing routine program, the data B stored in the correction memory space 32 is written to the “dddd” address of the basic memory area 31 and the register and the like are updated. Thereafter, the processing returns to the instruction next to the interrupt attribute instruction.
[0053]
As described above, when the benchmark program is provided to the simulator 8, the same operation as that caused by the I / O instruction is realized in the original program execution machine 1. Here, in the benchmark program, the I / O instruction is replaced with an interrupt attribute instruction. Therefore, even when the simulator 8 cannot execute the I / O instruction, the operation corresponding to the I / O instruction is realized using the simulator 8.
Instructions that reference dynamic information
Here, it is assumed that an instruction referring to dynamic information is executed in the original program execution machine 1. The “dynamic information” is information relating to, for example, the time when an instruction is executed or the time required to execute a predetermined process. Further, the “instruction for referring to dynamic information” is an instruction for deriving different operations depending on the dynamic information. For example, it is a branch instruction in which “jump to address XX if executed within 10 seconds from program startup and jump to address YY if executed after that” is defined.
[0054]
An instruction for referring to the dynamic information as described above (hereinafter referred to as a dynamic information reference instruction) can basically be executed also by the simulator 8. However, the execution speed of the simulator 8 is not necessarily the same as that of the original program execution machine 1. For this reason, when the same program is given to the original program execution machine 1 and the simulator 8, the processing result by the dynamic information reference instruction is not always the same.
[0055]
In the program creation method of this embodiment, in order to solve this problem, when a dynamic information reference instruction is executed by the original program execution machine 1, the instruction is replaced with another instruction (for example, a load instruction). Then, correction processing is performed so that an equivalent operation is realized in the simulator 8.
[0056]
FIG. 9 is a diagram for explaining processing of the analysis tool 3 when a dynamic information reference instruction is executed. In FIG. 9, the dynamic information reference instruction is described as “D instruction”.
[0057]
In the original program execution machine 1, the dynamic information stored in the address "ffff" is referred to by executing the dynamic information reference instruction stored in the address "eeee" of the memory 12, and the dynamic information It is assumed that the subsequent processing is determined according to the value of. Here, the address “ffff” in the memory 12 is used as an area for writing the elapsed time from the start of the program, for example. This elapsed time is used as dynamic information. This dynamic information reference instruction loads, for example, the dynamic information stored in the address “ffff” of the memory 12 into a predetermined register and compares it with a predetermined threshold value. This is an instruction for determining subsequent processing.
[0058]
In this case, the tracer 15 creates corresponding instruction records and register records. At this time, at least the instruction code for identifying the dynamic information reference instruction, the storage address of the dynamic information reference instruction, and the storage address of the dynamic information are registered in this instruction record. Further, at least a register value is registered in the register record. Here, the register value is a comparison result between the dynamic information read from the address “ffff” of the memory 12 and the threshold value.
[0059]
The analysis tool 3 performs the following processing by analyzing the created record. That is, the analysis tool 3 first writes a load instruction at the address “eeee” in the basic memory space 31 based on the instruction record. This load instruction is an instruction for loading the data stored at the address “ffff” into a predetermined register. Further, the analysis tool 3 writes the register value registered in the register record in the address “ffff” of the basic memory space 31.
[0060]
When the benchmark program created as described above is given to the simulator 8, the following operations are realized. That is, when the load instruction is executed in the simulator 8, the data stored at the “ffff” address in the basic memory space 31 is loaded into a predetermined register. Here, the address “ffff” stores a comparison result when the dynamic information is compared with the threshold value in the original program execution machine 1. Therefore, when this load instruction is executed in the simulator 8, an operation equivalent to that when the dynamic information reference instruction is executed in the original program execution machine 1 is realized.
[0061]
As described above, when the benchmark program is given to the simulator 8, an operation equivalent to that when the dynamic information reference instruction is executed in the original program execution machine 1 is realized without referring to the dynamic information. That is, even if the execution speed or the operating environment of the original program execution machine 1 and the simulator 8 are different from each other, the operation of the original program execution machine 1 is reproduced on the simulator 8.
[0062]
In the example shown in FIG. 9, the same operation is realized in the original program execution machine 1 and the simulator 8 by replacing the dynamic information reference instruction with the load instruction. However, the present invention is not limited to this. Absent. That is, for example, when the processing by the dynamic information reference instruction is complicated, or when the instruction is executed a plurality of times and the register value is different every time it is executed, as in the processing for the I / O instruction described above, An interrupt attribute command may be used. That is, the dynamic information reference instruction is replaced with an interrupt attribute instruction, and a processing routine program called when an interrupt is generated by the interrupt attribute instruction is stored in the correction memory space 32. In this case, processing corresponding to the dynamic information reference instruction is described in the processing routine program.
Asynchronous interrupt (part 2)
Here, it is assumed that an I / O interrupt from the external device 21 occurs in the original program execution machine 1 and a process corresponding to the interrupt is executed.
[0063]
FIG. 10A is a diagram showing an instruction sequence when the above interrupt occurs in the original program execution machine 1. Here, instructions A to F. . . Assume that an interrupt is generated immediately after instruction C is executed in a sequence in which are executed sequentially. Then, the processing routine 41 including the instructions a to d is executed by the interruption, and then the processing returns to the instruction D.
[0064]
When creating the benchmark program of this embodiment, the instruction immediately before the asynchronous interrupt is replaced with an instruction for calling the processing routine 41 in order to reproduce the operation caused by the asynchronous interrupt in the simulator 8. . In the case of the above example, the instruction C is replaced with an interrupt attribute instruction for calling the processing routine 42 as shown in FIG. Here, the processing routine 42 includes data (emulation data) emulating the operation caused by the instruction C in addition to the instructions a to d constituting the processing routine 41. Further, the emulation data of the instruction C includes, for example, an operation result when the instruction C is executed, information related to register update, and the like.
[0065]
In the above example, the instruction immediately before the asynchronous interrupt is replaced with the interrupt attribute instruction. However, it is not always necessary to replace the previous instruction, and another instruction in the vicinity of the timing at which the asynchronous interrupt occurs. May be replaced with an interrupt attribute instruction. In this case, it is desirable that an instruction that can be easily emulated (for example, an ADD instruction) is replaced with an interrupt attribute instruction.
[0066]
FIG. 11 is a diagram illustrating the processing of the analysis tool 3 when an asynchronous interrupt occurs. FIG. 11 shows an embodiment corresponding to the example shown in FIG.
Assume that in the original program execution machine 1, an asynchronous interrupt is generated immediately after the instruction C stored in the address “gggg” of the memory 12 is executed, and the processing routine 41 is called by this interrupt. In this case, the tracer 15 corresponds to the instruction record corresponding to the instruction C, the record corresponding to the information updated due to the instruction C, the interrupt record corresponding to the asynchronous interrupt, and the instruction included in the processing routine 41. Create records to be used.
[0067]
The analysis tool 3 performs the following processing based on the created record. That is, the analysis tool 3 first creates emulation data of the instruction C by referring to a register record or the like, and creates a processing routine 42 that finally executes an instruction including the emulation data and passing the process to the instruction a. . Then, the processing routine 42 is written in a predetermined area of the correction memory space 32. Further, the analysis tool 3 writes an interrupt attribute command at the “gggg” address of the basic memory space 31. This interrupt attribute instruction is an instruction for calling the processing routine 42.
[0068]
When the benchmark program created as described above is given to the simulator 8, the following operations are realized. That is, when the interrupt attribute command is executed in the simulator 8, the processing routine 42 is called. Thereby, the operation corresponding to the instruction C is realized. Subsequently, control is passed to the processing routine 41. After the processing routine 41 is executed, the process returns to the instruction next to the instruction C.
[0069]
As described above, when the benchmark program is given to the simulator 8, an operation equivalent to the operation caused by the asynchronous interrupt is reproduced in the original program execution machine 1 without generating the asynchronous interrupt. In other words, even if the simulator 8 does not have a function of accepting asynchronous interrupts, an operation equivalent to that when an asynchronous interrupt occurs in the original program execution machine 1 is reproduced on the simulator 8.
[0070]
Although an interrupt instruction is used in the above embodiment, this interrupt instruction is an example of an instruction for switching an instruction sequence. That is, in FIG. 11, the instruction C may be replaced with an instruction for switching the instruction sequence. In this case, the instruction for switching the instruction sequence and the processing routine 42 are linked.
[0071]
FIG. 12 is a flowchart for explaining the operation of the analysis tool 3. As described above, the analysis tool 3 generates the basic data 4 and the correction data 5 that are the basis of the benchmark program 7 by sequentially analyzing the records of the execution history information 2. The basic data 4 and the correction data 5 are written in the initial memory space 30.
[0072]
Step S21 is a process of extracting each record of the execution history information 2 one by one from the top. In steps S22 to S27, the attribute of the extracted record is examined. Here, the attribute of the record is identified by the record type shown in FIG.
[0073]
If the record extracted from the execution history information 2 is an instruction record, the process proceeds to step S31. In step S31, it is checked whether an interrupt instruction is registered in the record. If an interrupt instruction has been registered, information related to the interrupt instruction is registered in the management list in step S32. As shown in FIG. 13A, the management list registers information related to each interrupt instruction in the order of appearance. When a new interrupt instruction is registered in this management list, a serial number is assigned to the interrupt instruction. At this time, the address information corresponding to the interrupt instruction is added to the interrupt management table shown in FIG. The interrupt management table manages the correspondence between the serial number assigned to each interrupt instruction and the address storing the processing routine program describing the process executed due to the interrupt instruction.
[0074]
If no interrupt instruction is registered in the extracted record, the process proceeds to step S33. In step S33, it is checked whether or not “an instruction that can be replaced with another instruction (candidate point that generates an interrupt)” is registered in the extracted record. The “instruction that can be replaced with another instruction” corresponds to, for example, the dynamic information reference instruction shown in FIG. 9 in the previous embodiment. If such an instruction is registered in the record, the correspondence relationship between the instruction before replacement and the instruction after replacement is registered in step S34. Specifically, an instruction ID corresponding to a variable for recording a replacement candidate is registered.
[0075]
If no “instruction that can be replaced with another instruction” is registered in the extracted record, the process proceeds to step S35. In step S35, it is checked whether or not an inexecutable instruction is registered in the extracted record. The non-executable instruction is an instruction that the simulator 8 cannot execute, and corresponds to, for example, the I / O instruction shown in FIG. 8 in the previous embodiment. If an inexecutable instruction is registered in the record, an emulation process (a process routine program for the emulation process) is created in step S36.
[0076]
As shown in FIG. 8, when an inexecutable instruction is replaced with an interrupt instruction, the interrupt instruction is also registered in the management list shown in FIG. The correspondence relationship between the serial number of the interrupt instruction and the address storing the processing routine program describing the process executed due to the interrupt instruction is shown in the interrupt management table shown in FIG. Is set.
[0077]
When a general command is stored in the extracted record (when “No” is determined in steps S31, 33, and 35), the initial memory space 30 is updated in step S37. This process corresponds to, for example, the procedure shown in FIG. Step S37 is also executed when an emulation process is created in step S36. This process corresponds to, for example, a procedure for writing an interrupt attribute instruction and data B in the initial memory space 30 in FIG.
[0078]
If the record extracted from the execution history information 2 is a register record, the process proceeds to step S41. In step S41, the register (register group 33 shown in FIG. 5) is updated according to the contents of the extracted register record.
[0079]
If the record extracted from the execution history information 2 is an interrupt record, the process proceeds to step S42. In step S42, an interrupt instruction is generated as necessary, and is registered in the management list shown in FIG. For example, in the example shown in FIGS. 10 to 11, since the instruction C is replaced with an interrupt attribute instruction, the interrupt attribute instruction is registered in the management list. In this case, the corresponding information is set in the interrupt management table shown in FIG.
[0080]
If the record extracted from the execution history information 2 is a memory data record, the corresponding data is written in the initial memory space 30 in step S37.
[0081]
If the record extracted from the execution history information 2 is a table reference record, the updated table contents are written in the memory space 30 in step S37. Here, an address conversion table for converting a logical address into a real address is assumed. The address conversion table will be separately described later.
[0082]
If the record extracted from the execution history information 2 is a key information record, the corresponding key information is registered in step S43. The key information is written in the correction memory space 32.
[0083]
When the processing of steps S21 to S43 is executed for all the records constituting the execution history information 2, information necessary to call the corresponding processing routine from each interrupt instruction is set in step S51. At this time, the interrupt management table shown in FIG. 13B is referred to, and for the interrupt instruction generated by the replacement process, information (including the instruction) for calling the corresponding processing routine from the correction memory space 32 is included. ) Is set.
[0084]
As described above, the benchmark program of the present embodiment is stored in the initial memory space 30 including the basic memory space 31 and the correction memory space 32. The instruction executed by the original program execution machine 1 is written in the basic memory space 31. At this time, each instruction is written at the same address as that stored in the memory 12 of the original program execution machine 1. Further, when a memory update or memory reference occurs in the original program execution machine 1, the corresponding memory data is written in the basic memory space 31. At this time, the memory data is written at the same address as that stored in the memory 12 of the original program execution machine 1.
[0085]
For operations that cannot be performed in the simulator 8, equivalent operations are provided using the correction memory space 32. For example, when an I / O instruction is executed in the original program execution machine 1, an interrupt instruction is written in the basic memory space 31 instead of the I / O instruction, and an operation caused by the I / O instruction is performed. Information (correction data) for realization is written in the correction memory space 32. Then, necessary information is set so that the correction data stored in the correction memory space 32 is called from the interrupt instruction. When an asynchronous interrupt occurs in the original program execution machine 1, a predetermined instruction to be executed in the vicinity of the timing at which the interrupt occurs is replaced with an interrupt instruction. Then, necessary information is set so that the correction data stored in the correction memory space 32 is called in the same manner.
[0086]
Therefore, when the benchmark program is given to the simulator 8, the same instruction sequence as when the application program is executed in the original program execution machine 1 is executed. At this time, among the processes executed in the original program execution machine 1, processes that cannot be executed by the simulator 8 are rewritten into a format that can be executed by the simulator 8. Therefore, even if the simulator 8 does not have a function equivalent to that of the original program execution machine 1, it can faithfully reproduce the operation realized in the original program execution machine 1. As a result, highly reliable evaluation can be performed using the simulator 8.
[0087]
Next, the address conversion table will be described. The address conversion table is a table that is referred to when a logical address recognized by the CPU is converted into a real address, and is stored in a predetermined area in the memory 12 in the original program execution machine 1. However, the correspondence between the logical address and the real address usually changes from moment to moment as the instruction sequence is executed. Therefore, the benchmark program must also describe the change in the correspondence between the logical address and the real address.
[0088]
For this reason, during the period in which the application program is being executed in the original program execution machine 1, the tracer 15 sequentially creates a table reference record including a set of pre-conversion addresses and post-conversion addresses each time the address conversion table is referenced. To go. Then, the analysis tool 3 generates an address translation table actually referred to in the original program execution machine 1 in the initial memory space 30 based on the created table reference record. Here, only a part of the address conversion table provided in the original program execution machine 1 is actually referred to when the instruction is executed. That is, valid information is stored only in a part of the address conversion table reproduced in the initial memory space 30. Therefore, the address conversion table reproduced in the initial memory space 30 can be compressed. Hereinafter, compression of the address conversion table will be described with reference to FIG.
[0089]
Here, as shown in FIGS. 14 (a) and 14 (b), the table A converts a predetermined area in the logical address space to the address 1000 to 2000 in the real address space, and the table B is the other in the logical address space. Are converted into addresses 3000 to 4000 in the real address space. In addition, as shown in FIG. 14B, only the areas indicated by hatching in Table A and Table B are actually referred to in the original program execution machine 1. In this case, when the table A and the table B are reproduced in the initial memory space 30, effective conversion information is stored only in the area indicated by the oblique lines. Further, as shown in FIG. 14B, when it is assumed that the real address spaces managed by the table A and the table B are the same, the real addresses in which effective translation information is stored in the two tables are It shall not be duplicated.
[0090]
In this case, as shown in FIG. 14B, the table A and the table B can be merged (integrated) with each other in the initial memory space 30. As a result, the real address spaces managed by the two tables can also be merged with each other. For example, data stored at addresses 1000 to 2000 and 3000 to 4000 before table A and table B are merged are stored only at addresses 1000 to 2000 as shown in FIG. Thereby, the initial memory space 30 can be reduced.
[0091]
FIG. 15 is a configuration diagram of a system for creating and verifying the benchmark program 7. Here, the original program execution machine 1, the execution history information 2, the analysis tool 3, the basic data 4, the correction data 5, and the benchmark program 7 correspond to units having the same reference numerals in FIG.
[0092]
In FIG. 15, the monitor source 51 stores a program for processing the correction data 5. These programs are written in a high-level language, for example. One of the programs stored in the monitor source 51 is shown in FIG.
[0093]
FIG. 16 is a flowchart showing a procedure for determining a process corresponding to each interrupt instruction when the benchmark program is executed in the simulator 8.
In step S61, first, pre-interrupt processing is executed. In this processing, for example, register backup is performed. Subsequently, in step S62, it is checked whether or not correction is necessary for the generated interrupt. If correction is necessary, in step S63, the interrupt management table shown in FIG. 13B is searched using the control variable as a search key. Then, the corresponding address is extracted from the entry having the serial number that matches the control variable, and the processing routine program stored at the address is executed. In step S64, “1” is added to the control variable. In step S65, post-interrupt processing is executed. As a result, the process returns to the interrupt source or the instruction to pass control.
[0094]
The object generation unit 52 includes a compiler that compiles the correction data 5 and the monitor source 51, and a linker. The output of the object generation unit 52 is a data string to be stored in the correction memory space 32 of the initial memory space 30. The address resolution unit 53 resolves addresses so as to ensure continuity between the data stored in the basic memory space 31 and the data to be stored in the correction memory space 32. Then, the benchmark program 7 is obtained by integrating the basic data 4 generated by the analysis tool 3 and the data resolved by the address resolution unit 53.
[0095]
The monitor source 51, the object generation unit 52, and the address resolution unit 53 correspond to the correction tool 6 illustrated in FIG.
The created benchmark program 7 is verified by the architecture simulator 61. At this time, the dynamic analysis tool 62 checks the malfunction of the tracer 15 or the analysis tool 3 based on the execution history information 2 and the simulation result by the architecture simulator 61. The check result is fed back to the tracer 15 and the analysis tool 3 as necessary.
[0096]
By the way, the above-described embodiment is based on the premise that the execution history information 2 includes all information related to the operation of the original program execution machine 1. That is, in the above-described embodiment, the tracer 15 operates continuously in parallel with the execution of the application program.
[0097]
However, depending on the application, the load on the tracer 15 may become heavy. In this case, if the tracer 15 is continuously operated, the execution of the application program may be adversely affected. For this reason, the original program execution machine 1 can operate the tracer 15 intermittently.
[0098]
FIG. 17 is a diagram for explaining processing when the tracer 15 is operated intermittently. Here, it is assumed that a cycle composed of a period in which the tracer 15 is operating and a period in which the tracer 15 is stopped is repeated.
[0099]
The tracer 15 outputs execution history information during the operation period, but does not output it when stopped. For this reason, in order to create a benchmark program for faithfully reproducing the operation of the original program execution machine 1, the analysis tool 3 estimates the operation of the original program execution machine 1 during the period in which the tracer 15 is stopped. There is a need. For example, in the cycle n of FIG. 17, the execution history information at times Ta to Tb is output, but the execution history information at times Tb to Tc is not output. In this case, the analysis tool 3 needs to estimate the execution history of the original program execution machine 1 at times Tb to Tc.
[0100]
The analysis tool 3 estimates the operation of the original program execution machine 1 at times Tb to Tc as follows. However, since it is difficult to completely determine the operation of the original program execution machine 1, the update contents of the memory 12 at times Tb to Tc are estimated here. The updated contents of the memory 12 at the times Tb to Tc are expressed by the difference between the contents of the dynamic memory space at the time Tb and the contents of the memory space created based on the execution history information after the time Tc. The dynamic memory space is a memory space that reflects all the contents of the memory data record in the order of application, and is basically created in a space different from the initial memory space 30. Also, the memory space created based on the execution history information after time Tc is basically created in a space different from the initial memory space 30.
[0101]
The analysis tool 3 writes the data corresponding to the initial memory space 30 based on the execution history information at the times Ta to Tb, and then writes the updated contents of the memory 12 at the times Tb to Tc into the initial memory space 30. Thereafter, the analysis tool 3 repeats the same processing for subsequent cycles. Thereby, even if the tracer 15 operates intermittently, a benchmark program for faithfully reproducing the operation of the original program execution machine 1 is created.
[0102]
As described above, the benchmark program 7 of the present embodiment is a load module that reproduces an instruction sequence when the original program is executed in the original program execution machine 1. At this time, the benchmark program 7 may be a load module representing an instruction sequence when only a part of the original program is executed.
[0103]
The function of creating the benchmark program (load module) 7 is realized by executing a program describing the above-described sequence using a computer. FIG. 18 shows the configuration of a computer 100 that executes the program.
[0104]
The CPU 101 loads a program describing the processing shown in the above sequence from the storage device 102 to the memory 103 and executes it. The storage device 102 is a mass storage device and stores the program. On the other hand, the memory 103 is a semiconductor memory, for example, and is used as a work area of the CPU 101. Note that the initial memory space 30 can be realized using the memory 103.
[0105]
The recording medium driver 104 accesses the portable recording medium 105 according to instructions from the CPU 101. The portable recording medium 105 is, for example, a semiconductor device (PC card or the like), a medium (floppy disk, magnetic tape, etc.) to which information is input / output by magnetic action, or a medium (optical disk) to which information is input / output by optical action. Etc.). The communication control device 106 transmits / receives data to / from the network according to instructions from the CPU 101.
[0106]
Here, the benchmark program 7 is created by the tracer 15 that extracts the execution history information 2 from the original program execution machine 1 and the analysis tool 3 (here, including the correction tool 6) that analyzes the execution history information 2. . The tracer 15 is realized by executing the flowchart of FIG. 3 in the original program execution machine 1. On the other hand, the analysis tool 3 is realized by executing the flowchart of FIG. 12 (including the sequences shown in FIGS. 6 to 11) in the computer 100 shown in FIG. However, the analysis tool 3 is not necessarily realized by a computer different from the original program execution machine 1, and may be realized by the original program execution machine 1.
[0107]
FIG. 19 is a diagram for explaining a program providing method for creating a benchmark program. A program for creating a benchmark program is provided by any of the following three methods, for example.
[0108]
(a) Provided installed on a computer. In this case, the program or the like is preinstalled before shipment, for example.
(b) Provided by being stored in a portable recording medium. In this case, the program stored in the portable recording medium 105 is basically installed in the storage device 102 via the recording medium driver 104.
[0109]
(c) Provided by a server on the network. In this case, basically, the computer 100 obtains the program or the like by downloading the program or the like stored in the server.
[0110]
The created benchmark program may be stored in a portable recording medium such as a CD-ROM and provided to the user, or may be sent to the user terminal via a network.
[0111]
(Appendix 1) A method for creating a test program for evaluating an information processing apparatus,
When an original program is executed using a computer having a processor and a memory, instructions executed by the processor and contents of access to the memory are detected,
Store the detected information as execution history information in time series,
A test program creation method, comprising: creating a load module format program for reproducing an instruction execution sequence executed by the computer based on the execution history information.
[0112]
(Appendix 2) A method for creating a test program for evaluating an information processing apparatus,
When an original program is executed by using a computer having a processor and a memory, an instruction code corresponding to an instruction executed by the processor, instruction information related to the instruction, written to the memory, or read from the memory Detects binary data and access information indicating access contents to the memory,
Store the detected information as execution history information in time series,
By analyzing the execution history information in time series and writing the instruction code based on the instruction information and writing the binary data based on the access information in a memory space prepared in advance, A test program creation method characterized by creating a program.
[0113]
(Appendix 3) A test program creation method according to appendix 2,
The memory space has substantially the same address space as the memory included in the computer.
[0114]
(Appendix 4) A test program creation method according to appendix 2,
When the first instruction, which is an instruction that cannot be executed by the device to which the test program is given, is executed by the computer,
Create a processing routine program that replaces the operation of the computer due to the first instruction and write it to the memory space;
An instruction for calling the processing routine program is written in the memory space instead of the first instruction.
[0115]
(Appendix 5) A test program creation method according to appendix 4,
The first instruction is an I / O instruction.
(Appendix 6) A test program creation method according to appendix 2,
When a second instruction, which is an instruction that may cause different operations between when executed by the computer and when executed by an apparatus provided with the test program, is executed by the computer,
Writing the condition referenced by the processor to the memory space when the second instruction is executed in the computer;
An instruction for calling the condition is written to the memory space instead of the second instruction.
[0116]
(Appendix 7) A test program creation method according to appendix 2,
When the first operation, which is an operation that cannot be performed by the apparatus to which the test program is given, is performed by the computer,
Replacing the third instruction, which is an instruction executed in the vicinity of the timing at which the first operation is performed in the computer, with an instruction to switch the instruction sequence, and writing to the memory space;
Create a processing routine program that substitutes for the first operation and write it to the memory space;
An instruction for replacing the instruction sequence is linked to the processing routine program.
[0117]
(Appendix 8) A test program creation method according to appendix 7,
The first operation is an asynchronous interrupt.
(Appendix 9) A test program creation method according to appendix 7,
The processing routine program includes emulation of the third instruction.
[0118]
(Additional remark 10) It is a test program creation method of Additional remark 2, Comprising:
When a logical address is converted to a real address using a plurality of address conversion tables in the computer,
When the plurality of address conversion tables are referenced, reference information representing the reference contents is stored in time series,
Based on the stored reference information, a plurality of tables corresponding to the plurality of address conversion tables are created, and the result of merging these tables is written into the memory space.
[0119]
(Supplementary note 11) The program creation method according to supplementary note 2,
Estimating the update contents of the memory during a period in which the instruction code, instruction information, binary data, and access information are not detected,
Write the estimated update contents into the memory space.
[0120]
(Supplementary note 12) A system for creating a test program for evaluating an information processing apparatus,
Detecting means for detecting instructions executed by the processor and contents of access to the memory when an original program is executed using a computer having a processor and a memory;
Storage means for storing detected information in time series as execution history information;
Creating means for creating a load module type program that reproduces an instruction execution sequence executed by the computer based on the execution history information;
A test program creation system comprising:
[0121]
(Supplementary note 13) A system for creating a test program for evaluating an information processing apparatus,
When an original program is executed by using a computer having a processor and a memory, an instruction code corresponding to an instruction executed by the processor, instruction information related to the instruction, written to the memory, or read from the memory Detecting means for detecting binary data and access information representing access contents to the memory;
Storage means for storing detected information in time series as execution history information;
By analyzing the execution history information in time series and writing the instruction code based on the instruction information and writing the binary data based on the access information in a memory space prepared in advance, Creating means to create programs and
A test program creation system comprising:
[0122]
(Supplementary note 14) In order to create a test program for evaluating the information processing apparatus,
Instructions executed by the processor detected when the original program is executed using another computer having a processor and a memory, and instructions executed by the other computer based on the access contents to the memory Creation means for creating a load module format program that reproduces the execution sequence,
Test program creation program to function as
[0123]
(Supplementary Note 15) In order to create a test program for evaluating the information processing apparatus,
An instruction code corresponding to an instruction executed by the processor, detected when the original program is executed using a computer having a processor and a memory, instruction information related to the instruction, written into the memory, or from the memory Analysis means for analyzing read binary data and access information representing access contents to the memory;
Based on the analysis result by the analysis means, the instruction code is written to a memory space prepared in advance based on the instruction information and the binary data is written based on the access information. Creation means to create,
Test program creation program to function as
[0124]
(Supplementary Note 16) In order to create a test program for evaluating an information processing apparatus,
Detecting means for detecting instructions executed by a processor of the computer and contents of access to the memory of the computer when the original program is executed using the computer;
Creating means for creating a load module format program for reproducing the instruction execution sequence executed by the computer based on the information detected by the detecting means;
Test program creation program to function as
[0125]
(Supplementary Note 17) In order to create a test program for evaluating the information processing apparatus,
When an original program is executed using the computer, an instruction code corresponding to an instruction executed by the processor, instruction information related to the instruction, binary data written to or read from the memory, and Detection means for detecting access information representing access contents to the memory;
The information detected by the detection means is loaded by writing the instruction code on the basis of the instruction information and writing the binary data on the basis of the access information in a previously prepared memory space based on the time series. Creation means for creating a modular program,
Test program creation program to function as
[0126]
(Supplementary Note 18) In order to create a test program for evaluating the information processing apparatus,
Detecting means for detecting instructions executed by a processor of the computer and contents of access to the memory of the computer when the original program is executed using the computer;
Creating means for creating a load module format program for reproducing the instruction execution sequence executed by the computer based on the information detected by the detecting means;
A computer-readable recording medium in which a test program creation program for functioning as a computer is recorded.
[0127]
(Supplementary note 19) In order to create a test program for evaluating the information processing apparatus,
When an original program is executed using the computer, an instruction code corresponding to an instruction executed by the processor, instruction information related to the instruction, binary data written to or read from the memory, and Detection means for detecting access information representing access contents to the memory;
The information detected by the detection means is loaded by writing the instruction code on the basis of the instruction information and writing the binary data on the basis of the access information in a previously prepared memory space based on the time series. Creation means for creating a modular program,
A computer-readable recording medium in which a test program creation program for functioning as a computer is recorded.
[0128]
(Supplementary note 20) A test program for evaluating an information processing apparatus,
An instruction execution sequence executed by the computer is reproduced based on an instruction executed by the processor detected when the original program is executed using a computer having a processor and a memory and contents of access to the memory Load module test program.
[0129]
【The invention's effect】
According to the present invention, the performance can be accurately evaluated before the information processing apparatus is completed. For this reason, the development period of the information processing apparatus can be shortened. In addition, it is possible to efficiently change the design to bring it closer to the target characteristic.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an overview of a program creation method according to an embodiment.
FIG. 2 is a configuration diagram of an original program execution machine.
FIG. 3 is a flowchart showing the operation of the tracer.
FIG. 4 is an example of execution history information.
FIG. 5 is a configuration diagram of an initial memory space.
FIG. 6 is an example of a process for writing an instruction code to an initial memory space.
FIG. 7 is a diagram illustrating processing of an analysis tool when a memory update occurs due to an I / O interrupt.
FIG. 8 is a diagram for explaining processing of an analysis tool when a memory update by an I / O instruction occurs.
FIG. 9 is a diagram illustrating processing of an analysis tool when a dynamic information reference instruction is executed.
FIG. 10A is a diagram showing an instruction sequence when an asynchronous interrupt occurs in the original program execution machine, and FIG. 10B is a diagram for explaining a method for realizing the sequence shown in FIG. It is.
FIG. 11 is a diagram for explaining processing of an analysis tool when an asynchronous interrupt occurs.
FIG. 12 is a flowchart for explaining the operation of the analysis tool.
13A is an example of a list for managing interrupt instructions, and FIG. 13B is a diagram illustrating an example of a method for identifying interrupt instructions.
FIG. 14 is a diagram illustrating compression of an address conversion table.
FIG. 15 is a configuration diagram of a system for creating and verifying a benchmark program.
FIG. 16 is a flowchart showing a procedure for determining a process corresponding to each interrupt instruction when a benchmark program is executed;
FIG. 17 is a diagram for explaining processing when the tracer is operated intermittently;
FIG. 18 is a block diagram of a computer that executes a program describing functions of the present invention.
FIG. 19 is a diagram illustrating a method for providing a software program or the like according to the present invention.
[Explanation of symbols]
1 Original program execution machine
2 Execution history information
3 Analysis tools
4 Basic data
5 Correction data
6 Correction tool
7 Benchmark program
11 CPU
12 memory
13 OS
14 Application programs
15 Tracer
21 External devices
30 Initial memory space
31 Basic memory space
32 Memory space for correction

Claims (7)

The I / O device is connected using at least the history of executing the original program on the first information processing device to which the I / O device is connected and storing the instruction code, the write destination address, and the reference destination address. A creation program for creating a test program for evaluating a second information processing apparatus that is not,
On the computer,
The history including a plurality of sets of the storage address of the instruction code and the instruction code executed by the original program, the procedure for reading from the first memory unit,
If the read instruction code is not an I / O instruction, the instruction code is written to an address where the address to be written to the second storage unit is the storage address of the instruction code;
If the instruction code is an I / O instruction, branch to the load module that emulates I / O access to the I / O device at an address written to the second storage unit that is the storage address of the instruction code Writing a branch code to be written, writing the load module to the branch code destination address of the second storage unit, and creating a test program load module;
Created program to execute. When the read instruction code is an interrupt instruction, the data of the interrupt destination address of the first storage unit is written to the address of the second storage unit corresponding to the interrupt destination address of the interrupt instruction . The creation program according to claim 1, wherein When the read instruction code is a dynamic information reference instruction, the reference destination data is loaded into the address of the second storage unit corresponding to the address of the dynamic information reference instruction in the first storage unit. write the instruction, or the second information processing apparatus to perform the information processing apparatus equivalent to the operation of the first, is replaced with the interrupt attribute instruction, interrupt by該割write attribute command is generated The creation program according to claim 1 or 2, further comprising a processing routine program for performing processing corresponding to the dynamic information reference instruction, which is sometimes called . The asynchronous interrupt occurs after execution of said read the instruction code, when the processing routine is called, the instruction code address in the second storage unit corresponding to the instruction code of the first storage unit 4. The creation program according to claim 1, wherein the creation program is replaced with an instruction for calling a processing routine, and emulation data of the replacement instruction is added to a head of the processing routine .   The creation program according to any one of claims 1 to 4, wherein the computer is the first information processing apparatus. The I / O device is connected using at least the history of storing the instruction code, the write destination address, and the reference destination address when the original program is executed on the first information processing device to which the I / O device is connected. A creation device for creating a test program for evaluating a second information processing device that is not,
Means for reading out the history including a plurality of sets of instruction codes executed by the original program and storage addresses of the instruction codes from the first storage unit;
If the read instruction code is not an I / O instruction, the instruction code is written to an address whose address to be written to the second storage unit is the storage address of the instruction code, and the instruction code is an I / O instruction A branch code that branches to a load module that emulates an I / O access to an I / O device is written to an address whose address to be written to the second storage unit is the storage address of the instruction code, and the second storage Means for writing out the load module to the address of the branch code destination of a section to create a load module of a test program;
A creation device comprising: The I / O device is connected using at least the history of storing the instruction code, the write destination address, and the reference destination address when the original program is executed on the first information processing device to which the I / O device is connected. A creation method for creating a test program for evaluating a second information processing apparatus that is not,
On the computer,
Reading the history including a plurality of sets of instruction codes executed by the original program and storage addresses of the instruction codes from the first storage unit;
If the read instruction code is not an I / O instruction, the instruction code is written to an address whose address to be written to the second storage unit is the storage address of the instruction code, and the instruction code is an I / O instruction A branch code that branches to a load module that emulates an I / O access to an I / O device is written to an address whose address to be written to the second storage unit is the storage address of the instruction code, and the second storage Writing the load module to the branch code destination address of a section to create a test program load module;
How to create.

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