JP2919302B2 - CPU simulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for simulating the operation of a target CPU on a host CPU, and more particularly to a high-speed CPU simulation method.

[0002]

2. Description of the Related Art Before a target machine including a target CPU is completed, or before debugging or performance analysis on the target machine, a program developed for the target CPU (referred to as a target program) is debugged. The target CP is used as an evaluation method.
There is a method of simulating the operation of the target CPU according to the target program on a CPU simulator including a host CPU which is a CPU different from the U. The method includes an interpreter method for sequentially interpreting and executing a source program for the target CPU. The CPU simulation method used is broadly divided into a CPU simulation method using an object simulation method of sequentially interpreting and executing a machine language code of a target CPU (for example, edited by the IEICE Handbook Committee,
Published by Ohmsha Co., Ltd. on March 30, 1988, 1st edition, "Electronic Information and Communication Handbook Second Volume," p. 1857, 5.3 Simulator).

[0003] Here, a CP using an interpreter system is used.
The U simulation method simulates while directly interpreting a source program (source program) for the target CPU. The CPU simulation method using the object simulation method uses the source program (target program) of the target program prior to the simulation. The source program is compiled or assembled, converted into a machine language level instruction code of the target CPU, and the instruction code is simulated.

[0004] The CPU simulation method using the object simulation method is based on a target CPU.
It takes time to generate machine language level instructions,
The simulation execution time is faster than the CPU simulation method using the interpreter method. Therefore, when a short simulation time is required, the CPU simulation method using the object simulator method is used. If the target program already exists at the machine language level, it goes without saying that compilation or assembling is unnecessary.

[0005] In the CPU simulation method using the object simulation method,
For example, as described in Japanese Patent Application Laid-Open No. 2-250122, an instruction code of a target CPU is executed at the time of execution on a host CPU.
Simulating while interpreting each instruction.

As described above, the CPU simulation method using the object simulation method is superior in terms of simulation speed as compared with the interpreter method. However, unlike the conventional method, the instruction code of the target CPU is executed at the time of execution on the host CPU. In a configuration in which the interpretation is executed one instruction at a time, the time required for the interpretation becomes an overhead during the execution of the simulation.

[0007]

In the CPU simulation method using the interpreter system or the object simulation system for simulating a target program of a target CPU on a host CPU, the time required for executing the simulation is increased. There is.

Accordingly, the present invention provides a host CPU having an instruction set compatible with or upwardly compatible with a target CPU.
It is an object of the present invention to perform a target program simulation at high speed on a host CPU having the same architecture as that of the target CPU.

[0009]

According to the present invention, a target C is provided.
In a CPU simulation method in which instruction simulation means for simulating a machine language level instruction of a PU is executed by a host CPU, the host C
When the PU has a machine language instruction set compatible with or upwardly compatible with the machine language level instruction set of the target CPU, or when the host CPU has the target CP
When the target program developed for the target CPU is loaded, when the same type of architecture as U is used.
Among instructions at the machine language level of the target program, instructions that can be directly executed by the host CPU are arranged in memory as they are, and restrictions on the operating system operating on the host CPU and the restrictions on the target CPU and the host Instructions that cannot be directly executed due to differences in the functions of the CPU are replaced with instruction simulation means call instructions and arranged in memory, and the instruction simulation is executed.
Instruction replaced by the instruction
The instructions that can be directly executed by the host CPU are directly executed by the host CPU, and the instructions that cannot be directly executed by the host CPU are replaced by the instruction stored by the instruction simulation unit calling instruction .
The simulation is performed by instruction simulation means called with reference to the instruction and the address to be executed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a CPU simulator to which the CPU simulation method according to the present invention is applied. This CPU simulator 1 has a host C
A PU 12 and a memory 11 are provided. The memory 11
Host CPU 12 included in target program 2
A process that replaces an instruction that cannot be directly executed by the instruction with an instruction that calls the instruction simulation unit 15, and an instruction replacement unit 10 that registers an instruction code and its address before replacement in the replacement instruction position storage area 14;
The instruction code area 13 after replacement, the replacement instruction position storage area 14, and the instruction simulation means 15 are stored.

The target program 2 includes a target C
This is a program developed for a PU (not shown; the same applies hereinafter), and includes instruction codes 2-1 to 2-n at the machine language level of the target CPU.

The instruction code area 13 after replacement is a set of instruction codes included in the target program 2 that can be directly executed by the host CPU 12 and instructions that cannot be directly executed by the CPU 12 are replaced with instruction simulation means calling instructions. is there. When the instruction code 2-2 among the instruction codes in the target program 2 cannot be directly executed by the host CPU 12, the instruction code 2-2 is converted into an instruction simulation means call instruction 13-2 and arranged on the memory 11. Instruction code 2-1 and 2-n is host C
In the case of an instruction that can be directly executed by the PU 12, the instruction code 13-1, 13-n is arranged on the memory 11 as it is.

The instruction simulation means 15 is called by an instruction simulation means call instruction included in the instruction code area 13 after replacement. The called instruction simulation means 15 acquires the instruction code before replacement from the replacement instruction position storage area 14 based on the address of the instruction simulation means calling instruction, and simulates the instruction code.
After the simulation is completed, the instruction simulation means 1
5 performs processing for returning to the next instruction code portion to be executed in the instruction code area 13 after replacement.

When simulating the operation of the target CPU according to the target program 2, the CPU simulator 1 activates the instruction replacing means 10 before executing the simulation.

The instruction replacing means 10 sequentially reads and interprets each of the instruction codes 2-1 to 2-n of the target program 2 and determines whether or not the instruction code can be directly executed by the host CPU 12. If the instruction code cannot be directly executed by the host CPU 12, the instruction code is replaced with an instruction simulation means calling instruction, and a set of the address of the replaced instruction and the instruction code before the replacement are registered in the replacement instruction position storage area 14. If the read instruction code is an instruction directly executable by the host CPU 12, no replacement is performed.

For example, if the instruction code 2-1,2-n is the host CP
If the instruction code 2-2 is an instruction code that can be directly executed by the U12 and the instruction code 2-2 cannot be directly executed by the host CPU 12, the instruction replacement means 10 replaces the instruction code 2-2 with an instruction simulation means call instruction. 2-1,2-n is not replaced. By this processing, when the instruction codes 2-1 to 2-n are stored in the memory as the instruction codes 13-1 to 13-n, the instruction code 13-1 and the instruction code 13-n are restored to the original instruction code 2 -1
The instruction code 2-2 is the same instruction code as the instruction code 2-n. The instruction code 2-2 is replaced and replaced by the instruction simulation means calling means 13-2 and stored in the memory 11. The instruction replacement means 10 registers the set of the address of the replaced instruction code 2-2 and the instruction code before replacement in the replacement instruction position storage area 14 at this time.

The instruction replacing means 10 in FIG. 1 stores the result in the memory 11, but temporarily stores the contents of the replaced instruction code area 13 and the contents of the replaced instruction position storage area 14 in an external storage device (not shown). It is also possible to store the contents of the instruction code area 13 after replacement and the contents of the replacement instruction position storage area 14 from the external storage device 3 into the memory 11 when executing the simulation.

When the replaced instruction code area 13 is generated in the memory 11 by the instruction replacing means 10, the CPU simulator 1
1 to execute the replaced instruction code area 13.

The host CPU 12 first executes the instruction code in the instruction code area 13 after replacement corresponding to the execution start address of the target program. In the case of an instruction other than the instruction simulation means call instruction, the instruction code is executed by the host CPU 12 as it is.
If the executed instruction is an instruction simulation means call instruction, the execution moves to the instruction simulation means 15.

The instruction simulation means 15 obtains the instruction code before replacement from the replacement instruction position storage area 14 based on the address of the instruction to call the instruction simulation means, and simulates the instruction code. Do. After the simulation, the process is returned to the position of the next instruction code to be executed in the replaced instruction code area 13.

Thereafter, by repeating the above operation, the instruction in the instruction code area 13 after the replacement is executed, and the target CP according to the target program 2 is executed.
The operation of U is simulated on the host CPU 12.

FIG. 2 is a flowchart showing the processing of the instruction replacing means 10. In step 101, a process of reading one instruction of the target program stored in a memory or a file (not shown) is performed.

Next, in step 102, it is determined whether or not the instruction read in step 101 is an instruction that can be directly executed by the host CPU.
To step 104 if the instruction is not directly executable
Proceed to.

In step 103, the instruction code area 13 after replacing the instruction code read in step 101
Perform the process of storing in. Then the target program
Judge whether all the instruction codes of step 2 have been read,
If all instructions have not been read, step 101
Proceed to and terminate the process if all instructions have been read
You .

In step 104, the instruction code area 13 after replacing the instruction simulation means calling instruction
The processing for storing in is performed. Then, in step 101,
Instruction code and its instruction code are allocated in memory
Replaced address is stored in instruction position storage means 14
Perform the following processing. After that, the life of target program 2
It is determined whether all the instruction codes have been read and all
If no instruction has been read, proceed to step 101.
When all instructions have been read, the process ends.
You.

[0027]

[0028]

In the following, the target CPU is M3000 R3000, the host CPU is R3000, UNIX is installed as an operating system, and the CPU simulator is U3000.
An example of instruction replacement when operating as a NIX application program is shown in assembler notation. Also,
The addresses where the instructions are located are Addr_1 to Addr for explanation.
Use the label name _5.

○ Instruction code in target program Addr_1: srl ra, ra, 6 / * Directly executable on host CPU * / Addr_2: sll ra, ra, 6 / * Directly executable on host CPU * / Addr_3: or gp, gp, ra / * Execute directly on host CPU * / Addr_4: mtc0 gp, sr / * Impossible directly on host CPU * / Addr_5: lw ra, 0x50 (sp) / * On host CPU Directly executable * / ○ Instruction code after replacement Addr_1: srl ra, ra, 6 / * No replacement * / Addr_2: sll ra, ra, 6 / * No replacement * / Addr_3: or gp, gp, ra / * Replace None * / Addr_4: .word 0xfffffffe / * Replacement of instruction * / Addr_5: lw ra, 0x50 (sp) / * No replacement * / The above srl, sll, or, lw instructions are operating as UNIX application programs Although the host CPU can be executed directly on the CPU simulator, the mtc0 instruction is a privileged instruction and must be used as a UNIX application program. CPU simulator that is running can not be executed directly. Therefore, the mtc0 instruction is an instruction simulation means calling means (in this example, .word 0xff
fffffe).

As can be seen from the specific example described above, in step 102, it is determined whether or not the CPU simulator operating as a UNIX application program is a directly executable instruction.
In step 103, the process of arranging in the memory as it is is performed, and in the case of an instruction that cannot be directly executed, in step 104, the process of arranging in the memory by replacing the instruction simulation means calling instruction (in this example, using .word 0xfffffffe) is performed.

[0032] In the case of the instruction can not be executed directly, in step 10 4, the address and instruction code of the instruction of performing the replacement is performed a process of storing the replacement instruction position storage area 14 in FIG. 1.

[0033] In this example, information stored in the instruction position storage area 14 replaced by Step 10 4,

[0034]

This is the instruction code before it is replaced with the address of the instruction.

The instruction code ".word0xfffffffe" used as the instruction simulation means calling means in this example is an illegal instruction in the R3000 CPU. UN
When the CPU simulator, which is an application program on the IX, executes this instruction, UNIX starts a processing routine called a signal handler. In order to transfer control to the instruction simulation means in this example, it is necessary to separately prepare a signal handler (not shown) and call the instruction simulation means 15 from this signal handler.

FIG. 3 illustrates an example of information stored in the replacement instruction position storage area 14 in FIG. The information stored in the replacement instruction position storage area 14 is the address of an instruction that cannot be directly executed by the host CPU 12 and the code of the instruction. In FIG. 3, addresses are shown by label names and instruction codes are shown by assembler notation for explanation. In this example, target program 2
Instruction “mtc0 gp, sr” at address “Addr_4” in
This indicates that the instruction “mfc0 s0, sr” at the address “Addr_25”, the instruction “tlbp” at the address “Addr_48”, and the instruction “tlbr” at the address “Addr_62” have been replaced.

FIG. 4 is a flowchart showing the processing in the instruction simulation means 15 in FIG.

At step 151, the host CPU 1 at the time when the instruction simulation means calling instruction is executed is executed.
A process of collecting the register information of No. 2 is performed.

[0040] Next, in step 15 3, based on the address of the instruction simulation means call instruction, executes the process of acquiring the instruction code before it is replaced as a replacement instruction position storage area 14.

[0041] In the next step 15 4, step 15 3
Analyze the instruction before replacement obtained in the above, and execute the instruction simulation process for simulating the instruction before replacement.

[0042] Step 15 5 -1~15 5 -m is a part for instruction simulation processing, the processing for each type of instruction is provided. Here, step 152 in which the register information collected in step 151 is stored.
Simulate the instruction while referring to and changing.

[0043] In next step 15 6, step 155
The register information changed as a result of the simulation of the instruction executed in step 2 is returned to the register of the host CPU.

[0044]

As described above, according to the present invention, it is not necessary to interpret and simulate all instruction codes at the time of executing a simulation, so that a simulation can be performed at a higher speed than a conventional CPU simulation method.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of an embodiment of a CPU simulator to which the present invention is applied.

FIG. 2 is a functional block diagram showing a configuration example of an instruction replacement unit 10 in FIG.

FIG. 3 is a diagram showing an example of information stored in a replacement instruction position storage area 14 in FIG.

FIG. 4 is a functional block diagram showing a configuration example of an instruction simulation means 15 in FIG. 1;

[Explanation of symbols]

 Reference Signs List 1 CPU simulator 10 Instruction replacement means 11 Memory 12 Host CPU 13 Instruction code area after replacement 13-1,13-n instruction code 13-2 Instruction simulation means call instruction 14 Replacement instruction position storage area 15 Instruction simulation means 2 Target program 2 -1 to 2-n Instruction code 3 External storage device

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-1020 (JP, A) JP-A-62-128339 (JP, A) PATTERSON, HENNESS Y “COMPUTER ORGANIZATION & DESIGN: THE HARDWARE / SOFTWARE INTERFACE Morgan Kaufmann Publishers (1994), Appendix A (58) Fields studied (Int. Cl. ⁶ , DB names) G06F 9/44 G06F 11/26

Claims (1)

(57) [Claims] 1. A CPU simulation method in which an instruction simulation means for simulating a machine language level instruction of a target CPU is executed by the host CPU.
Loading a target program developed for the target CPU if the host CPU has a machine language instruction set compatible or upward compatible with the instruction set at the machine language level of U, or if the host CPU has the same type of architecture as the target CPU; Sometimes the target program
Instructions that can be directly executed by the host CPU among the instructions at the machine language level of the system are directly arranged in the memory, and the restrictions on the operating system operating on the host CPU, the target CPU and the host CP
Instruction can not be executed directly by the difference in the U functionality is placed in the memory by replacing the instruction simulation unit call instruction, the instruction simulation unit call instruction
Instructions that can be directly executed by the host CPU are stored directly, and instructions that cannot be directly executed by the host CPU are stored.
The stored corresponding instruction and address are referred to by the replaced instruction simulation means calling instruction.
CPU simulation method characterized in that it is simulated by the instruction simulation means to be called by irradiation.