JPH08305583A - Method for simulating cpu - Google Patents

Abstract

PURPOSE: To do simulation of a target program working on a host CPU at a high speed working on a target CPU. CONSTITUTION: An instruction replacement means 10 replaces an instruction not executed directly on a host CPU with an instruction simulation means call instruction while leaving an instruction code directly executed by the host CPU among instructions included in a target program 2, stores the replaced code to an instruction code area 13 and an address of the replaced instruction and the instruction code are stored in a replacement instruction position storage area 14. When the host CPU 12 executes the instruction code stored in the instruction code area after the replacement, the instruction executed directly is directly executed and when the instruction simulation means call instruction is executed, an instruction simulation means 15 is called and the instruction not directly executed is simulated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simulating the operation of a target CPU on a host CPU, and more particularly to a high speed CPU simulation method.

[0002]

2. Description of the Related Art Before a target machine including a target CPU is completed, or debug or performance analysis is performed on the target machine, a program developed for the target CPU (referred to as a target program) is debugged and performance is improved. Target CP is used as an evaluation method.
There is a method of simulating the operation of the target CPU related to the target program on a CPU simulator including a host CPU which is a CPU different from U, and the method is an interpreter method for sequentially interpreting and executing the source program for the target CPU. It is roughly divided into a CPU simulation method used and a CPU simulation method using an object simulation method for sequentially interpreting and executing the machine language code of the target CPU (for example, edited by the Institute of Electronics and Communication Engineers Handbook Committee,
Ohmsha Co., Ltd., issued March 30, 1988, first edition "Electronic Information and Communication Handbook Second Volume", page 1857, 5 ・ 3 "Simulator").

Here, a CP using an interpreter system
The U simulation method simulates a source program for the target CPU by directly interpreting it, and the CPU simulation method using the object simulation method uses a source program (source program) of the target program prior to the simulation. A source program) is compiled or assembled and converted into a machine language level instruction code of the target CPU, and this instruction code is simulated.

The CPU simulation method using the object simulation method is a
It takes time to generate machine language level instructions,
Since the simulation execution time is faster than the CPU simulation method using the interpreter method, the CPU simulation method using the object simulator method is used when a short simulation time is required. Needless to say, if the target program already exists at the machine language level, no compilation or assembly is necessary.

In the CPU simulation method using the object simulation method,
For example, as shown in Japanese Patent Laid-Open No. 2-250122, the instruction code of the target CPU is 1 when executed on the host CPU.
While interpreting each instruction _that is promoting the simulated.

As described above, the CPU simulation method using the object simulation method is superior to the interpreter method in terms of simulation speed, but when executing the instruction code of the target CPU on the host CPU as in the conventional case. In the configuration in which the instructions are interpreted and executed one by one, the time required for the interpretation becomes an overhead when the simulation is executed.

[0007]

In the CPU simulation method using the interpreter method or the object simulation method for simulating the target program of the target CPU on the host CPU, the problem that the time required for executing the simulation becomes long. There is.

Therefore, the present invention provides a host CPU having an instruction set compatible with or upward compatible with the target CPU.
The object is to perform the simulation of the target program at high speed on the host CPU having the same architecture as the target CPU.

[0009]

The present invention provides a target C
Simulate PU machine language level instructions
_In a CPU simulation method for executing an _instruction simulation means by a host CPU, when the host CPU has a machine language instruction set compatible with _or higher than the machine language level instruction set of the target CPU, _{or the} host CPU has the target C
In the case of having the same kind of architecture as the PU, of the machine language level instructions of the target program developed for the target CPU, the instructions that can be directly executed by the host CPU are directly placed in the memory, and the host CP
An instruction that cannot be directly executed due to a limitation of the operating system operating on U and a difference in function between the target CPU and the host CPU is replaced with an instruction simulating means calling instruction and placed in the memory so that the host CPU directly executable instructions executed directly by the host CPU, the instructions the host CPU can not directly execute it is an _feature that is simulated by the instruction simulation unit that is called by the instruction simulation unit call instruction.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a CPU simulator to which the CPU simulation method according to the present invention is applied.
_{This CPU simulator 1 includes a host CPU 12 and a CPU.
Mori 11 and. The memory 11} replaces an instruction included _{in the} target program 2 that cannot be directly executed by the host CPU 12 with an instruction that calls the instruction simulation means 15, and replaces an instruction code and its address before the instruction replacement storage area 1
4, the instruction replacement means 10 _, the instruction code area 13 after replacement, and _the replacement instruction position storage area 14
_, Instruction simulation means 15 are stored.

The target program 2 is the target C
It is a program developed for a PU (not shown; the same applies hereinafter), and is composed of machine language level instruction codes 2-1 to 2-n of the target CPU.

The post-replacement instruction code area 13 is a set of instructions that can be directly executed by the host CPU 12 among the instruction codes included in the target program 2 and instructions that cannot be directly executed by the CPU 12 are replaced by instruction simulation means calling instructions. is there. Of the instruction codes in the target program 2, if the instruction code 2-2 cannot be directly executed by the host CPU 12, it is converted into an instruction simulation means call instruction 13-2 and placed in the memory 11. Command code 2-1 and 2-n are host C
In the case of executable instructions directly by _PU12, it is arranged as the instruction code 13-1,13-n on intact memory 11.

The instruction simulation means 15 is called by the instruction simulation means call instruction included in the instruction code area 13 after replacement. The called instruction simulation unit 15 acquires the instruction code before replacement from the replacement instruction position storage area 14 based on the address of the instruction simulation unit call instruction, and simulates the instruction code.
After the simulation is completed, the instruction simulation means 1
Step 5 performs a process of returning to the instruction code portion to be executed next in the instruction code area 13 after replacement.

When executing the simulation of the operation of the target CPU according to the target program 2, the CPU simulator 1 activates the instruction replacing means 10 prior to the execution of the simulation.

The instruction replacing means 10 sequentially reads and interprets each instruction code 2-1 to 2-n of the target program 2, and determines whether the instruction can be directly executed by the host CPU 12. When the instruction code cannot be directly executed by the host CPU 12, the process of replacing with the instruction simulation means calling instruction, and the address of the replaced instruction and the set of the instruction code before the replacement are registered in the replacement instruction position storage area 14. If the read instruction code is an instruction that can be directly executed by the host CPU 12, no replacement is performed.

For example, the instruction codes 2-1 and 2-n are host CPs.
Directly executable instructions encoded by U12, if the instruction opcode 2-2 can not be executed directly by the host CPU 12, although the instruction replacement means 10 performs replacement instruction codes 2-2 in instruction simulation unit call instruction, _{the instruction code} No replacement is performed for 2-1,2-n. By this processing, when the instruction codes 2-1 to 2-n are stored in the memory as the instruction codes 13-1 to 13-n, the instruction code 13-1 and the instruction code 13-n are the original instruction code 2 -1
, The same instruction code as the instruction code 2-n, and the instruction code 2-2 is replaced and replaced by the instruction simulation means calling means 13-2 and stored in the memory ₁₁ . The instruction replacing means 10 registers the set of the address of the instruction code 2-2 replaced at this time and the instruction code before replacement in the replacement instruction position storage area 14.

Although the instruction replacement means 10 in FIG. 1 stores the result in the memory 11, the contents of the instruction code area 13 and the contents of the replacement instruction position storage area 14 after replacement are temporarily stored in an external storage device (not shown). It is also possible to store and read the contents of the instruction code area 13 after replacement and the contents of the replacement instruction position storage area 14 from the external storage device ₃ into the memory 11 when the simulation is executed.

In the CPU simulator 1, when the replaced instruction code area 13 is generated on the memory 11 by the instruction replacement means 10, the memory 1 is stored in the host CPU 12.
The instruction code area 13 after the replacement on 1 is executed.

The host CPU 12 first executes the instruction code in the instruction code area 13 after replacement corresponding to the execution start address of the target program. In the case of an instruction other than the instruction simulating means call instruction, the instruction code is directly executed by the host CPU 12.
When the executed instruction is the instruction simulating means calling instruction, the execution shifts to the instruction simulating means 15.

The instruction simulating means 15 acquires the instruction code before replacement from the replacement instruction position storage area 14 based on the address of the instruction simulating means calling instruction which caused the call, and simulates the instruction code. To do. After the simulation is completed, the processing is returned to the position of the instruction code to be executed next in the instruction code area 13 after replacement.

Thereafter, by repeating the above operation, the instruction in the instruction code area 13 after the replacement is executed, so that the target CP of the target program 2 is executed.
The operation of U is simulated on the host CPU 12.

FIG. 2 is a flow chart showing the processing of the instruction replacement means 10. In step 101, it performs a process of reading a command _of the target program stored in the memory or file (not shown) or the like.

Next, at step 102, it is judged whether or not the instruction read at step 101 can be directly executed by the host CPU.
If the instruction is not directly executable, go to step 104.
Go to.

In step 103, the instruction code read in step 101 is stored in the replaced instruction code area 13.

In step 104, the instruction simulation means call instruction is stored in the instruction code area 13 after replacement.

In step 105, the instruction code read in step 101 and the address where the instruction code is arranged in the memory are stored in the replacement instruction position storage means 14.

[0028] In step 106, it is determined whether or not read _all the instruction code of the target program 2,
Step 101 if all instructions have not been read
If all the instructions have been read, the process ends.

Below, the target CPU is M3000 R3000, the host CPU is R3000, UNIX is installed as an operating system, and the CPU simulator is U.
An example of instruction replacement when operating as a NIX application program is shown in assembler notation. Also,
The address where the instruction is arranged is Addr_1 to Addr for the purpose of explanation.
Use the label name _5.

○ Instruction code in the target program Addr_1: srl ra, ra, 6 / * Directly executable on the host CPU * / Addr_2: sll ra, ra, 6 / * Directly executable on the host CPU * / Addr_3: or gp, gp, ra / * Can be executed directly on the host CPU * / Addr_4: mtc0 gp, sr / * Cannot be executed directly on the host CPU * / Addr_5: lw ra, 0x50 (sp) / * On the host CPU Directly executable * / ○ Instruction code after replacement Addr_1: srl ra, ra, 6 / * No replacement * / Addr_2: sll ra, ra, 6 / * No replacement * / Addr_3: or gp, gp, ra / * Replacement None * / Addr_4: .word 0xfffffffe / * Replace instruction * / Addr_5: lw ra, 0x50 (sp) / * No replacement * / The above srl, sll, or, lw instructions operate as UNIX application programs. Although the host CPU can be executed directly on the CPU simulator, the mtc0 instruction is a privileged instruction, so it must be a UNIX application program. CPU simulator that is running can not be executed directly. Therefore, the mtc0 instruction is the instruction simulation means calling means (.word 0xff in this example).
I am using fffffe).

As can be seen from the specific example described above, in step 102, it is determined whether the CPU simulator operating as the UNIX application program can directly execute the instruction.
In step 103, the process of arranging in the memory is performed as it is, and in the case of an instruction that cannot be directly executed, in step 104, it is replaced with the instruction simulation means calling instruction (in this example, .word 0xfffffffe is used) and is placed in the memory.

If the instruction cannot be directly executed, the address and the instruction code of the instruction replaced in step 105 are stored in the replacement instruction position storage area 14 of FIG.

In this example, the information stored in the replacement command position storage area 14 in step 105 is

[0034]

This is the instruction code before it is replaced with the address of the instruction.

The instruction code ".word0xfffffffe" used as the instruction simulation means calling means in this example is an illegal instruction in the R3000 CPU. UN
When a CPU simulator, which is an application program on IX, executes this instruction, UNIX starts a processing routine called a signal handler. In this example, in order to transfer control to the instruction simulation means, it is necessary to separately prepare a signal handler (not shown) and call the instruction simulation means 15 from this signal handler.

FIG. 3 shows an example of information stored in the replacement command position storage area 14 in FIG. The information stored in the replacement instruction position storage area 14 is the address of an instruction that cannot be directly executed by the host CPU 12 and the code of that instruction. In FIG. 3, for the sake of explanation, addresses are shown as label names and instruction codes are shown in assembler notation. In this example, target program 2
The instruction “mtc0 gp, sr” at the address “Addr_4” in the
It indicates that the instruction “mfc0 s0, sr” at the address “Addr_25”, the instruction “tlbp” at the address “Addr_48”, and the instruction “tlbr” at the address “Addr_62” have been subject to instruction replacement.

FIG. 4 is a flow chart showing the processing in the instruction simulation means ₁₅ in FIG.

In step 151, the host CPU 1 at the time when the instruction simulation means call instruction is executed
A process of collecting register information 2 is performed.

Next, at step 152, processing for acquiring the instruction code before being replaced from the replacement instruction position storage area 14 is performed based on the address of the instruction simulating means calling instruction.

Next, at step 153, the instruction before replacement obtained at step 152 is analyzed, and the execution is shifted to the instruction simulation processing for simulating the instruction before replacement.

Steps 154-1 to 154-m are parts for performing instruction simulation processing, and processing is prepared for each type of instruction. Here, a simulation of the instruction referring _Oyo change beauty the collected register information in step 151.

Next, in step 155, the register information changed as a result of the simulation of the instruction executed in the previous step is returned to the register of the host CPU.

[0044]

As described in the foregoing, in the present invention because there is no need to interpret and simulate all the instruction code during simulation run, which enables high-speed simulation than conventional CPU _{simulation method.}

[Brief description of drawings]

FIG. 1 is a functional block diagram of an embodiment of a CPU simulator to which the present invention is applied.

FIG. 2 is a functional block diagram showing a configuration example of instruction replacing means 10 in FIG.

3 is a diagram showing an example of information stored in a replacement instruction position storage area 14 in FIG.

FIG. 4 is a functional block diagram showing a configuration example of an instruction simulation means 15 in FIG.

[Explanation of symbols]

 1 CPU Simulator 10 Instruction Replacement Means 11 Memory 12 Host CPU 13 Instruction Code Area after Replacement 13-1, 13-n Instruction Code 13-2 Instruction Simulation Means Calling Instruction 14 Replacement Instruction Position Storage Area 15 Instruction Simulation Means 2 Target Program 2 -1 to 2-n instruction code 3 External storage device

Claims (1)

[Claims] 1. A CPU simulation method in which an _instruction simulation means for simulating a machine language level instruction of a target CPU is executed by a host CPU, wherein the host CPU is compatible _or upward compatible with a machine language level instruction set of the target CPU. Of the machine language level instructions of the target program developed for the target CPU, the host CPU can directly execute if it has a machine language instruction set _or if the host CPU has the same architecture as the target CPU. The instruction is placed in the memory as it is, the limitation of the operating system operating on the host CPU and the target CPU and the host CP.
Instructions that cannot be directly executed due to a difference in the function of U are replaced with instruction simulation means calling instructions and placed in the memory, so that instructions that can be directly executed by the host CPU are directly executed by the host CPU and the host C
The instruction that the PU cannot directly execute is simulated by the instruction simulation means called by the instruction simulation means call instruction.
CPU simulation method and _butterflies.