JPH10320212A - Cache optimizing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute cache optimization based on accurate cache miss ratio prediction. SOLUTION: In a step 202, whether this compiling is 1st step compiling or not is checked. In the case of the 1st step compiling, processing goes to a step 203 and cache simulation padding processing is executed. In a case other than the 1st step compiling, the processing goes to a step 204 and cache optimizing processing is executed. In the code generating processing 203, an intermediate code 307 is inputted and an object program 309 or 313 described by machine words or an assembling language is generated. (The cache simulation object program 309 is generated in the 1st step compiling and the final object program 313 is generated in the 2nd step compiling).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION In computer utilization technology,
The present invention relates to a compiling method for reducing the execution time of an object program. In particular, the present invention relates to an optimization method by a compiler for reducing a decrease in performance due to a cache miss.

[0002]

2. Description of the Related Art Many methods for reducing the execution time of an object program generated by a compiler have been developed. One of them is optimization for caching by a compiler.

As one of the optimization methods for cache,
There is software prefetch optimization. Software prefetch optimization, data is stored in main storage (memory)
Instruction to move data from to cache (prefetch instruction)
Is inserted into the object program by the compiler to reduce (conceal) the waiting time (cache miss penalty) generated at the time of a cache miss. For details on software prefetch optimization methods, see, for example, Bernstein et al .: Compiler Techniques for Da.
ta Prefetching on the PowerPC, PACT '95, 1995, pp.
19-26 ".

In software prefetch optimization, a compiler generates a code that issues a prefetch instruction before data access (load or store) that is likely to cause a cache miss. That is, data is moved from the memory to the cache by a prefetch instruction, and a cache miss does not occur in an actual access instruction. (The latency is concealed by inserting another unrelated instruction between the prefetch instruction and the load or store instruction.) That is, for one data access, two instructions of the prefetch instruction and the access instruction are used. Need to do it. Therefore, if software prefetch is performed for access to data that does not cause a cache miss, issuing a prefetch instruction is useless (overhead).
And there is a problem that the performance is reduced accordingly.

In order to solve this problem, a conventional compiler analyzes a source program and performs optimization for cache (for example, software prefetch) only for data access that is likely to cause a cache miss. I have. As a method of statically analyzing the possibility of causing a cache miss, "Wolf et al .: A DataLo
cality Optimizing Algorithm, ACM SIGPLAN '91, 199
1, pp.30-40 "(called reuse analysis). In this method, by examining the subscript part of the array reference code that appears in the loop nest (nest of loops) in the program, it is determined whether the data is reused, and the time interval until the data is reused. Is analyzed.
If certain data is found to be reused during a relatively short interval, the data is presumed to remain in the cache.

[0006]

In the optimization method for a cache using the above-mentioned conventional technology (reuse analysis method),
There was a problem that a mistake would occur in prediction of a cache miss. For example, in the conventional method, when predicting a cache miss, the analysis is often performed based on the size of the array in the program and the number of loop iterations, but these values are determined at the time of execution (static analysis). Cannot be obtained in many cases), and as a result, the cache miss prediction often deviates.

FIG. 4 shows an example of such a program.
FIG. 4 shows a program written in the Fortran language.
NC subroutine is defined. From the parameter declaration section 401, FUNC is A, B, C, N, M
It is shown that two parameters (arguments) are input, and A, B, and C are arrays from the variable declaration sections 402 to 403.
It is shown that M and N are integers. A two-dimensional array A
The size of the first dimension is 1 to N, the second dimension is 1 to M,
The sizes of the one-dimensional arrays B and C are 1 to N. Since the size of the array used in the program is determined by the input parameters M and N, the compiler cannot determine the size. The program execution units 403 to 407 form a double loop, and the range of the loop is determined by the input parameters M and N, where J is 1 to M and I is 1 to N. When estimating the cache miss rate in such a program, the range of the loop and the size of the array are important clues, so that if these are not known statically, the prediction becomes uncertain.

In addition, there is a problem that it is difficult to predict a competitive cache miss in the conventional method. A competitive cache miss is a cache miss that occurs in a direct map type or set associative type cache. Although the cache capacity is sufficiently large, the cache addresses of two or more data (addresses stored in the cache). ) Happen to coincide with each other. Such a cache miss is difficult to predict by static analysis of the program.

In the case where a cache miss is predicted based on a static analysis of a program as described above, the prediction is likely to be missed. Therefore, the optimization is not applied to the place where the cache optimization is really required, or is not required ( That is, there is a problem that useless optimization is performed on a portion where the cache miss rate is low), which becomes an overhead.

An object of the present invention is to more accurately determine a cache miss rate for each data access in a program,
An object of the present invention is to provide a method for performing efficient optimization for a cache without waste by a compiler by utilizing the above.

[0011]

The above object is solved by a two-stage compiling method using feedback as follows.

In the first stage of compiling, an object program is generated by inserting, into each memory reference code in a source program, a code that simulates a cache operation in the memory reference. Then the first
Data that records the cache miss rate of each memory reference by executing the object program generated in the stage compilation (cache miss rate recording file)
Create Next, in the second stage of compilation, a final object program is generated using the cache miss rate recording file and the original source program as inputs.
In the second stage of compilation, the cache miss rate at each memory reference is known, so that a memory reference to which cache optimization such as software prefetch is applied can be appropriately selected, and effective optimization can be performed.

In the cache simulation, a cache miss of a competitiveness which cannot be predicted by a static analysis can be correctly simulated, so that the cache optimization for the competitive cache miss can be applied without fail.

For this reason, the compiler checks whether or not the current compilation is the first-stage compilation. If the current compilation is the first-stage compilation, the compiler performs a cache simulation code embedding process. The process is performed, and in the cache optimization process, a portion to which the cache optimization is applied is selected using the cache miss rate data.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below.

FIG. 3 is a configuration diagram of a computer system according to the present invention. As shown, the computer system has a CPU
The system includes a main storage device 301, a main storage device 302, an external storage device 303, a display device 304, and a keyboard 305. The external storage device 303 stores the source program 30
8, a cache simulation object program 309, a cache simulation library 310, a cache simulation load module 311, an object program 312, and a cache miss rate recording file 313 are stored. Main storage device 3
02 holds the compiler 306 and the intermediate code 307 required in the compilation process. The compiling process is performed by the CPU 301 executing the compiler program 306. The keyboard 305 is used to give a command from the user to the compiler 311. Display device 304 informs the user of the end of compilation or an error.

FIG. 1 shows a procedure of a compile process by a user in the compiler according to the present embodiment. The compilation process is the first stage compilation 10
1, four steps: link 102, execution 103, and second stage compilation 104. First stage compilation 1
01, an object program (cache simulation object program) 30 in which a code for simulating the cache operation at the time of execution of the program is embedded in the source program 306.
7 is created. Next, the cache simulation load module 310 is created by linking the cache simulation object program 307 and the cache simulation library 309 with the link 102. Since the link processing is a known technique, it will not be described in detail here. Next, in execution 103,
Load module 310 for cache simulation
To create the cache miss rate recording file 313. Finally, the second stage compilation 104
Then, using the cache miss rate recording file 313, an object program 312 in which the source program 306 is optimized for cache is created. First
The flow of the compiler processing in the compiling of the stage and the second stage will be described with reference to FIG.

FIG. 2 is a flowchart showing the flow of the compiling process. In the processing of the compiler, first, in step 201, syntax analysis 201 is performed. The syntax analysis reads the source program 306 and creates an intermediate code 307 that can be processed inside the compiler. The syntax analysis processing is described in, for example, "Eiho, Seshi, Ullman: Compiler I (Science Inc., 1990), pp. 30-74".
And will not be described in detail here. Next, at step 202, it is checked whether the main compilation is the first stage compilation. Whether or not the compilation is the first stage is determined by a compilation command from the user. Step 203 if the compilation is the first stage
And a cache simulation code embedding process is performed. In this processing, this processing will be described later in detail with reference to the flowchart of FIG. If it is not the first stage compilation, the process proceeds to step 204, where optimization processing for the cache is performed. The cache optimization processing will be described later with reference to FIG. In the code generation process 203, the intermediate code 307 is input, and an object program 309 or 313 described in a machine language or an assembly language is generated. (In the first stage of compilation, the object program 309 for cache simulation is generated, and in the second stage of compilation, the final object program 313 is generated.) Regarding the code generation, similarly, "Eiho, Cessy and Ullman: Compiler II ( Science, 1990) 624
Pages to 707 ", and will not be described in detail here.

FIG. 5 shows an example of the intermediate code of the compiler in the present embodiment. The intermediate code is created by the processing of the syntax analysis 201. The intermediate code in FIG. 5 corresponds to the source program in FIG. The intermediate code in FIG. 5 is represented by a graph in which basic blocks (abbreviated as Basic Block, BB) are connected by edges. (Such a graph is called a control flow graph.) 501 to 507 are basic blocks. These basic blocks are numbered BB1 to BB7, respectively. The basic block does not branch or jump in the middle,
It represents a series of code strings. Edges (arrows) represent transitions between basic blocks. For example, basic block 5
Since an edge is set from 01 to 502, control is transferred to 502 after 501 ends. The method of analyzing the basic block and the method of constructing the control flow graph are described in the previous book (Compiler II), pp. 642-648, and will not be described in detail here. What is written in each basic block is an executable statement, which is executed when control is transferred to the basic block. However, some executable statements are not explicitly shown in the source program. For example, the last sentence “I” in BB5 (505)
= I + 1 "is not present in the source program, but is added by the compiler to represent the meaning of the source program. Each executable statement in the basic block is given a unique number (executable statement number) by the compiler. This is shown in [] on the left side of each executable statement. Here, since only one memory reference appears in one sentence, the corresponding memory reference is uniquely determined by the execution statement number.

FIG. 6 shows a simulation code insertion process 2
13 is a flowchart showing the flow of the second embodiment. First, in step 601, an unprocessed executable statement in the intermediate code is extracted. If there is no unprocessed executable statement, the process proceeds to step 604.
In step 602, it is checked whether the extracted execution statement is a memory reference statement. The memory reference statement is, for example, a statement including an array element reference. If it is a memory reference statement, in step 603, a function call statement called sim (memory address, execution statement number) is created and inserted immediately before the execution statement currently being processed. Here, “memory address” is an expression representing the address of the memory to be referred to. Function si
m () is a library function prepared by the compiler to simulate cache operation. The operation will be described later with reference to FIG. Finally step 6
At 04, a cache simulation initialization function is inserted at the beginning of the program, and a cache simulation result output function is inserted at the end of the program. These functions and the function sim () are all included in the cache simulation library 307.

FIG. 7 shows the intermediate code after the simulation code insertion processing. In FIG. 7, since the execution statement numbers 4, 5, and 7 have memory references "B (I)", "C (I)", and "A (I, J)", the simulation code is inserted immediately before these statements. Have been. For example, a sentence “sim (& B (I), 4)” is inserted before the execution sentence 4. Here, “& B (I)” is an expression representing the address of array element B (I). Similarly, before execution statement 5, "sim (& C (I),
The statement "5)" is preceded by executable statement 7 with "sim (& A (I, J), 7)"
Is inserted.

FIG. 8 is a diagram schematically showing the operation of the function sim (). Hereinafter, this function is referred to as a cache simulator for convenience. The cache simulator operates when the cache simulation load module 311 is executed. Cache simulator 801
Is roughly divided into the control unit 802 and the cache table 8
03, a cache miss rate recording table 804.
The inputs to the cache simulator are the memory address 805 and the execution statement number 806. (This corresponds to the two arguments of the function sim.) The cache model table 803 is a software simulation of an actual cache. The control unit 802 checks, based on the given memory address, whether the address exists in the cache (whether or not there is a cache hit) by using a cache model table. The contents of the table are changed, and the result is recorded in the cache miss rate recording table 8.
Register in 04. When registering, use the executable statement number,
It is recorded in the entry corresponding to the executable statement number. The cache model table and the cache miss rate recording table are initialized when the cache simulation initialization function is executed (at the beginning of the program). Also, the contents of the cache miss rate recording table are at the time of execution of the cache simulation result output function (at the end of the program).
Output to the cache miss rate recording file 313. For a method of performing cache simulation using a cache model table or the like, see, for example, `` TMConte, C.
E. Gimac: Fast Simulation of Computer Architectur
e, pp87-108, Kluwer, 1995 "
It will not be described in detail here.

FIG. 9 shows a cache miss rate recording table 80.
6 is a diagram showing (example of) the contents of FIG. The cache miss rate record table includes an execution statement number 901 and an access count 90
2, five fields of cache hit count 903, cache miss count 904, and cache miss rate 905. The execution statement number 901 indicates the number of an execution statement having a memory reference. The access count 902 indicates the number of memory references, which is the sum of the cache hit count 903 and the cache miss count 905 (accordingly, 902 to 9).
04 can be omitted because one can be calculated from the other). The cache miss ratio 905 indicates “the number of cache misses / the number of accesses” (this can also be calculated from other sources and can be omitted). The contents of the cache miss rate recording file 313 have the same configuration as the cache miss rate table 804.

FIG. 10 shows a cache optimization process 204.
5 is a flowchart showing the flow of the process. In the present embodiment, it is assumed that software prefetch is performed as optimization processing for cache. First, in step 1001, it is checked whether there is any unprocessed executable statement in the intermediate code. If there is no unprocessed executable statement, the process ends. Step 1002 checks whether it is a memory reference. If it is a memory reference statement, it is checked in step 1003 whether there is an entry corresponding to the executable statement from the cache miss rate recording file. If there is no entry, it means that the executable statement has not been executed, so skip to step 1001.
Proceed to. If there is an entry, in step 1004, the cache miss rate of the execution statement is extracted, and it is checked whether or not it is equal to or more than a predetermined value. If the cache miss rate is equal to or more than a certain value, it means that the memory is to be referenced for the effect of cache optimization.

FIG. 11 shows an intermediate language obtained by performing software prefetch optimization based on the input intermediate code of FIG. 5 and the data of the cache miss rate recording file of FIG. In the program of FIG. 5, 3 of executable statement numbers 4, 5, and 7
Although there is a memory reference at a location, it can be seen from the cache miss rate recording file that the corresponding cache miss rates are 0.19%, 0.19%, and 25.0%, respectively.
Here, assuming that the cache optimization is performed only for the reference having the cache miss rate of 3% or more, the prefetch instruction may be inserted only for the memory reference of the executable statement 7. 12, an execution statement 10 “prefetch (& A (I + 3, J)” ”, which is a prefetch instruction for the execution statement 7, is newly inserted. "Bernstein et al .: Compile
r Techniques for Data Prefetching on the PowerPC,
PACT '95, 1995, pp. 19-26 "and will not be described here in detail.

In this embodiment, the configuration of the compiler that performs software prefetching as optimization for the cache has been described. However, the present invention is not limited to this configuration. The same can be applied to the conversion.
In the present invention, the cache miss rate recording file mainly records only the cache miss rate. In addition to this, the present invention is applied by recording the type of the cache miss (initial miss, capacity miss, contention miss). It is also possible to select more finely the cache optimization.

[0027]

According to the present invention, even for a program in which the cache miss rate cannot be predicted by the static analysis, the cache miss rate for each data access in the program is obtained more accurately, and the program is used by the compiler by utilizing the same. It is possible to perform efficient optimization for cache without waste.

[Brief description of the drawings]

FIG. 1 shows a procedure of a compile process by a user.

FIG. 2 shows a flow of processing of a compiler.

FIG. 3 is a configuration diagram of a computer system.

FIG. 4 is an example of a source program.

FIG. 5 is an example of an intermediate code.

FIG. 6 is a flowchart of a cache simulation code embedding process.

FIG. 7 shows an intermediate code after a cache simulation code is inserted.

FIG. 8 is an operation model diagram of a cache simulation function sim.

FIG. 9 is a cache miss rate recording table.

FIG. 10 shows a flow of a cache optimization process.

FIG. 11 shows an intermediate code after a cache optimization process.

[Explanation of symbols]

301: CPU, 302: Main storage device, 3
03: external storage device, 304: display device, 30
5 ... Keyboard.

Claims (7)

[Claims] An optimization method for a cache in a compiler, the method comprising: determining whether compilation is a first-stage compilation; and determining a memory reference in a program when the compilation is a first-stage compilation. A step of inserting a code for performing a cache simulation on the other hand, and a step of performing optimization for a cache with respect to a memory reference in a program at the time of the second stage compilation. And performing a process using the cache characteristic data in the memory reference. 2. The cache optimizing method according to claim 1, wherein said cache characteristic data includes a cache miss rate. 3. The cache optimizing method according to claim 1, wherein said cache characteristic data includes a type of a cache miss. 4. The cache optimizing method according to claim 1, wherein said cache characteristic data includes information indicating to which reference in the program the data is. Optimization method. 5. The optimization method for a cache according to claim 1, wherein said optimization for a cache performs software prefetch. 6. A compiler using the cache optimization method according to claim 1. 7. A storage medium storing the compiler according to claim 6.