JPH10132906A - Method and device for designing test pattern for verification - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and a device for designing a test pattern for verification in which the test pattern can efficiently be entered. SOLUTION: The device comprises an output device 1 which displays input data from an input device 2 and a designed test pattern, a data storage device 4 which stores created test pattern data 41, the input device 2, an arithmetic processing unit 3 which designs a test pattern based on various information from the data storage device 4 and various directions from a test pattern generator 5 and outputs the designing results, and the test pattern generator 5. The test pattern generator 5 is a software composed of an input controlling program 51, a display controlling program 52, a flowchart input program 53, a clock signal input program 54, and a signal input program 55, a test pattern reading program 56, and a test pattern storage program 57. The processing unit 3 executes this software to design a test pattern, and displays a flowchart.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for designing a test pattern for verification, and more particularly to a method and apparatus for designing a test pattern for designing a test pattern for verifying a circuit operation of an electronic circuit.

[0002]

2. Description of the Related Art As an example of a conventional test pattern design method for verification, a "test pattern design method for verification" described in Japanese Patent Application No. 7-23558 can be cited.

FIG. 5 is a diagram showing a general test pattern in a time chart. FIG. 6 is a diagram showing an example of a test pattern design screen by a flow chart input method of a conventional test pattern design method for verification.

In the test pattern design method based on the flowchart input method shown in FIG. 6, with respect to the test pattern shown in the time chart of FIG. 5, a certain time is regarded as one pattern, and a signal is supplied to each terminal synchronized in pattern units. The signal can be easily and efficiently input by means of a control flow with pattern repetition and regular test patterns.

[0005] In addition, by expressing the test pattern in a flowchart, the test contents and the flow of the order can be visually recognized, so that it is easy to understand.

[0006]

The conventional test pattern design method based on the flowchart input method has a feature that only a changing signal is input. However, a signal repeated at the same cycle, for example, a clock signal is frequently input. However, since the state value of the signal changes, the number of inputs in the flowchart increases, and the input efficiency of the test pattern decreases.

An object of the present invention is to set a signal, such as a clock signal, in which a change in the state value of the signal is repeated at the same cycle as a clock signal separately from the flow chart input,
An object of the present invention is to provide a test pattern design method for verification and a test pattern design method capable of efficiently inputting a test pattern by controlling the generation of a pulse of the signal using a keyword in the signal input of the flowchart. .

[0008]

According to the present invention, when designing a test pattern for verifying a circuit operation of an electronic circuit, a signal input instruction is given to each terminal of the electronic circuit.
The arithmetic processing of the test pattern design is performed by various instructions for generating the test pattern according to the input instruction, and the flowchart of the test pattern as the processing result is output and displayed, and the change of the state value of the signal is repeated at the same cycle. A signal to be output is set as a clock signal separately from the signal input in the flowchart, and control of generation of a pulse of the clock signal is performed using a keyword in the signal input in the flowchart, and a verification test pattern design method is provided. Is obtained.

Further, according to the present invention, there is provided a verification test pattern designing apparatus for designing a test pattern for verifying a circuit operation of an electronic circuit, wherein an input for giving a signal input instruction to each terminal of the electronic circuit is provided. An apparatus, a test pattern creating means for performing test pattern creation control in accordance with the input instruction input from the input device, an arithmetic processing apparatus for performing arithmetic processing of test pattern design in accordance with various commands from the test pattern creating means, An output device for outputting and displaying a flow chart of the test pattern, which is a processing result of the processing device; and a data storage device for storing the generated test pattern data, wherein the test pattern generation unit has the same cycle as the output device. Clock signal input means for setting a signal name of a signal whose signal changes repeatedly at and a cycle of the signal change A verification test pattern design apparatus characterized by comprising: an input control means for controlling various means corresponding to an input instruction from the input device; anda test pattern creation means, Screen display control means for displaying information including signals and graphics, flowchart input means for inputting graphics information selected from a template menu on a test pattern design screen to a flowchart of a test pattern to be displayed, and the input control means Signal input means for creating signal information to be displayed from a signal of the input instruction, test pattern reading means for reading test pattern data already created, and test pattern storage means for saving the input test pattern data, The screen display control means displays a test pattern design screen on the output device. The input control means receives an input instruction from the input device, and when there is already generated test pattern data in the data storage device, the test pattern reading means reads the test pattern data from the data storage device. When the test pattern data is displayed in a flow chart on the test pattern input screen in a flow chart, and the signal that repeats the change of the signal at the same cycle is set, the clock signal input means sends a clock signal definition screen to the output device by a clock signal input instruction. Displaying, after the input device has finished inputting the terminal name, signal polarity and clock pulse type on the clock signal definition screen, the clock signal input means erases the clock signal definition screen. A test pattern design device for the A verification test pattern design apparatus, wherein the creation means is composed entirely of software, and the arithmetic processing unit executes and processes the software to design the test pattern and display the flowchart on the output unit. Is obtained.

When a new test pattern is input, the screen display control means identifies the flow chart figure and selects "Signal substitution" from the template menu of the test pattern design screen. A "Signal substitution" graphic is displayed in the flow chart of the test pattern input screen, and when a signal or a conditional expression to be substituted is input from the input device in the graphic, a signal or condition designated by a keyboard by the signal input means. When an expression is input, the screen display control means displays a signal or a conditional expression in a flowchart graphic, the test pattern storage means stores the input test pattern data of the flowchart, and when this input is completed, Test pattern design equipment for verifying that test pattern design screen is erased It is obtained.

[0011]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a test pattern design apparatus for verification of the present invention, FIG. 2 is a flowchart showing the flow of processing in this embodiment, and FIG. 3 is an example of an input test pattern in this embodiment. FIG. 4 is a diagram showing a clock signal set in the present embodiment.

Referring to FIG. 1, a test pattern design apparatus for verification according to the present embodiment includes an input device 2 that allows a designer to operate a keyboard, a mouse, or the like to issue an input instruction, and a result input from the input device 2. An output device 1 for displaying various information including a display of a designed and designed test pattern on a display, a data storage device 4 for storing created test pattern data 41, a test pattern creating means 5,
An arithmetic processing unit 3 for performing arithmetic processing of test pattern design in accordance with various information from the input device 2 and various data from the data storage device 4 and various instructions from the test pattern creating means 5 and outputting an arithmetic processing result to the output device 1; I have.

The test pattern creating means 5 is all composed of software (program), and the software is executed and processed by the arithmetic processing unit 3 to design a test pattern and a flowchart is displayed.

That is, the test pattern creating means 5 in the present embodiment includes an input control means 51 for controlling various means corresponding to an input instruction given from the input device 2 to each terminal of the electronic circuit, and a test pattern input screen. Screen display control means 52 for displaying information including signals and figures, a flow chart input means 53 for inputting figure information selected from a template menu of a test pattern design screen to a flow chart of a test pattern to be displayed, and an input control means 51 Signal input means 55 for creating signal information to be displayed from the signal of the input instruction received in step (1), and test pattern reading means 56 for reading the already created test pattern data.
Test pattern storage means 57 for storing the input test pattern data, and these respective means 52, 53, 55, 5
6 and 57 are provided with a clock signal input means 54 for setting the signal name of the signal repeated at the same cycle through the input control means 51 and the cycle of the signal change.

Next, the operation of this embodiment will be described with reference to FIGS.
This will be described with reference to FIGS. 2, 3 and 4.

The screen display control means 52 displays the test pattern design screen G1 shown in FIG. 3 on the display of the output device 1 (step S10).

Next, the input control means 51 receives an input instruction from a keyboard, a mouse or the like of the input device 2 (step S20).

Here, when the test pattern data 41 already created exists in the data storage device 4, the test pattern reading means 56 reads the test pattern data 41 from the data storage device 4 (step S50) and displays the screen. The control means 52 performs a test pattern input screen G shown in FIG.
2, the test pattern data is displayed in a flowchart (step S82).

Further, in order to set a signal that repeats a signal change at the same cycle, the clock signal input means 54 causes the output device 1 to display a clock signal definition screen G4 shown in FIG. 4 in response to a clock signal input instruction (step S90). ).

On the clock signal definition screen G4, the terminal name, signal polarity, and clock pulse type are input from the keyboard in the input device 2 (step S91). After the input is completed, the clock signal input means 54 sets the clock signal definition. The screen G4 is erased (Step S92).

In FIG. 5, the positive polarity pulse A and the negative polarity pulse A 'represent the opposite pulses depending on the polarity of the clock signal. Further, as shown in FIG. 4, two different pulses A and B are represented by the clock pulse type.

To input a new test pattern, a flowchart figure is identified and a flowchart input means 53 is entered.
Is the template menu G on the test pattern design screen G1
When "Signal substitution" is selected from Step 3 (Step S30),
The screen display control means 52 displays a "signal substitution" graphic in the flowchart of the test pattern input screen G2 (step S80).

When a terminal name and a signal or conditional expression to be substituted in the figure are input from the keyboard in the input device 2 (step S40), a signal or conditional expression specified by the keyboard is input by the signal input means 55, and the screen is displayed. The display control means 52 displays a signal or a conditional expression in the flowchart figure (step S81).

Note that, as shown in FIG.
When a pattern of a regular increment of a signal is input to the (0 to 7) terminal, the increment is defined by looping the flow of the flowchart.

When inputting the clock pattern of the clk terminal, instead of the signal to be substituted for the signal name in the "signal substitution" figure in the flowchart, the "keyword" st
Assign "art". Conversely, when stopping the clock pattern, "keyword" stop is substituted for the signal substituted for the signal name in the "signal substitution" figure in the flowchart.

The test pattern storage means 57 stores the test pattern data of the input flowchart (step S60). Further, when the input of the test pattern is completed, the test pattern design screen G1 is erased (step S7).
0).

[0028]

As described above, the verification test pattern designing method of the present invention provides a method for designing a test pattern for verifying the circuit operation of an electronic circuit, in which a signal input instruction is input to each terminal of the electronic circuit. The test pattern design calculation processing is performed according to various instructions for test pattern creation in accordance with the input instruction, and a flow chart of the test pattern, which is the processing result, is output and displayed. The repeated signal is set as a clock signal separately from the signal input in the flowchart, and the generation of the pulse of the clock signal is controlled by using a keyword in the signal input in the flowchart. The design device is a test pattern design device for verification for designing a test pattern for verifying a circuit operation of an electronic circuit. An input device for giving a signal input instruction to each terminal of the electronic circuit, a test pattern creating means for performing test pattern creation control in accordance with the input instruction input from the input device, and a test pattern design by various instructions from the test pattern creating means An arithmetic processing device for performing the arithmetic processing of the above, an output device for outputting and displaying a flowchart of a test pattern which is a processing result of the arithmetic processing device, and a data storage device for storing the created test pattern data. The pattern generating means further comprises a clock signal input means for setting a signal name of a signal in which a signal change is repeated at the same cycle and a clock signal changing cycle in the output device. Input control means for controlling various means corresponding to input instructions from the apparatus, and a test pattern input screen Screen display control means for displaying information including signals and graphics, flowchart input means for inputting graphic information selected from a template menu of a test pattern design screen to a flowchart of a test pattern to be displayed, and input received by the input control means A screen display comprising signal input means for creating signal information to be displayed from an instruction signal, test pattern reading means for reading already created test pattern data, and test pattern storage means for saving the inputted test pattern data The control means causes a test pattern design screen to be displayed on the output device, the input control means accepts an input instruction from the input device, and the test pattern reading means stores data when there is already created test pattern data in the data storage device. Read test pattern data from the device When the test pattern data is displayed in a flow chart on the input input screen, and a signal that repeats a signal change at the same cycle is set, the clock signal input means causes the output device to display the clock signal definition screen in response to the clock signal input instruction. After inputting the terminal name, signal polarity, and clock pulse type on the clock signal definition screen, the clock signal input means erases the clock signal definition screen, and the test pattern creation means is all software. A test pattern is designed by the execution processing of the software by the arithmetic processing unit, and a flowchart is displayed on the output device. As a result, a signal such as a clock signal whose signal is repeatedly changed at the same cycle is output once. This can be done by signal input and It is possible to control the generation and Kuparusu and stopping, becomes easier input of a signal which the signal change at the same period is repeated, the creation efficiency of the test pattern has the effect of remarkably improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a test pattern design method for verification of the present invention.

FIG. 2 is a flowchart illustrating a flow of a process according to the embodiment.

FIG. 3 is a diagram illustrating an example of an input test pattern according to the embodiment.

FIG. 4 is a diagram showing a clock signal set in the embodiment.

FIG. 5 is a diagram showing a general test pattern in a time chart.

FIG. 6 is a diagram showing a test pattern design screen by a flowchart input method as an example of a conventional test pattern design method for verification.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Output device 2 Input device 3 Arithmetic processing unit 4 Data storage device 5 Test pattern creation means 41 Test pattern data 51 Input control means 52 Screen display control means 53 Flow chart input means 54 Clock signal input means 55 Signal input means 56 Test pattern reading means 57 Test pattern storage means G1 Test pattern design screen G2 Test pattern input screen G3 Template menu G4 Clock signal definition screen

Claims (5)

[Claims] When designing a test pattern for verifying a circuit operation of an electronic circuit, an input instruction of a signal is given to each terminal of the electronic circuit, and various types of test patterns are created in accordance with the input instruction. The test pattern design arithmetic processing is performed according to the instruction, and a flowchart of the test pattern, which is the processing result, is displayed and displayed. And controlling the generation of a pulse of the clock signal using a keyword at the signal input of the flowchart. 2. A test pattern design apparatus for designing a test pattern for verifying a circuit operation of an electronic circuit, comprising: an input device for giving a signal input instruction to each terminal of the electronic circuit; A test pattern creating means for performing test pattern creation control in accordance with the input instruction input from, and an arithmetic processing device for performing arithmetic processing of test pattern design by various instructions from the test pattern creating means;
An output device that outputs and displays a flowchart of the test pattern, which is a processing result of the arithmetic processing device; and a data storage device that stores the created test pattern data. A test pattern design device for verification, comprising: clock signal input means for setting a signal name of a signal in which a signal change is repeated at the same cycle and a cycle of the signal change. 3. The test pattern creation means for controlling various means corresponding to an input instruction from the input device, and a screen display control means for displaying information including signals and graphics on a test pattern input screen. A flow chart input means for inputting graphic information selected from a template menu of a test pattern design screen into a flow chart of a test pattern to be displayed, and signal information to be displayed is generated from an input instruction signal received by the input control means. Signal input means, test pattern reading means for reading already generated test pattern data, and test pattern storage means for storing the input test pattern data, wherein the screen display control means displays a test pattern design screen on the output device. And the input control means receives an input instruction from the input device. When test pattern data already created exists in the data storage device, the test pattern reading means reads the test pattern data from the data storage device and displays the test pattern data on a test pattern input screen in a flowchart. When setting the signal that repeats a signal change at the same cycle, the clock signal input means causes the output device to display a clock signal definition screen in response to a clock signal input instruction, and the input device outputs a terminal to the clock signal definition screen. 3. The test pattern design apparatus for verification according to claim 2, wherein the clock signal input means erases the clock signal definition screen after the input of the name, the polarity of the signal, and the clock pulse type is completed. 4. The test pattern creation means is entirely composed of software, and the software is executed and processed by the arithmetic processing unit, whereby the test pattern is designed and the flowchart is displayed on the output device. 3. The verification test pattern designing apparatus according to claim 2, wherein 5. When inputting a new test pattern,
When the flowchart input is identified and the flow chart input means selects "signal assignment" from the template menu of the test pattern design screen, the screen display control means displays the "signal assignment" graphic in the flowchart of the test pattern input screen. Then, when a signal or a conditional expression to be substituted for a terminal name is input from the input device in the graphic, a signal or a conditional expression designated by a keyboard is input by the signal inputting means, and the screen display control means enters the flowchart graphic in the flowchart graphic. 3. A signal or a conditional expression is displayed, said test pattern storage means stores said input test pattern data of said flowchart, and when said input is completed, said test pattern design screen is erased. The described test pattern design device for verification.