CN114002583A - Pattern editing tool and method based on integrated circuit automatic test system - Google Patents
Pattern editing tool and method based on integrated circuit automatic test system Download PDFInfo
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- CN114002583A CN114002583A CN202111289225.XA CN202111289225A CN114002583A CN 114002583 A CN114002583 A CN 114002583A CN 202111289225 A CN202111289225 A CN 202111289225A CN 114002583 A CN114002583 A CN 114002583A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2868—Complete testing stations; systems; procedures; software aspects
- G01R31/287—Procedures; Software aspects
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Abstract
The invention relates to the integrated circuit automatic test industry, in particular to a pattern editing tool and a method based on an integrated circuit automatic test system. This instrument includes: the device comprises a window segmentation module and a control module; the window segmentation module is used for setting a first display window, a second display window and a third display window on the editing interface of the pattern; the control module is used for reading the pattern file and displaying the pin information in the pattern file in a first display window in a row, wherein each group of pin information is a row; displaying the pattern data in the pattern file in a second display window according to lines; and displaying the waveform of the line pattern data or a plurality of lines of pattern data including the line in a third window according to the selected line in the second display window. The tool optimizes the display mode of the chip pattern, adds a visual waveform picture to visually display the time sequence content of the pattern, has better readability, and greatly improves the working efficiency of chip test developers.
Description
Technical Field
The invention relates to the integrated circuit automatic test industry, in particular to a pattern editing tool and a method based on an integrated circuit automatic test system.
Background
In the Test link of chip research and development and mass production, a Pattern editing tool (Pattern Editor Tools) is provided, wherein a Pattern represents the time sequence characteristics of the chip function, namely, in the process of chip Test, an Automatic Test Equipment (ATE) of an integrated circuit sends a series of time sequences to an input pin of a chip to be tested, and an output pin of the chip compares the output time sequences, so that whether the chip meets the functions of the chip is tested. To some extent, the test pattern is the truth table of the chip.
When a pattern editor commonly used in the market is used for pattern editing, each digit of a pattern always needs to be in one-to-one correspondence with a longitudinal pin name and a pin number, but the display mode easily causes visual confusion when pattern data is large, and the pattern can only be represented by symbols such as 0, 1, H and L …, so that the timing sequence represented by the pattern and the content of the pattern test cannot be easily and intuitively seen, as shown in fig. 1. In the debugging process of chip testing, if a tester needs to read and change the pattern, some difficulties are brought.
Disclosure of Invention
In view of the above-mentioned defects of the prior art, an object of the present invention is to provide a pattern editing tool based on an automatic test system for integrated circuits, which provides better display and editing modes, thereby improving the work efficiency of testers; the second objective of the present invention is to provide a pattern editing method based on an automatic test system of an integrated circuit, which provides better display and editing modes, thereby improving the working efficiency of testers.
To achieve the first objective of the present invention, the present invention provides a pattern editing tool based on an automatic test system of an integrated circuit, comprising: the device comprises a window segmentation module and a control module;
the window segmentation module is used for setting a first display window, a second display window and a third display window on an editing interface of the pattern;
the control module is used for reading the pattern file and displaying the pin information in the pattern file in a first display window in a row, wherein each group of pin information is a row; displaying the pattern data in the pattern file in a second display window according to lines; and displaying the waveform of the line pattern data or a plurality of lines of pattern data including the line in a third window according to the selected line in the second display window.
Further, the first display window is arranged on the left of the editing interface, the second display window is arranged below the editing interface, and the third display window is arranged above the editing interface.
Further, the first display window is arranged on the left of the editing interface, the second display window is arranged above the editing interface, and the third display window is arranged below the editing interface.
Furthermore, the first display window is arranged on the left side of the editing interface, the second display window is arranged on the right side of the editing interface, and the third display window is a floating window and is arranged at any position of the editing interface in a floating mode.
To achieve the second objective of the present invention, the present invention provides a pattern editing method based on an automatic test system of an integrated circuit, comprising:
reading a chip pattern file;
displaying the pin information in the pattern file on a first display window line by line according to the reading sequence, wherein each group of pin information displays one line;
displaying the pattern data in the pattern file on a second display window line by line according to the reading sequence, and enabling the pattern data and the pin information in the same line of the editing interface to be related data, namely enabling the line of pattern data to be the pattern data of the pin of the line;
and generating corresponding waveforms for the line pattern data or a plurality of lines of pattern data including the line according to the selected line in the second display window, and displaying the waveforms in a third display window.
Further, the pin information includes: pin name and pin number.
Further, each row of the third display window displays a waveform of a line of pattern data.
Furthermore, the third display window is divided into a plurality of groups and is used for simultaneously displaying the data waveform after the multi-line pattern data are fused.
Further, when the third display window displays waveforms, pin information corresponding to each waveform information is displayed before each waveform information.
Further, the method for editing the pattern further comprises: and storing the waveform of the third window as a simulation pattern.
The invention realizes the following technical effects:
the pattern editing tool provided by the invention optimizes the display mode of the chip pattern, provides a new display mode, and adds a visual waveform picture to visually display the time sequence content of the pattern, so that the pattern can be displayed more visually. Therefore, the system has extremely high value in the development process of the chip test program, and brings great convenience to chip development and test personnel.
Drawings
FIG. 1 is an editing interface of a conventional pattern editing tool;
FIG. 2 is a diagram of a first form of a pattern editing tool editing interface according to the present invention;
FIG. 3 is a diagram of a second form of a graphical editing tool editing interface in accordance with the present invention;
fig. 4 is a schematic diagram of a third form of the editing interface of the pattern editing tool of the present invention.
Detailed Description
To further illustrate the various embodiments, the invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. Those skilled in the art will appreciate still other possible embodiments and advantages of the present invention with reference to these figures. Elements in the figures are not drawn to scale and like reference numerals are generally used to indicate like elements.
The invention will now be further described with reference to the accompanying drawings and detailed description.
As shown in fig. 2, 3 and 4, the present invention provides a pattern editing tool based on an automatic test system of an integrated circuit, which resets the layout of an editing interface, and a virtual window segmentation module is considered to set a pin name and pin number display area 101, a pattern display area 102 and a waveform display area 103 on the editing interface; the control module of the pattern editing tool executes the following operations:
reading a chip pattern file, and storing the pattern content in a memory according to rows; displaying the pin information in the pattern file in a pin name and pin sequence number display area 101 according to a row, wherein each group of pin information is a row; displaying the pattern data in the pattern file in the pattern display area 102 according to lines; according to the selected row of the pattern display area 102, the waveform of the row pattern data or a plurality of rows of pattern data including the row is displayed in the waveform display area 103.
In this embodiment, various preferred layouts of the editing interface are given.
(1) A pin name and pin number display area 101 is provided on the left side of the editing interface, a pattern display area 102 is provided below the editing interface, and a waveform display area 103 is provided above the editing interface.
(2) A pin name and pin number display area 101 is provided on the left side of the editing interface, a pattern display area 102 is provided above the editing interface, and a waveform display area 103 is provided below the editing interface.
(3) The pin name and pin number display area 101 is arranged at the left side of the editing interface, the pattern display area 102 is arranged at the right side of the editing interface, and the waveform display area 103 is arranged in a floating window and can be arranged at any position of the editing interface in a floating mode.
The invention also provides a chip pattern display method, which comprises the following steps:
(1) reading a chip pattern file;
(2) displaying the pin information in the pattern file on the pin name and pin number display area 101 line by line according to the reading sequence, wherein each group of pin information displays one line;
(3) displaying the pattern data in the pattern file in the pattern display area 102 line by line according to the reading sequence, and enabling the pattern data and the pin information displayed in the same line of the editing interface to be related data, namely enabling the line of pattern data to be the pattern data of the line of pins;
(4) according to the selected row in the pattern display area 102, the corresponding waveform is generated from the row pattern data or the plurality of rows of pattern data including the row, and is displayed in the waveform display area 103. When the selection operation is not performed, the pattern editing tool designates a certain row of the pattern display area 102 as the selected row by default.
The development tester can easily and intuitively see the simulation pattern which can be generated by the pattern data through the waveform of the waveform display area 103 and the pattern data in the pattern display area 102, and can save the simulation pattern as a standard pattern which is compared with the pattern generated when the chip test is formally carried out.
When a development tester adds or modifies a pattern, the pattern editing tool immediately re-reads the pattern data in the pattern display area 102, converts it into a waveform, and synchronously displays the modified waveform in the waveform display area 103.
The pattern editing tool also provides a function of fusing multiple lines of pattern data into a group to display when more pins are available, namely, waveforms of the multiple lines of pattern data are fused into a data waveform to be displayed in the waveform display area 103, and the function can be used for displaying complex pattern data.
To facilitate the correspondence between the waveform and the pin, the pin information corresponding to the pattern data may be displayed before the waveform of the pattern data in the waveform display area 103.
The pattern editing tool provided by the invention optimizes the display mode of the chip pattern, provides a new display mode, adds a visual waveform picture to visually display the time sequence content of the pattern, thereby enabling the pattern to be displayed more visually. Therefore, the system has extremely high value in the development process of the chip test program, and brings great convenience to chip development and test personnel.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A pattern editing tool based on an integrated circuit automatic test system, comprising: the device comprises a window segmentation module and a control module;
the window segmentation module is used for setting a first display window, a second display window and a third display window on an editing interface of the pattern;
the control module is used for reading the pattern file and displaying the pin information in the pattern file in a first display window in a row, wherein each group of pin information is a row; displaying the pattern data in the pattern file in a second display window according to lines; and displaying the waveform of the line pattern data or a plurality of lines of pattern data including the line in a third window according to the selected line in the second display window.
2. The pattern editing tool of claim 1, wherein the first display window is disposed to the left of the editing interface, the second display window is disposed below the editing interface, and the third display window is disposed above the editing interface.
3. The pattern editing tool of claim 1, wherein the first display window is disposed to the left of the editing interface, the second display window is disposed above the editing interface, and the third display window is disposed below the editing interface.
4. The pattern editing tool according to claim 1, wherein the first display window is disposed at the left of the editing interface, the second display window is disposed at the right of the editing interface, and the third display window is a floating window disposed at an arbitrary position of the editing interface in a floating manner.
5. A pattern editing method based on an automatic test system of an integrated circuit is characterized by comprising the following steps:
reading a chip pattern file;
displaying the pin information in the pattern file on a first display window line by line according to the reading sequence, wherein each group of pin information displays one line;
displaying the pattern data in the pattern file on a second display window line by line according to the reading sequence, and enabling the pattern data and the pin information in the same line of the editing interface to be related data, namely enabling the line of pattern data to be the pattern data of the pin of the line;
and generating corresponding waveforms for the line pattern data or a plurality of lines of pattern data including the line according to the selected line in the second display window, and displaying the waveforms in a third display window.
6. The pattern editing method according to claim 5, wherein the pin information includes: pin name and pin number.
7. The pattern editing method according to claim 5, wherein each line of the third display window displays a waveform of one line of pattern data.
8. The method for pattern editing according to claim 5, wherein the third display window is divided into a plurality of groups for simultaneously displaying a plurality of rows of the data waveforms after pattern data fusion.
9. The pattern editing method according to claim 5, wherein the third display window displays the pin information corresponding to each waveform information before the waveform information when displaying the waveform.
10. The pattern editing method according to claim 5, further comprising: and storing the waveform of the third window as a simulation pattern.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111289225.XA CN114002583A (en) | 2021-11-02 | 2021-11-02 | Pattern editing tool and method based on integrated circuit automatic test system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111289225.XA CN114002583A (en) | 2021-11-02 | 2021-11-02 | Pattern editing tool and method based on integrated circuit automatic test system |
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| CN114002583A true CN114002583A (en) | 2022-02-01 |
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| CN202111289225.XA Pending CN114002583A (en) | 2021-11-02 | 2021-11-02 | Pattern editing tool and method based on integrated circuit automatic test system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116580757A (en) * | 2023-07-12 | 2023-08-11 | 悦芯科技股份有限公司 | Virtual ATE test method and system |
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| JPS6478166A (en) * | 1987-09-18 | 1989-03-23 | Matsushita Electric Ind Co Ltd | Ic tester |
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| JPH0373069A (en) * | 1989-04-26 | 1991-03-28 | Tektronix Inc | Graphic database editor |
| CA2222665A1 (en) * | 1997-11-26 | 1999-05-26 | Mosaid Technologies Incorporated | Graphical editor for defining memory test sequences |
| JPH11195053A (en) * | 1997-12-26 | 1999-07-21 | Nec Eng Ltd | Test pattern generating device |
| JPH11344543A (en) * | 1998-06-03 | 1999-12-14 | Nec Commun Syst Ltd | Device and method for designing test pattern for verification |
| CN104345262A (en) * | 2014-10-27 | 2015-02-11 | 华南农业大学 | Universal circuit board test system |
| CN113553805A (en) * | 2021-07-28 | 2021-10-26 | 珠海泰芯半导体有限公司 | Method and device for converting simulation waveform file, storage medium and automatic test equipment |
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2021
- 2021-11-02 CN CN202111289225.XA patent/CN114002583A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6478166A (en) * | 1987-09-18 | 1989-03-23 | Matsushita Electric Ind Co Ltd | Ic tester |
| JPH01251171A (en) * | 1988-03-31 | 1989-10-06 | Fujitsu Ltd | Test data editing device |
| JPH01251173A (en) * | 1988-03-31 | 1989-10-06 | Fujitsu Ltd | Test data editing device |
| JPH0373069A (en) * | 1989-04-26 | 1991-03-28 | Tektronix Inc | Graphic database editor |
| CA2222665A1 (en) * | 1997-11-26 | 1999-05-26 | Mosaid Technologies Incorporated | Graphical editor for defining memory test sequences |
| JPH11195053A (en) * | 1997-12-26 | 1999-07-21 | Nec Eng Ltd | Test pattern generating device |
| JPH11344543A (en) * | 1998-06-03 | 1999-12-14 | Nec Commun Syst Ltd | Device and method for designing test pattern for verification |
| CN104345262A (en) * | 2014-10-27 | 2015-02-11 | 华南农业大学 | Universal circuit board test system |
| CN113553805A (en) * | 2021-07-28 | 2021-10-26 | 珠海泰芯半导体有限公司 | Method and device for converting simulation waveform file, storage medium and automatic test equipment |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116580757A (en) * | 2023-07-12 | 2023-08-11 | 悦芯科技股份有限公司 | Virtual ATE test method and system |
| CN116580757B (en) * | 2023-07-12 | 2023-09-22 | 悦芯科技股份有限公司 | Virtual ATE test method and system |
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Application publication date: 20220201 |