JPH0468472A - Logical diagram input device - Google Patents

Abstract

PURPOSE:To shorten time for logic inspection by providing an input signal line extraction part, output signal line extraction part, signal information storage part and rule check part so as to find out a fundamental logical design miss on a logical diagram input device. CONSTITUTION:An input signal line extraction part 1 extracts the input signal line name of each element and property to the signal line from a drawing data storage part 8, an output signal line extraction part 2 extracts the output signal line name of each element and the property to the signal line from the drawing data storage part 8, and a signal line information storage part 3 stores the extracted data. A rule check part 4 is equipped with a function to compare the input signal line name with the output signal line name from the data in the signal line information storage part 3 and when the same name can not be detected in the input signal line and the output signal line, it is judged that the direction of the logical element is wrong, and displayed on a logical diagram display part 5 by a message or the like. Thus, time for logic inspection can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic diagram input device for performing logic verification;

[Conventional technology]

FIG. 3 shows a block diagram of the configuration of a conventional logic diagram input device. In the figure, (5) is a logic diagram display section, (6) is a logic diagram input section, (7) is a symbol library section for logic diagram input,
It consists of five elements: (8) a drawing data storage section and (9) a disconnection check section.

Next, the operation will be explained.

The logic diagram input section (5) is composed of a graphic display, and has the function of visually displaying the data input by the logic diagram input section (6).

This logic diagram input section (6) usually includes a mouse, keyboard,
It is composed of a digitizer, etc., and has the function of selecting necessary symbols from the logic diagram input symbol library section (7) and the function of wiring each element on the drawing. Symbol library section for inputting logic diagrams (stores the shapes, functions, etc. of logic elements until July, and provides data to the logic diagram display section (5) and logic diagram input section (6).

The drawing data storage section (8) has a function of storing connection information of the logic drawing data input by the logic diagram input section (6) and displayed by the logic diagram input section (6).

The disconnection check unit (9) receives an execution command from the logic diagram input unit (6), extracts connection information from the drawing data storage unit (8), and detects disconnections (elements whose inputs and outputs are not determined).
It has a function of outputting an oath message to the logic diagram display section (5) if the logic diagram display section (5) detects the problem (or the wiring).

FIG. 2 shows an execution flowchart of logic verification of the logic diagram input device of FIG.

In step 10, a logic diagram is input in the logic diagram input section (6). At this time, logic verification properties are input for each element in the logic diagram.

In step 11, the logic diagram is converted into phase line connection information (hereinafter referred to as a netlist) exclusively for the logic simulator by the logic diagram input symbol library section (7).

Step 12 is to create a test pattern for signal value input (hereinafter referred to as test pattern) which is required at the beginning of the simulation.

A simulation is executed using the nine netlists and test patterns created in steps It and 12 as input data.

In step 13, logical design errors are investigated by comparing the results of step 13 with expected values. If there is no design error, the logic verification ends. If a logical design error is detected, the process advances to step 15.

In step 15, if a logic design error is detected in step 14, the logic diagram is corrected in the logic diagram input section, and logic verification is performed again in the order of steps 11 to 14.

[Problem to be solved by the invention]

The conventional logic diagram input device is configured as described above;
Therefore, since the logic diagram input device does not have a function to discover logic design errors, it does not have a function to discover property design errors for each element, so it may cause errors in setting properties for each element or setting errors in the direction of each element. In order to discover these basic logic design mistakes, it is essential to create a netlist, use the test pattern as input data, and run a simulation, which makes it easy to discover logic design mistakes. Therefore, there is a problem that it takes time to verify the logic. and an output signal line extraction section,
The purpose of the present invention is to shorten logic verification time by providing a signal information storage section and a rule check section to discover basic logic design errors on a logic diagram input device.

[Solve the problem; tth means]

The logic diagram input device according to the present invention includes an input signal line extraction section, an output signal line extraction section, a signal information storage section, and a rule check section.

[Effect]

The logic diagram input device of this invention enables basic logic design mistakes to be discovered on the logic diagram input device.
Logic verification time can be shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration block diagram of a logic diagram input device which is an embodiment of the present invention. In the figure, (1) is an input signal line extraction section, (2) is an output signal line extraction section, and (3) is a signal line extraction section. Information storage section, (4) is the rule check section, (5) is the logic diagram display section, (6) is the logic diagram input section, (7) is the symbol library section for logic diagram input, (August, drawing data storage section , (9) is a disconnection check section, which is composed of nine elements.

The next operation will be explained.

The input signal line extraction unit (1) has a function of extracting the input signal line name of each element and the properties for the signal line from the drawing data storage unit (8), and inputs the input signal data to the signal information storage unit (3). Has a writing function.

The output signal line extraction section (2) has a function of extracting the output signal line name of each element and the properties for the signal line from the drawing data storage section (8), and outputs the output signal data to the signal information storage section (3). Has a writing function.

The signal information storage section (3) has a function of storing data extracted by the signal line extraction section of the input signal line extraction section (1) and the output signal line extraction section (2), and has a function of storing data extracted by the signal line extraction section of the input signal line extraction section (1) and the output signal line extraction section (2).
It has the function of providing data to.

The rule check section (4) has a function of comparing the input signal line name and the output signal line name from the data in the signal information storage section (3), and if the same name cannot be detected for the input signal line and the output signal line. has a function of determining that the direction of a logic element is wrong and displaying it on the logic diagram display section (5) by changing a message or the color of the element on the drawing. In addition, if the same signal line name is detected in the output signal data, it is determined that there is a signal conflict, and the signal strength property is calculated relative to that signal line. If the signal strength properties are the same, it is determined that the signal strength was set incorrectly. Judging that, the logic diagram display section (1)
It has a function to display a message by changing the color of the speed mark on the drawing, etc.

〔Effect of the invention〕

As described above, according to this defense, since basic logic design errors can be discovered on the logic diagram input device, there is an effect that the logic verification time can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a logic diagram input device according to an embodiment of the present invention, FIG. 2 is a logic verification execution flowchart of FIG. 3, and FIG. 3 is a block diagram of a conventional logic diagram input device. . In the figure, (1) is the input signal line extraction section, (
2) is an output signal line extraction section, (3) is a signal information storage section, (
4) is the rule check section, (5) is the logic diagram display section, (6
) indicates a logic diagram input section, (7) a logic diagram input symbol library section, (8) a drawing data storage section, and (9) a disconnection check section. In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A logic diagram input device necessary for logic verification, characterized by comprising an input signal extraction section that performs a rule check for logic verification, an output signal line extraction section, a signal information storage section, and a rule check section. Diagram input device.