JPH06215069A - Device and method for mask pattern generation - Google Patents

Abstract

PURPOSE:To greatly reduce the contradiction between described ROM specifications and actual ROM specifications. CONSTITUTION:The mask pattern generating device is equipped with a ROM coordinate extraction part 11 which extracts ROM coordinate information from chip layout data, a ROM address information reception part 12 which receives ROM address information, and a mask pattern generation part 13 which generates a mask pattern on the basis of the chip layout data, ROM coordinate information extracted by the ROM coordinate extraction part 11, ROM address information received by the ROM address information reception part 12, and ROM data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an RO such as a mask ROM.
The present invention relates to an apparatus and method for generating a mask pattern for manufacturing an LSI chip having M.

[0002]

2. Description of the Related Art FIG. 12 is a functional block diagram of a conventional mask pattern generation device. This mask pattern device includes a ROM layout description section for describing a ROM specification, and a mask pattern generation section for generating a mask pattern based on the chip layout data, the ROM specification, and the ROM data. .

The ROM specification describes the coordinate information and address information about the ROM in a dedicated language.

FIG. 13 shows a ROM written in a specific language.
An example of specifications is shown. In this language example, the coordinate information about the ROM is BASECOOR, PITCHCOO.
It is defined using symbols such as R and DIMENSION.
The address information regarding the ROM is XADDR, Y
It is defined using symbols such as ADDR.

[0005]

As described above, in the conventional technique, the RO is independent of the design of the chip layout.
I was preparing M specifications. Therefore, the operator has to describe the coordinate information and the address information as shown in FIG. 13 by using the dedicated language, which imposes a heavy burden on the operator to learn the dedicated language. Further, there is a problem that the written ROM specifications and the actual ROM specifications may be inconsistent due to a description error in the ROM specifications.

The present invention has been made to solve the above problems, and is a mask that can obtain ROM coordinate information and ROM address information without using a ROM specification written in a dedicated language. An object is to provide a pattern generation device and a generation method.

[0007]

The apparatus of the present invention comprises a first means for extracting ROM coordinate information from chip layout data and a second means for receiving ROM address information.
And means for generating a mask pattern based on the chip layout data, the ROM coordinate information extracted by the first means, the ROM address information received by the second means, and the ROM data. The above object is achieved by this.

Another apparatus of the present invention is a first means for extracting ROM coordinate information from chip layout data,
Second means for extracting ROM address information from the chip layout data, the chip layout data, the ROM coordinate information extracted by the first means,
Means for generating a mask pattern based on the ROM address information and the ROM data received by the second means are provided, thereby achieving the above object.

The method of the present invention comprises a first step for extracting ROM coordinate information from chip layout data,
A second step for receiving ROM address information,
And a step of generating a mask pattern based on the chip layout data, the ROM coordinate information extracted in the first step, the ROM address information received in the second step, and the ROM data. Thus, the above object is achieved.

Another method of the present invention is a first step for extracting ROM coordinate information from chip layout data, a second step for extracting ROM address information from chip layout data, and the chip layout data. , A step of generating a mask pattern based on the ROM coordinate information extracted in the first step, the ROM address information received in the second step, and the ROM data, whereby The purpose is achieved.

[0011]

EXAMPLES Examples of the present invention will be described below.

(First Embodiment) FIG. 1 shows a functional block diagram of a mask pattern generator 1. The mask pattern generation device 1 includes a ROM coordinate extraction unit 11 for extracting ROM coordinate information from chip layout data, and a ROM address information receiving unit 1 for receiving ROM address information.
2, and a mask pattern generation unit 13 for generating a mask pattern based on the chip layout data, the ROM coordinate information, the ROM address information, and the ROM data.

In the present specification, the above-mentioned various data are defined as follows. The ROM has a memory cell array section including a plurality of memory cells and a decoder section including a plurality of decoders.

The chip layout data is data that does not depend on the data to be written in the ROM and is designed in advance as the base layout of the chip. The chip layout data includes, in addition to ROM coordinate information, which will be described later, information regarding a mask overlap check pattern, a chip name pattern, a bank pattern for controlling transistors, and the like.

The ROM coordinate information is the coordinate information required when laying out each of the memory cells forming the memory cell array section and the decoder forming the decoder section on the chip. However, when the memory cell array unit is hierarchically designed using layout cells, the coordinate information of the layout cells is also referred to.

The ROM address information is data for defining the relationship between the address bit of the memory cell and the coordinate of the memory cell. However, if the memory cell array is hierarchically designed using layout cells,
It also refers to data that defines the relationship between the layout cell address bits and the layout cell coordinates.

The ROM data is data for defining the relationship between the address bit of the memory cell and the logical value of the memory cell. That is, the ROM data determines whether a memory cell having a particular address bit value represents "0" or "1".

In order to generate a mask pattern, RO
Obtaining M coordinate information and ROM address information is required. In the conventional mask pattern generation device, such information is given by the ROM specification written in a specific dedicated language. The present invention uses the R
By extracting the OM coordinate information and receiving the ROM address information corresponding to the extracted ROM coordinate information, the ROM coordinate information and the ROM address information are obtained without using the ROM specification written in a specific dedicated language. It made it possible.

FIG. 2 shows an example of the structure of the mask pattern generator 1. The central processing unit (CPU) 2 executes various processes such as a mask pattern generation process described later. The storage device 3 stores the chip layout data file and the ROM data file input to the mask pattern generation device 1 and the mask pattern data file output from the mask pattern generation device 1. Input device 4
Allows the operator to enter data using a device such as a keyboard or mouse, and the display device 5
The processing result and the like by the CPU 2 are displayed.

FIG. 3 is an example showing the structure of a ROM having a capacity of 512 KB. The ROM 30 includes decoders 31, 32,
And a decoder unit including 33 and a layout cell 3
It has a memory cell array portion including 4, 35, and 36.

The memory cell array portion of the ROM 30 is hierarchically designed with the memory cell as a minimum unit. Specifically, the ROM 30 has two layout cells 34. Each layout cell 34 has 4 × 512 layout cells 35, each layout cell 35 has 16 layout cells 36, and each layout cell 36 has 8 memory cells. As a result, the ROM 30 is 2 ×
It has 4 × 512 × 16 × 8 = 524288 memory cells.

Each of the decoders 31, 32, and 33 selectively activates one of the output lines according to an input address bit. As a result, the data bits D0 to D7 are output according to the address bits A0 to A15 input to the ROM 30.

FIG. 4 shows an example of ROM coordinate information included in the chip layout data stored in the storage device 3. In this example, the ROM coordinate information 40 is the ROM 3 described above.
0 corresponds to the layout cell 34, and the ROM coordinate information 41 corresponds to the layout cell 35.

As shown in FIG. 4, for each layout cell, the layout cell name 42, origin coordinates 43,
The pitch width 44 and the number of repetitions 45 are stored. The origin coordinate 43 indicates the displacement in the X-axis direction and the displacement in the Y-axis direction from the upper layout cell. The pitch width 44 indicates an arrangement interval in the X-axis direction and an arrangement interval in the Y-axis direction of layout cells. The repetition number 45 indicates how many layout cells are arranged in each of the X-axis direction and the Y-axis direction.
The directions of the X axis and the Y axis are as shown in FIG.

For example, the origin coordinate of the layout cell with the name "ROM2" is (0, 0), and the pitch width is (594,
6) and the number of repetitions is (4, 512). This means that the origin coordinates of the layout cell with the name "ROM2" are
The coordinates of the origin of the upper layout cell 34 are equal to each other.
It means that they are arranged in rows and arranged in 512 columns at an arrangement interval of 6 μm in the Y-axis direction.

Next, a process 50 for extracting ROM coordinate information and obtaining ROM address information corresponding thereto will be described.

FIG. 5 is a flow chart showing the process 50 executed by the CPU 2. Hereinafter, each step of the process 50 will be described in detail with reference to FIG.

In step S51, the CPU 2 receives the layout cell name. In order that the operator can easily specify the layout cell name, the CPU 2 displays a list of layout cell names on the display device 5 in a menu format, and inputs the layout cell name selected by the operator from among the displayed layout cell names. It may be received via the device 4.

The CPU 2 obtains ROM coordinate information having a layout cell name that matches the layout cell name received in step S51 from the chip layout data stored in the storage device 3 (step S52).

The CPU 2 uses the R corresponding to the ROM coordinate information.
The OM address information is received (step S53). The CPU 2 displays a screen for inputting the ROM address information on the display device 5 so that the operator can easily specify the ROM address information, and the RO input by the operator is displayed.
The M address information may be received via the input device 4.

The CPU 2 obtains the R obtained in step S52.
It is determined whether the address information is valid based on the number of times the layout cell is repeated included in the OM coordinate information (step S54). More specifically, when the number of repetitions in the X-axis direction is represented by 2 ^N , the CPU 2 determines Yes if the number of input address bits in the X-axis direction is equal to N, and otherwise. Judge as No. The same applies to the number of repetitions in the Y-axis direction. Step S5
If Yes is determined in 4, the process proceeds to step S55. If No is determined in step S54, the process returns to step S53.

The CPU 2 determines whether or not there is another layout cell which should receive the address information (step S55). When it is determined No in step S55, the CPU 2 ends the process 50.

Upon ending the process 50, the CPU 2 causes the RO
The M coordinate information and the corresponding ROM address information are stored in the storage device 3. These pieces of information can be used in the mask pattern generation process executed by the CPU 2. Alternatively, when ending the process 50, the CPU 2
These pieces of information may be directly passed to the mask pattern generation processing. Since the mask pattern generation processing is the same as the conventional one, the description is omitted.

If it is determined Yes in step S55, the CPU 2 returns the control to step S51.

Next, as shown in FIG. 4, the above-described processing 50 will be specifically described by taking the case where the ROM coordinate information 40 and 41 are stored in the storage device 3 as an example.

When the layout cell name "ROM2" is given (step S51), the CPU 2 finds ROM coordinate information corresponding to "ROM2" from the chip layout data (step S52). That is, CPU2
Is (0, 0) as the origin coordinate value and (5
94, 6) and (4, 512) as the number of repetitions.

The CPU 2 receives the address bit input to the layout cell "ROM2" as ROM address information via the input device 4 (step S5).
4).

FIG. 6 shows an example of the address bit input screen displayed on the display device 5 for the operator to input the address bits to the layout cell "ROM2". In this example, the address bit input screen has an area 6 for inputting address bits in the X-axis direction.
1, an area 62 for inputting a value of an address bit in the X-axis direction input to the area 61, an area 63 for inputting an address bit in the Y-axis direction, a Y-axis direction input to the area 63 It has an area 64 for inputting its value for the address bits of the. Each of the areas 61 to 64 is preferably scrollable so that the number of address bits that can be input or the number of values thereof is not limited. Further, in order to save the operator the trouble of inputting the address bit values one by one, it is preferable that the address bit values can be automatically input in ascending or descending order. FIG. 6 shows an example of the address bit input screen when each input is completed. B0 to B1 shown in FIG. 6 represent intermediate variables used to associate layout cells defined hierarchically with each other.

FIG. 7 schematically shows the relationship between the value of the address bits input as described above and the layout cell "ROM2". In this way, the ROM address information regarding the layout cell "ROM2" can be obtained.

In this example, the layout cell "ROM2" is used.
The number of repetitions in the X-axis direction is 4 (= 2 ² ) and the number of repetitions in the Y-axis direction is 512 (= 2 ⁹ ). Therefore, as shown in FIG. 6, when 2 bits of B0 to B1 are input in the X-axis direction and 9 bits of A7 to A15 are input in the Y-axis direction, the determination in step S54 is Yes,
It proceeds to step S55. The determination in step S55 is as described above.

In this way, the ROM coordinate information and the ROM address information can be obtained without using the ROM specification written in a specific dedicated language.

(Second Embodiment) In the first embodiment, the operator inputs the address bits interactively by using the address bit input screen or the like. Therefore, the input address bits and the actual address bits are compared with each other. There may be a contradiction between the two. An apparatus and method for further improving this point will be described below.

FIG. 8 shows a functional block diagram of the mask pattern generator 80. The mask pattern generation device 80
ROM coordinate extraction unit 81 for extracting ROM coordinate information from chip layout data, ROM address information extraction unit 82 for extracting ROM address information from chip layout data, and chip layout data,
A mask pattern generation unit 83 for generating a mask pattern based on the ROM coordinate information, the ROM address information, and the ROM data is provided.

Next, from the chip layout data to the ROM
A process 90 for extracting the coordinate information and the ROM address information will be described.

FIG. 9 is a flowchart showing the process 90 executed by the CPU 2. Hereinafter, each step of the process 90 will be described in detail with reference to FIG.

In step S91, the CPU 2 receives the name of the layout cell which constitutes the memory array section. In order that the operator can easily specify the layout cell name, the CPU 2 displays a list of layout cell names on the display device 5 in a menu format, and inputs the layout cell name selected by the operator from among the displayed layout cell names. It may be received via the device 4.

The CPU 2 extracts the ROM coordinate information from the chip layout data based on the layout cell name. Specifically, the CPU 2 obtains ROM coordinate information having a layout cell name that matches the layout cell name received in step S91 from the chip layout data stored in the storage device 3 (step S9).
2). This step is step S52 shown in FIG.
Is the same as.

The CPU 2 determines whether or not another layout cell exists (step S93). CPU2 is
Steps S91 and S92 are repeated until the ROM coordinate information is obtained for all the layout cells forming the memory array section.

The CPU 2 extracts ROM address information from the chip layout data (step S94). Details of this step will be described later.

Upon ending the processing 90, the CPU 2 causes the RO
The M coordinate information and the ROM address information are stored in the storage device 3. These pieces of information can be used in the mask pattern generation process executed by the CPU 2. Alternatively, when ending the process 90, the CPU 2 may directly pass these pieces of information to the mask pattern generation process. Since the mask pattern generation processing is the same as the conventional one, the description is omitted.

Next, the above step S94 will be described with reference to FIGS.

FIG. 10 shows a memory cell array 101 in which a plurality of memory cells 100 are arranged in a matrix, and a row decoder 102 for accessing the memory cell array 101.
2 schematically shows the configuration of a ROM having a column decoder 103 and a column decoder 103. Row decoder 102 and column decoder 1
Each of 03 has a plurality of input terminals and a plurality of output terminals. Each output terminal RO _i of the row decoder 102 is connected to the bit line 104, and each output terminal CO _j of the column decoder 103 is connected to the word line 105. Row decoder 10
One of the plurality of bit lines 104 is selectively activated according to the combination of the signals input to each of the two input terminals RI _i, and is input to each of the input terminals CI _i of the column decoder 103. One of the plurality of word lines 105 is selectively activated according to the combination of signals. Data corresponding to 1 bit is read from the memory cell connected to the activated bit line and word line.

FIG. 11 shows that the above step S94 further includes six steps S111 to S116.

Here, it is assumed that the chip layout data is preliminarily added with the coordinate information about the input terminal and the output terminal of each decoder. This coordinate information includes a plurality of terminal names, and X and Y coordinates corresponding to each of the plurality of terminal names. Figure 1 shows the directions of the X and Y axes.
It is as shown in 0.

The CPU 2 receives the name of the decoder forming the decoder section (step S111). In order that the operator can easily specify the decoder name, the CPU 2 displays a list of the decoder names in the menu format on the display device 5, and selects the decoder name selected by the operator from among the displayed decoder names via the input device 4. You may also receive it.

The CPU 2 extracts the circuit connection information of the decoder from the chip layout data based on the name of the decoder received in step S111 (step S112). The circuit connection information is information indicating which output terminal a specific input terminal of the decoder is logically connected to, and is also called a netlist. This step is performed by, for example, a commercially available CADENCE D
It can be performed by racula software.

The CPU 2 carries out a logic simulation by using the circuit connection information of the decoder extracted in step S112 (step S113). According to this logical simulation, the CPU 2 outputs from the output terminal of the decoder according to each input bit pattern, assuming that a plurality of input bit patterns including all combinations are input to the input terminal of the decoder. Get the wax output bit pattern.

For example, the column decoder 10 shown in FIG.
The case where 3 has 9 input terminals CI _{0 to} CI ₈ will be described as an example. In this case, 512 (= 2 ⁹⁾ input bit pattern as is input to the input terminal of the column decoder 103. For the input bit pattern (01001001), the output bit pattern (0 ... 010 ...
0) is output. Where (0 ... 01
0 ... 0) is 9 "0" s, 1 "1", and 5
It is assumed that 02 “0” s represent bit patterns arranged in this order from left to right. This means that the column decoder 1
The address bits input to 03 are (01001100
In the case of 1), it means that “1” is output from the tenth output terminal of the column decoder 103 and “0” is output from the other output terminals.

The CPU 2 extracts the coordinates of the output terminal of the decoder from the chip layout data (step S11).
4). As a result, the CPU 2 can obtain the correspondence between the address bits input to the decoder and the coordinates of the output terminal of the decoder. For example, in the case of the above example, in step S114, the CPU 2 causes the column decoder 10
3. Obtain the coordinates of the 10th output terminal of 3. Assuming that the coordinates are (100, 120), CPU2
Are address bits (0
10011001), the first of the column decoder 103
The coordinates (100, 120) of the 0th output terminal will be obtained. The CPU 2 similarly performs the same for the other address bits input to the column decoder 103.
Get the coordinates of the 3 output terminals.

The CPU 2 determines whether or not another decoder exists (step S115). Step S115
If Yes is determined in step S111, the process returns to step S111. If No in step S115, the process proceeds to step S116.

In this way, the CPU 2 obtains, for each of the decoders constituting the decoder section, the correspondence between the address bits input to the decoder and the coordinates of the output terminal of the decoder.

The CPU 2 associates the address bit input to each decoder with the memory cell. As a result, C
PU2 obtains ROM address information (step S11).
6).

For example, the coordinates of the output terminal of the column decoder obtained for the specific address bit input to the column decoder 103 (X ₁ , Y ₁ ) are set to the specific address bit input to the row decoder 102. It is assumed that the coordinates of the output terminal of the column decoder obtained for the pair are (X ₂ , Y ₂ ). In this example, the CPU 2 connects the address bit input to each decoder, the word line connected to the output terminal having the coordinates (X ₁ , Y ₁ ) and the output terminal having the coordinates (X ₂ , Y ₂ ). The memory cells located at the intersections of the bit lines, that is, the memory cells having the coordinates (X ₂ , Y ₁ ) are associated with each other.

In this way, the CPU 2 obtains the correspondence between the address bit and the coordinate of the memory cell. A set of this correspondence becomes ROM address information.

According to the second embodiment, it is not necessary for the operator to interactively input the address bit using the address bit input screen or the like. Therefore, it is possible to prevent the inconsistency between the input address bit and the actual address bit. Further, as a result of eliminating the need to input the ROM address information, the mask pattern generation processing based on the chip layout data can be automated, so that the reliability and efficiency of the mask pattern generation processing can be improved.

[0066]

According to the present invention, ROM coordinate information and ROM address information can be obtained without using a ROM specification written in a specific dedicated language. As a result, the operator does not have to remember the dedicated language, and the operator's burden on mask pattern generation is reduced. Further, it is possible to significantly reduce the contradiction between the described ROM specifications and the actual ROM specifications, which has been conventionally caused by a description error in the ROM specifications.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a mask pattern generation device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a mask pattern generation device.

FIG. 3 is a diagram showing a configuration example of a ROM.

FIG. 4 is a diagram showing an example of ROM coordinate information included in chip layout data.

FIG. 5: ROM coordinate information is extracted and RO corresponding to it is extracted.
It is a flowchart which shows the process for obtaining M address information.

FIG. 6 is a diagram showing an example of an address bit input screen.

FIG. 7 is a diagram schematically showing the relationship between the value of an address bit and the layout cell layout.

FIG. 8 is a functional block diagram of a mask pattern generation device according to another embodiment of the present invention.

FIG. 9 is a flowchart showing a process for extracting ROM coordinate information and ROM address information.

FIG. 10 is a diagram schematically showing a configuration of a ROM.

FIG. 11 is a flowchart showing a part of the flowchart shown in FIG. 9 in more detail.

FIG. 12 is a functional block diagram of a conventional mask pattern generation device.

FIG. 13 is a diagram showing a description example of a conventional ROM specification.

[Explanation of symbols]

 1 Mask Pattern Generation Device 11 ROM Coordinate Information Extraction Unit 12 ROM Address Information Extraction Unit 13 Mask Pattern Generation Unit

Claims (4)

[Claims] 1. A first means for extracting ROM coordinate information from chip layout data, a second means for receiving ROM address information, said chip layout data, and said chip layout data extracted by said first means. A mask pattern generation device comprising means for generating a mask pattern based on ROM coordinate information, the ROM address information received by the second means, and ROM data. 2. A first means for extracting ROM coordinate information from chip layout data, a second means for extracting ROM address information from chip layout data, said chip layout data, and said first means. A mask pattern generation device having means for generating a mask pattern based on the ROM coordinate information extracted by the ROM coordinate information, the ROM address information received by the second means, and the ROM data. 3. A first step for extracting ROM coordinate information from chip layout data, a second step for receiving ROM address information,
And a step for generating a mask pattern based on the chip layout data, the ROM coordinate information extracted in the first step, the ROM address information received in the second step, and the ROM data. A mask pattern generation method to include. 4. A first step for extracting ROM coordinate information from chip layout data, a second step for extracting ROM address information from chip layout data, and the chip layout data, the first step. A mask pattern generation method including a step of generating a mask pattern based on the ROM coordinate information extracted in step 1, the ROM address information received in the second step, and the ROM data.