JP2798031B2 - Layout information generating apparatus and its generating method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout information generating apparatus and a method of generating the same, and more particularly to a layout information generating apparatus and a method of generating information for writing a ROM code in a semiconductor integrated circuit having a built-in mask ROM. About.

[0002]

Prior to the description of the prior art, FIG.
The configuration of a ROM code which is a premise of the technology related to the layout generation device will be described with reference to a configuration diagram of one bit of a 32-word ROM shown in FIG. FIG.
In, A ₀ to A ₁ of the 5-bit address signal A ₀ to A ₄ is input to the X decoder 32, one of the X coordinate direction of the select signal lines X ₀ to X ₃ is selected You.
Similarly, of the 5-bit address signals A _{0 to} A ₄ , A
₂ to A ₄ is input to the Y decoder 31, one of the Y coordinate direction of the select signal lines Y ₀ to Y ₇ is selected. A ROM cell is set by laying out a rectangle 33 at the intersection of the select signal lines in the X coordinate direction and the Y coordinate direction selected in this way.
ROM is constituted by deriving the presence of M cells as a bit output B _0. In this case, whether the rectangle 33 is laid out in which of the logical values “1” and “0” is determined by the circuit configuration and the manufacturing process. In the following description, the logical value “1” is used. In this case, the layout is performed, and when the logical value is “0”, the layout is not performed.

FIG. 7 is a block diagram showing a configuration of a conventional example (note: conventional example 1), and FIG. 9 is a flowchart showing a processing procedure in the conventional example. As shown in FIG. 7, in this conventional example, a PROM reader 1
It comprises an OM code input control unit 2, a screen display control unit 3, a display 4, a data processing unit 5, a layout information storage unit 6, a keyboard control unit 7, and a keyboard 8. Hereinafter, the operation of the conventional example will be described with reference to the block diagram of FIG. 7, the flowchart of FIG. 9, and the configuration diagram of one bit of the ROM of FIG.

First, assuming that all the ROM cells are laid out, the designer analyzes the arrangement of the X decoder and the Y decoder for each bit output from a circuit diagram and a layout pattern diagram to be laid out. Then, as shown in FIG. 13, address / bit arrangement information of each ROM cell is extracted as an address signal value (step S ₁ ). Next, as shown in FIG. 12, one of the ROM cell groups on the layout pattern is set as a reference point 34 (see FIG. 11), and as shown in FIG. The distance from the point 34 is determined by the pitch 35 (Y _P ) and the pitch 36 between the ROM cells.
Layout coordinate information is extracted from (X _P ) and the relative positional relationship of each ROM cell calculated from the number of arrays (step S ₂ ). Subsequently, the designer associates the address / bit arrangement information with the coordinate information on the layout pattern for each ROM cell, and creates a table showing the bit output shown in FIG. Size 37 (Y _S ) and size 38 (X _S )
At the same time, the data is read from the data processing unit 5 by the keyboard 8 (step S ₃ ).

On the other hand, a PROM reading device 1 sends a PROM
The target ROM code is read from the memory (including the EPROM) (step S ₄ ), and the read ROM code is rearranged in the data processing unit 5 according to the order of the address / bit arrangement information of each ROM cell. Te, the correspondence is performed (step S _5). Next, the ROM code logical value rearranged in the order of the address / bit arrangement information is checked, and only when the ROM code logical value is “1”, the corresponding ROM code is checked.
A layout pattern in which a rectangle 33 of a designated size is output based on the layout coordinate information of the cell is generated and stored in the layout information storage unit 6 (step S).
₆ ). Then, the processing result of the step S ₆ is confirmed on the display 4 via the screen display control section 3 (Step S _7).

Next, another conventional example (Note: Conventional example 2) will be described. This conventional example is an example of a layout generation device that is an improvement of the above-described conventional example, and is proposed in Japanese Patent Application Laid-Open No. Hei 5-314215. FIG. 8 is a block diagram showing the configuration of the conventional example, and FIG. 10 is a flowchart showing the processing procedure. As shown in FIG. 8, in this conventional example, a PROM reading device 1, a ROM code input control unit 2, a screen display control unit 3, and a display 4
, A data processing unit 5, a layout information storage unit 6, a keyboard control unit 7, a keyboard 8, a ROM position information extraction unit 9, a layout verification unit 12, and a logic simulation execution unit 13. You. The operation of the conventional example will be described below with reference to the block diagram of FIG. 8 and the flowchart of FIG.

First, logic circuit diagram data is read (step T ₁ ), layout pattern data is read (step T ₂ ), and test pattern data is read (step T ₃ ). Reading of the ROM code is performed (step T ₄ ). Then
Using the logic circuit diagram data, test pattern data and ROM code, a logic simulation execution unit 1
In 3, the address bit arrangement information of each ROM cell is created (Step T _5). Then, using the logic circuit diagram data and the layout pattern, the layout verification unit 12 creates coordinate information of each ROM cell (step T ₆ ). Next, the ROM position information extracting unit 9 associates the address / bit arrangement information of each ROM cell with the coordinate information (step T ₇ ).
The correspondence between the address / bit arrangement information and the coordinate information is rearranged in the data processing unit 5 in the order of the address / bit arrangement information so as to correspond to the ROM code (step T ₈ ). And the reordered ROM
Only when the logical value of the code is “1”, the keyboard 8 and the keyboard control unit 7
By outputting a rectangle of a specified size through key input by the
A pattern is generated, and the layout pattern is stored in the layout information storage unit 6 (step T ₉ ).

The difference between the conventional example and the above-described conventional example is that the conventional example does not include the RO that is not included in the conventional example.
An M position information extraction unit 9, a layout verification unit 12, and a logic simulation execution unit 13 are newly added.
An improvement is seen in that address and bit placement information and coordinate information are automatically created by logic simulation and layout verification.

[0009]

In the above-described conventional layout information generating apparatus (conventional example 1), the designer refers to the layout pattern diagram, the logic circuit diagram, and the like, and arranges the arrangement information of the ROM cells and the corresponding information. It is necessary to create and input coordinate information in advance, and therefore, not only requires a large number of man-hours and time, but also has a drawback that there is a risk that input errors due to manual processing may occur. is there.

In another conventional example (conventional example 2) in which the above-mentioned drawbacks are improved by a method using logic simulation and layout verification, the above-mentioned drawbacks are solved. In order to compare the layout pattern with the logic circuit diagram data, it is necessary to create logic circuit diagram data in which the ROM portion is entirely represented by transistor elements. In this case, the ROM portion in the logic circuit diagram is usually described as a functional unit without being described by a logic symbol, a transistor element, and the like. In a logic simulation, the ROM portion has a length corresponding to the number of output bits. Since the processing is performed by developing on a memory as an array (matrix) corresponding to the number of addresses possessed, a great deal of man-hours are required in creating logic circuit diagram data in which a ROM portion is represented by a transistor element and executing a logic simulation in that form. And time is required.

[0011]

According to a first aspect of the present invention, there is provided a layout information generating apparatus for laying out ROM code data provided by a PROM or the like. Data processing means for adding text information corresponding to a predetermined ROM section as an identifier on an address signal input line and a bit output line for
A layout pattern analysis means for automatically analyzing a logical connection in a layout pattern in the OM section, and automatically receiving circuit layout information and ROM cell coordinate information in the layout pattern in response to an analysis result by the layout pattern analysis means. And ROM position information extracting means for extracting.

A layout information generating apparatus according to a second aspect of the present invention is a layout information generating apparatus for laying out ROM code data provided by a PROM or the like.
Data processing means for adding text information corresponding to a predetermined ROM section as an identifier on an address signal input line and a bit output line to the OM section, and a layout pattern analysis for automatically analyzing a logical connection in a layout pattern in the ROM section Means, ROM position information extracting means for automatically extracting circuit connection information and coordinate information of ROM cells in the layout pattern in response to an analysis result by the layout pattern analyzing means, and coordinate pitch between adjacent ROM cells. And address increment (increment)
By extracting ROM cell groups having the same value, and expressing these ROM cell groups collectively as an array format,
ROM for compressing and expanding the arrangement information and the coordinate information
And position information compression / decompression means.

A layout information generating method according to a third aspect of the present invention is the layout information generating method used when laying out ROM code data provided by a PROM or the like. Step, a second step of adding text information including a range designation of the ROM section, an address signal name and a bit output signal name on a layout pattern as an identifier, and weighting the text information added as the identifier. Performing a third step;
A fourth step of analyzing layout pattern data in the OM section and extracting address / bit arrangement information and coordinate information of a ROM cell forming the ROM section; and an address signal weighted in the third step. , Each RO cell is generated by the address information and the arrangement information of the bit output automatically generated through the coordinate information of each ROM cell.
A fifth step of associating the arrangement information and the coordinate information of the M cell, a sixth step of reading the ROM code from the PROM, and a seventh step of associating the ROM code with the arrangement information and coordinate information Step, an eighth step of laying out a predetermined rectangular area specified according to the contents of the ROM code on the layout pattern, and a ninth step of confirming the layout pattern created through the eighth step And having the following.

A layout information generating method according to a fourth aspect of the present invention is the layout information generating method used when laying out ROM code data provided by a PROM or the like. Step, a second step of adding text information including a range designation of the ROM section, an address signal name and a bit output signal name on a layout pattern as an identifier, and weighting the text information added as the identifier. Performing a third step;
A fourth step of analyzing layout pattern data in the OM section and extracting address / bit arrangement information and coordinate information of a ROM cell forming the ROM section; and an address signal weighted in the third step. , Each RO cell is generated by the address information and the arrangement information of the bit output automatically generated through the coordinate information of each ROM cell.
A fifth step of associating the arrangement information of the M cells with the coordinate information, extracting a ROM cell group having the same coordinate pitch between adjacent ROM cells and an address increment (increment), and extracting these ROM cell groups; The arrangement information and the coordinate information are compressed and expressed by expressing them in a grouped array format.
A sixth step of expanding the data, a seventh step of reading the ROM code from the PROM, an eighth step of associating the ROM code with the arrangement information and the coordinate information, and a step designated according to the contents of the ROM code. Laying out the predetermined rectangular area on the layout pattern
And a tenth step of confirming a layout pattern created through the eighth step,
It is characterized by having.

[0015]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG.
PROM reader 1 and ROM code input controller 2
A screen display control unit 3, a display 4, a data processing unit 5, a layout information storage unit 6, a keyboard control unit 7, a keyboard 8, a ROM position information extraction unit 9,
And a layout pattern analysis unit 10. FIG. 2 is a schematic diagram of a layout pattern showing the position of the ROM unit. FIG. 3 is a diagram showing a specific example of simplification of connection information analyzed by the layout pattern analysis unit 10, and FIG. FIG. 4 is a diagram showing an operation flowchart of the embodiment. In the following, the block diagram of FIG.
With reference to the schematic diagram of the layout pattern, the flowchart of FIG. 5, and the configuration diagram of one bit of the ROM of FIG.
The operation of the embodiment will be described.

First, the base layout pattern information 21 (see FIG. 2) is read (step U ₁ ). Next, while confirming the reading state of step U _{1 on} the display 4, the R
The range designation 22 of the OM section and the address signals (A ₀ , A ₁ ,
............, A _n) address signal names on the layout pattern 23 is input A _0, A _1, ............, and A _n, bit output _{(B 0, B 1, ............} , B _n ) Bit output signal names B ₀ , B on the layout pattern from which 24 is derived
_1, ............, and B _n are, are respectively added as text information, it is set as an identifier (step U _2). The processing procedure in step U ₂ is
It may be carried out in advance on a layout pattern creation device. Further, in the above step U _2, for text information added as identifiers by the keyboard ^{_{8, A 0 = 2 0,}} A 1 = 2 1, ............,
And weighting information as defined as A ^_n = 2 _n, the size (Y _S) 37 and the size (X _S) 38 of rectangular 33 layout is input (Step U _3). next,
The layout pattern analysis unit 10 analyzes the layout pattern data in the ROM unit 22, and extracts circuit connection information and coordinate information of each transistor. At this time, as illustrated in FIGS. 3A and 3B, an input terminal to which text information as an identifier is not added (note: an input terminal indicated as “?” In FIG. 3) ) Is processed as an invalid input for the logical operation, and the circuit elements corresponding to these input terminals are deleted from the circuit connection diagram. Further, as illustrated in FIG. 3C, when circuit elements that perform a signal inversion operation, such as an inverter, are connected in cascade, a prior deletion process of the circuit element is performed for each even-numbered stage ( step U _4). next,
In ROM positional information extraction section 9, the X decoder 32 and Y connection information of the decoder 31, the weighted address signals _{(A 0, A 1, ............} , A n) 23, FIG. 1
2, select signal lines Y ₀ , Y ₁ ,...
, Y _n and X ₀ , X ₁ ,..., X _m , and the coordinate information of each ROM cell.
The information corresponding to FIG. 3 and FIG. 14 is automatically created, whereby the arrangement information of each ROM cell is associated with the coordinate information (step U ₅ ). Then, the ROM code is read from the PROM reading device 1 via the ROM code input control unit 2 (step U ₆ ).
The coordinate information is associated (step U ₇ ), the specified rectangle 33 is laid out according to the contents of the ROM code, and stored in the layout information storage unit 6 (step U ₈ ). Then, the created layout pattern is displayed on the display 4 via the screen display control unit 3, and the layout pattern is checked (step U ₉ ).

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing the second embodiment. As shown in FIG.
M reading device 1, ROM code input control unit 2, screen display control unit 3, display 4, data processing unit 5
And a layout information storage unit 6 and a keyboard control unit 7
, A keyboard 8, a ROM position information extraction unit 9, a layout pattern analysis unit 10, and a ROM position information compression / decompression unit 11. FIG. 6 is a diagram showing an operation flowchart of the present embodiment. In the following, the block diagram of FIG. 4, the schematic diagram of the layout pattern of FIG. 2, the flowchart of FIG.
The operation of this embodiment will be described with reference to a configuration diagram for bits.

First, the base layout pattern information 21 (see FIG. 2) is read (step U ₁ ). Next, while confirming the reading state of step U _{1 on} the display 4, the R
The range designation 22 of the OM section and the address signals (A ₀ , A ₁ ,
............, A _n) address signal names on the layout pattern 23 is input A _0, A _1, ............, and A _n, bit output _{(B 0, B 1, ............} , B _n ) Bit output signal names B ₀ , B on the layout pattern from which 24 is derived
_1, ............, and B _n are, are respectively added as text information, it is set as an identifier (step U _2). The processing procedure in step U ₂ is
It may be carried out in advance on a layout pattern creation device. Further, in the above step U _2, for text information added as identifiers by the keyboard ^{_{8, A 0 = 2 0,}} A 1 = 2 1, ............,
And weighting information as defined as A ^_n = 2 _n, the size (Y _S) 37 and the size (X _S) 38 of rectangular 33 layout is input (Step U _3). next,
The layout pattern analysis unit 10 analyzes the layout pattern data in the ROM unit 22, and extracts circuit connection information and coordinate information of each transistor. At this time, as in the case of the first embodiment, the circuit element corresponding to the input terminal to which the text information as an identifier is not added is deleted from the circuit diagram, and the signal inversion circuit element such as an inverter is removed. In the cascade circuit, the circuit element is deleted for each even-numbered stage (step U ₄ ). Next, the X decoder 32 and the Y decoder 3
1 and the weighted address signal (A ₀ ,
A ₁ ,..., A _n ) 23, select signal lines Y ₀ , Y ₁ ,..., Y _n and X ₀ , X ₁ ,. 13 and 14 based on the address signal information at _m and the coordinate information of each ROM cell.
Is automatically created, whereby each R
The OM cell arrangement information is associated with the coordinate information (step U ₅ ). Steps U ₁ to U
_The processing procedure contents up to ₅ are exactly the same as in the case of the above-described first embodiment.

[0020] Next, the arrangement information and the coordinate information associated in step U _5, in order to record the number of all the ROM cell is required, in the case of 16 Mbit level of the mask ROM, the above data information Requires hundreds of megabytes of storage space. Therefore,
The ROM position information compression / expansion unit 10
A process for reducing the storage capacity is performed by extracting ROM cell groups having the same coordinate pitch between M cells and address increments (increments) and expressing these ROM cell groups in an integrated array format (step). U _10). In the processing of step U _10, for example, in the case of a ROM shown in FIG. 11, the arrangement information and coordinate information of the ROM cell was necessary representation has been 32 records in the form as shown below, 3 records Has been reduced to

[Coordinate] [Address] [Bit] BASE X, Y, 0, 0 (Definition of reference point 34) [Level] [Direction] [Pitch] [Number of times] [Address increment] ARRAY, 0, x, X _P , 4,1 (first array definition) ARRAY, 1, y, Y _P , 8,4 (second array definition) Then, just like in the first embodiment, the ROM code PROM reading device 1 via input control device 2
The ROM code is read (step U ₆ ), and the data processing unit 5 associates the ROM code with the arrangement information / coordinate information (step U ₆ ).
₇ ) The specified rectangle 33 is laid out according to the contents of the ROM code, and stored in the layout information storage unit 6 (step U ₈ ). Then, the created layout pattern is displayed on the display 4 via the screen display control unit 3, and the layout pattern is checked (step U ₉ ).

[0022]

As described above, according to the present invention, the arrangement information and coordinate information of each ROM cell are automatically extracted by adding an identifier as text information to a base layout pattern. Therefore, it is possible to greatly reduce the man-hour and time required for manually extracting the placement information and the coordinate information in the related art, and to prevent human error from occurring. This has the effect.

Further, since it is not necessary to perform the conventionally used logic simulation, it is possible to eliminate the number of preparation steps and time required for executing the simulation, and to execute the logic simulation without performing the logic simulation. There is an effect that an apparatus with high design quality can be obtained.

Further, by compressing and storing the arrangement information and coordinate information of each ROM cell, the required storage capacity corresponding to such information can be reduced from several hundred megabytes to several kilobytes. This allows
The storage of the information becomes extremely easy, and different R
In the case of re-processing by the OM code, by starting the processing from the present data, it is possible to omit the previous step, and there is an effect that the processing time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a schematic diagram of a layout pattern showing a position of a ROM unit.

FIG. 3 is a diagram illustrating simplification of connection information analyzed by a layout analysis unit.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram showing an operation flowchart of the first embodiment.

FIG. 6 is a diagram showing an operation flowchart of the second embodiment.

FIG. 7 is a block diagram showing a conventional example (1).

FIG. 8 is a block diagram showing another conventional example (2).

FIG. 9 is a diagram showing an operation flowchart of the conventional example (1).

FIG. 10 is a diagram showing an operation flowchart of the conventional example (2).

FIG. 11 is a configuration diagram of one bit of a 32-word ROM.

FIG. 12 is a diagram showing a relationship among select signal lines, address signal lines, and coordinates on a layout.

FIG. 13 is a diagram showing a relationship between a ROM cell and an address signal.

FIG. 14 is a diagram showing a relationship between a ROM cell and coordinates on a layout.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 PROM reader 2 ROM code input control part 3 Screen display control part 4 Display 5 Data processing part 6 Layout information storage part 7 Keyboard control part 8 Keyboard 9 ROM position information detection part 10 Layout pattern analysis part 11 ROM position information compression / expansion Unit 12 layout verification unit 13 logic simulation execution unit 21 layout pattern information 22 ROM unit 23 address signal 24 bit output 31 Y decoder 32 X decoder 33 rectangle 34 reference point 35 pitch (Y _P ) 36 pitch (X _P ) 37 size (Y) _S) 38 size _{(X S) U 1 ~U 9} , S 1 ~S 7, T 1 ~T 10 step

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50 H01L 27/10

Claims (4)

(57) [Claims] 1. A layout information generating apparatus for laying out ROM code data provided by a PROM or the like, comprising: a ROM portion on a base layout pattern; a predetermined ROM portion on an address signal input line and a bit output line for the ROM portion; A data processing unit that adds text information corresponding to the ID as an identifier; a layout pattern analysis unit that automatically analyzes a logical connection in a layout pattern in the ROM unit; Circuit connection information in pattern and R
And a ROM position information extracting means for automatically extracting coordinate information of an OM cell. 2. A layout information generating apparatus for laying out ROM code data provided by a PROM or the like, comprising: a ROM section on a base layout pattern; a predetermined ROM section on an address signal input line and a bit output line for the ROM section; A data processing unit that adds text information corresponding to the ID as an identifier; a layout pattern analysis unit that automatically analyzes a logical connection in a layout pattern in the ROM unit; Circuit connection information in pattern and R
ROM position information extracting means for automatically extracting the coordinate information of the OM cells, and extracting the ROM cell groups having the same coordinate pitch between adjacent ROM cells and the address increment (increment), and integrating these ROM cell groups By expressing the layout information and the coordinate information in an array format,
And a OM position information compression / decompression means. 3. A layout information generating method used when laying out ROM code data provided by a PROM or the like, comprising: a first step of reading layout pattern information serving as a basis; Text information including the above address signal name and bit output signal name,
A second step of adding the identifier as an identifier, a third step of weighting the text information added as the identifier, a ROM forming the ROM unit by analyzing layout pattern data in the ROM unit A fourth step of extracting address / bit arrangement information and coordinate information of the cell; an address signal weighted in the third step; and address information of a bit output automatically generated based on the coordinate information of each ROM cell. And R
Fifth correspondence between OM cell arrangement information and coordinate information
A sixth step of reading the ROM code from the PROM; a seventh step of associating the ROM code with the arrangement information / coordinate information; and a predetermined rectangular area designated according to the contents of the ROM code. An layout step of laying out a layout pattern on a layout pattern, and a ninth step of confirming a layout pattern created through the eighth step. 4. A layout information generating method used when laying out ROM code data provided by a PROM or the like, comprising: a first step of reading base layout pattern information; Text information including the above address signal name and bit output signal name,
A second step of adding the identifier as an identifier, a third step of weighting the text information added as the identifier, a ROM forming the ROM unit by analyzing layout pattern data in the ROM unit A fourth step of extracting address / bit arrangement information and coordinate information of the cell; an address signal weighted in the third step; and address information of a bit output automatically generated based on the coordinate information of each ROM cell. And R
Fifth correspondence between OM cell arrangement information and coordinate information
And extracting the ROM cells having the same coordinate pitch between adjacent ROM cells and the address increment (increment).
A sixth step of compressing / expanding the arrangement information and the coordinate information by expressing the cell group in an integrated array format; a seventh step of reading a ROM code from a PROM; An eighth step of associating the arrangement information / coordinate information, a ninth step of laying out a predetermined rectangular area specified in accordance with the contents of the ROM code on a layout pattern, and And a tenth step of confirming a layout pattern to be created.