JP3090510B2 - Semiconductor device layout method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device layout method. In recent years, semiconductor devices have become more highly integrated and multifunctional, and the circuit scale has been increasing. For this reason, the time required for circuit layout tends to increase, and it is required to realize a simple layout method.

[0002]

2. Description of the Related Art A conventional layout method of a semiconductor device using a system design apparatus such as a CAD system will be described with reference to FIG. 2. First, a desired function of a semiconductor device to be designed is expressed in a function description language (step S1). 1. Hereinafter, the steps are referred to as S), and then a logic description operation for converting the function description language into a logic circuit is performed (S2).

Next, a basic operation of the converted logic description is confirmed (S3, S4). That is, the static characteristics of each of the logic circuits constituting the logical description are sequentially read from the first file 1 in which the static characteristics of various types of logic circuits are stored in advance, and the operation of the logical description is simulated. Then, it is determined whether or not the simulation result satisfies a desired function (S4).
If it is satisfied, proceed to the next step. If it is not satisfied, change the logical description and repeat this operation until the logical description satisfies the desired function.

If the logic description satisfies a desired function, the logic description is laid out as an actual logic circuit (S5). That is, from the second file 2 in which physical data of a large number of logic circuits having different sizes, heights or widths of the logic cells constituting the logic circuit, transistor sizes, power supply line widths, number of contacts, and the like are stored in advance, the logical file is stored. The data corresponding to the description is read out and laid out.

Next, the operation of the laid-out logic circuit is verified by simulation (S6). If the desired operation characteristics are satisfied, the layout operation is terminated. If not, the layout operation and the verification and verification operation are performed. Is repeated, and if a satisfactory characteristic cannot be obtained by changing the layout, the logical description operation is repeated.

[0006]

In the layout method as described above, if a desired functional characteristic cannot be obtained due to the operation simulation of the logical description, the logical description is changed even though there is no error in the functional description. If the desired characteristics cannot be obtained by simulation after the layout of the actual logical cell based on the physical data, the layout must be changed or the logical description must be changed retrospectively. There is a problem that processing work for improvement is complicated.

Further, the first file 1 needs to store a large number of static characteristics of a large number of logic circuits, and the second file 2 has various types of logics corresponding to the characteristics even if they have the same logical function. I need to store cell data,
There is a problem that the first and second files 1 and 2 require an enormous capacity.

An object of the present invention is to simplify the layout work by eliminating the need to change the logical description and the layout of the logical cells unless the functional description is changed, and to reduce the capacity of a file for storing physical pattern data. It is to provide a layout method that can be reduced.

[0009]

According to the present invention, a function of a semiconductor device is described in a function description language, the function description language is converted into a logic description language and stored in a first storage means. cell performs a symbolic layout calculated on the basis of the
Storing the data as second data in the second storage means;
The logical description language stored in the first storage means and the second
Symbolic based on the cell data stored in the storage means.
Symbolic layout data
Storing the data as third data in a third storage means;
Of the symbolic layout data stored in the storage means
Fourth storage means for verifying the characteristics and as cell characteristic parameters
Storing the data in the second storage means.
Data and symbolic files stored in the third means.
Layout data and cells stored in the fourth storage means
Calculate the physical pattern based on the characteristic parameters
And a step of performing a physical layout .

[0010]

According to the present invention, an arbitrary cell shape and cell characteristics are realized based on the symbolic layout and the characteristic evaluation data, so that verification after layout is not required and layout change after layout is prevented.

[0011]

FIG. 1 shows an embodiment of the present invention.
It will be described according to. In this embodiment, first, a desired function of a semiconductor device to be designed is expressed in a function description language (S11), and then a logic description operation for automatically converting the function description language into a logic circuit is performed (S12). Logical data is stored in the file 3a.

On the other hand, the symbolic layout of the basic logic cell is calculated based on the rule file 3b (S1).
3) Cell data is stored in the file 3c in advance. That is, the symbolic layout receives as input symbol data based on the type of the logic cell and rule information such as a data input layer, and makes it possible to change elements in the actual physical layout of the logic cell, such as transistor size, cell height and width, and power supply line. The layout is made by replacing the width, the number of contacts, and the like with symbols in advance.

The cell data stored in the file 3c is subjected to rule file conversion (S14) and is stored in the rule file 3d in advance. That is, the characteristic data of each cell of the cell data stored in the file 3c and the characteristic data of each of the variable data are stored in the rule file 3d for verification.

Next, a symbolic layout of a desired semiconductor device is calculated based on the logical data stored in the file 3a and the cell data stored in the file 3c (S15), and stored in the layout file 3e. .

Next, based on the data stored in the layout file 3e, extraction of the characteristic evaluation data of the symbolic layout (S16) and verification of the extracted characteristic evaluation data (S17) are performed. That is, file 3f
Is read out from the file 3g, information on wiring length data of each logical net is read from the file 3g, and the characteristic data is read from the rule file 3d. Read out,
From the file 3h, verification data including timing data such as input data and operation timing of a desired semiconductor device is read. Then, an operation is performed to extract the optimum value of the variable parameter of the symbolic layout based on each of these data, and the operation result is stored in the file 3i as a cell characteristic parameter.

Next, the symbolic layout stored in the layout file 3e and the file 3i
Cell characteristic parameters stored in the file 3c
Is read out, and a physical pattern of a desired semiconductor device is calculated from these data (S18). Then, the physical pattern is compressed by further reducing the number of unnecessary contacts and unnecessary wiring, and the redundancy is removed to improve the yield in the actual manufacturing process (S19), and the layout operation is completed.

As described above, in the layout method of this embodiment, a symbolic layout is calculated based on a logical description, and a physical pattern of an actual logic circuit is formed based on the symbolic layout and the cell characteristic parameters. Therefore, since the layout is performed while verifying the cell characteristics, it is not necessary to verify the characteristics after the layout, and as a result, the characteristics can be improved without changing the layout. In addition, it is not necessary to previously store a large number of physical patterns for a large number of logic cells having the same function in a file, and it is possible to realize an optimal layout for a desired semiconductor device, such as a cell shape and a transistor size, Layout of various types of semiconductor devices can be easily performed.

[0018]

As described in detail above, the present invention simplifies the layout work by eliminating the need to change the logic description and the layout of the logic cells unless the function description is changed, and stores the physical pattern data. An excellent effect of providing a layout method for a semiconductor device that can reduce the capacity of a file for the semiconductor device is exhibited.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a conventional example.

[Explanation of symbols]

 3a-3i files

────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FIG06F 15/60 656F H01L 21/82 C (56) References JP-A-3-15984 (JP, A) JP-A-4-51367 (JP, A) Yukio Uematsu, Hiroya Kawamura, Yutaka Koike, "Cell Design Using Symbolic Layout System SYLA", Information Processing Society of Japan Research Report (88-DA-41), 1988, 1988, Vol. No., p. 1-9 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 17/50 H01L 21/82

Claims (1)

(57) [Claims] 1. The function of a semiconductor device is described in a function description language.Description
And saidConvert function description language to logical description languageFirst note
Storing in the storage means;  In the base cellOn the basis ofSymbolic layoutCalculationDo
Storing the cell data in the second storage means; A logical description language stored in the first storage means and the logical description language
2 based on the cell data stored in the storage means.
Perform symbolic layout calculation and symbolic layout
Storing in a third storage means as data; Symbolic layout stored in the third storage means
The characteristics of the data are verified and the fourth
Storing in storage means of The cell data stored in the second storage means and the third
The symbolic layout data stored in the means
And the cell characteristic parameters stored in the fourth storage means.
Calculate the physical pattern based on the physical layout
Process, Having Semiconductor device layout method characterized by the following:
Law.