JPH05225285A - Analog element design device - Google Patents

Abstract

PURPOSE:To automatically obtain analog element data information once analog element design information is generated and to reduce the man-hours and shorten TAT. CONSTITUTION:An element information input part 2 extracts information which is necessary for respective parts from the analog element design information 1 consisting of element demand specifications, a design rule, and basic cell element data required for analog element designing and stores the information in a temporary storage part 7. A layout data generation part 3 receives information on respective element structures, shape parameter values, and mask pattern layer numbers from the temporary storage part 7 and generates analog element mask pattern information, an element extraction part 4 receives the mask pattern information and element extraction information from the temporary storage part 7 and generates element connection information including parasitic elements, and an element characteristic arithmetic part 5 receives the element connection information and element physical characteristic information from the temporary storage part 7 and generates analog element circuit characteristic information. An element data output part 6 receives the analog element mask pattern information and analog element characteristic element from the temporary storage part 7 and edits those pieces of information to output analog element data information 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog element design apparatus for designing analog elements in an integrated circuit.

[0002]

2. Description of the Related Art When designing an analog element in a semiconductor integrated circuit, etc., a circuit designer manually creates a mask pattern of the element based on the know-how of design experience, and the created mask pattern is used to remove the elements other than the element. It was carried out by reading the parasitic element of, making circuit connection information, performing a circuit simulation using a computer, and judging the characteristic of this analog element from the result.

[0003]

This conventional analog device designing method has the drawback of spending a great deal of man-hours and time for a circuit engineer, and requires many years of experience.
There is also the problem of human error.

An object of the present invention is to solve the above problems, to provide an analog element designing apparatus having a reduced number of design steps and a shortened TAT.

[0005]

The structure of an analog element designing apparatus according to the present invention comprises element requirement specifications such as element values, sizes, and element types required for analog element design, and electrical specifications to be adhered to during element design. An element information input section for extracting information required by each section from analog element design information including design rules including geometric rules and basic cell element data including basic shape data and element parameters of element constituent elements; A temporary storage unit for temporarily storing information from the device information input unit; receiving information on each device structure, shape parameter value, and mask pattern layer number from the temporary storage unit, generating analog device mask pattern information, and temporarily storing the analog device mask pattern information. A layout data generation unit for storing in a storage unit; including a parasitic element for receiving the mask pattern information and element extraction information from the temporary storage unit An element extraction unit that generates child connection information and stores it in the temporary storage unit; receives the element connection information and device physical characteristic information from the temporary storage unit, generates analog element circuit characteristic information, and stores it in the temporary storage unit An element characteristic calculation unit; an element data output unit which receives the analog element mask pattern information and analog element characteristic information from the temporary storage unit and edits the information to output analog element data information; each of the calculation units and the temporary And a control unit for controlling the storage unit.

[0006]

1 is a block diagram of an embodiment of the present invention, FIG.
6 is a block diagram of the components of FIG. In this embodiment, the element information input unit 2 and the layout data generation unit 3
The element extraction unit 4, the element characteristic calculation unit 5, the element data output unit 6, the temporary storage unit 7, and the control unit 8. In this embodiment, analog element design information (1)
By creating, the mask pattern of the analog element and the analog element data information (9) of the characteristic information can be automatically created.

In the figure, an analog element design information file 1 includes element requirement specifications consisting of element values, sizes, and element types required for analog element design, and electrical / geometric rules to be observed when elements are generated. Design rules,
It is a file including basic cell element data consisting of basic shapes of element constituent elements and shape parameters.

The element information input section 2 reads the information from the analog element design information file 1 as shown in FIG. 2, and the information of the layout data generating section at step 21 and the element extracting section 4 at step 22. And the information of the element characteristic calculation unit 5 in step 23. The element requirement specification information including the element value, the element size, the element type, and the like extracted in this way, and the basic cell element data information including the electrical / geometric rail information, the element structure, the shape parameter, and the basic shape are It is stored in the temporary storage unit 7.

Subsequently, as shown in FIG. 3, the layout data generating section 3 receives the element value, the element size, the element requirement specification of the element type, the electrical / geometrical design rule and the basic cell from the temporary storage section 7, as shown in FIG. Read element data, then step 3
In 1, the element is selected according to the element type of the element required specifications.
When these element types are resistance elements, in step 32, the element value of the element requirement specification is calculated using the contact basic cell and the resistance basic cell, and the size of the resistance basic cell is calculated using the sheet resistance value of the resistance basic cell of the design rule. Then, the contact basic cell and the resistance basic cell are coupled to generate resistance element layout data.

Next, when the element type is a capacitive element, in step 33, the element value of the element required specifications and the unit capacitance value in the design rule are used to determine the size of the basic capacitance L and the geometric rule is violated. The layout data of the capacitive element is generated so as not to do so.

Next, in the case where the device type is a bipolar device, in step 34, the collector basic cell and the base are selected according to the device structure such as the multi-emitter and multi-collector of the device required specifications and the wiring width designation formula according to the device structure in the design rule. The size of the basic cell and the emitter basic cell is determined, and coupling is performed so as not to violate the geometrical rule, and layout data of the bipolar element is generated.

Next, when the element is a MOS element, step 3
In step 5, the sizes of the channel element cell and the diffusion basic cell are determined according to the required channel length, channel width, and diffusion size, and coupling is performed so as not to violate the geometric rule to generate layout data of the MOS element. .. The layout data of the element thus generated is stored in the temporary storage unit 7.

Next, as shown in FIG. 4, the element extracting unit 4 reads the element layout information and electrical / geometric rule information from the temporary storage unit 7 in step 41, and selects the element type. Information is extracted according to the type.

In the case of the resistance element, in step 42, the resistance value of the resistance element and the capacitance element which is a parasitic element are extracted based on the sheet resistance value and the capacitance value of the resistance basic cell. In step 47, the unit capacitance value and sheet resistance value of the capacitance basic cell are used to extract the capacitance value of the capacitance element and the resistance element which is a parasitic element. The size of the bipolar element and the resistance element that is a parasitic element are extracted based on the sheet resistance values of the cell and the emitter basic cell. If the element type is a MOS element, in step 45, the sheet resistance values of the channel basic cell and the diffusion basic cell, Based on the capacitance value, the MOS element and the parasitic resistance element and capacitance element are extracted. The respective elements extracted in this way and the parasitic element information extracted from them are stored in the temporary storage unit 7.

Next, as shown in FIG. 5, the element characteristic calculation unit 5 stores the element value, the element size, and the parasitic element information generated by the element extraction unit from the temporary storage unit 7 in step 51. , The characteristic test conditions of the electrical / geometric rules are read and circuit connection information for circuit analysis is created. Next, in step 52, the modified node analysis method is used to analyze the electrical characteristic information of each element. create. The created electrical characteristic information of each element is stored in the temporary storage unit 7.

Next, the element data output section 6 outputs the element layout data information from the temporary storage section 7 as shown in FIG.
The electrical characteristic information is read and edited, and the analog element data information is output to the file 9. Regarding the storage circuit, the temporary storage unit 7 stores the processing result of each processing unit.

FIG. 7 is a block diagram showing the configuration of the second embodiment of the present invention, and FIG. 8 is a detailed block diagram of FIG. In the figure, the plurality of input / output dedicated devices 10 and the arithmetic processing dedicated device 12 are connected by a network 11 capable of passing data between the respective devices. If the analog element design information file 1 is created and input to the input / output dedicated device 10, the analog element data information 10 based on the analog element design information 1 can be automatically created and output by the input / output dedicated device 10. it can.

As shown in FIG. 8, the arithmetic processing-dedicated device 12 includes the layout data generating section 3, the element extracting section 4, the element characteristic calculating section 5, and the arithmetic processing-dedicated controlling section 15 described in FIG. It is composed of a temporary storage unit 16 dedicated to arithmetic processing. The input / output dedicated device 10 is composed of the element information input unit 2, the element data output unit 6, the input / output dedicated control unit 13, and the input / output dedicated temporary storage unit 14 described with reference to FIG.

Here, the arithmetic processing dedicated control unit 15 controls each arithmetic unit in the apparatus and also controls the transfer of data with the input / output dedicated apparatus 10 via the network 11. Further, the input / output-dedicated device 13 controls each arithmetic unit in the device, and also controls the transfer of data to / from the arithmetic processing-dedicated device 12 via the network 11.

[0020]

As described above, according to the present invention, in the design of an analog element, a conventional designer performs a design using know-how based on past cases and experiences, and manually checks as a verification means. If the analog element generation information is created, the analog element data information can be automatically obtained, and there is an effect that the design man-hour and the TAT can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an analog element designing apparatus of the present invention.

FIG. 2 is a flowchart of the element generation / input unit in FIG.

FIG. 3 is a flowchart of a layout data generation unit in FIG.

FIG. 4 is a flowchart of the element extraction unit of FIG.

5 is a flowchart of the element characteristic calculation unit in FIG.

FIG. 6 is a flowchart of the element data output unit of FIG.

FIG. 7 is a block diagram showing a device configuration of a second embodiment of the present invention.

FIG. 8 is a block diagram showing a detailed configuration of FIG.

[Explanation of symbols]

 1 Analog element design information file 2 Element information input section 3 Layout data generation section 4 Element extraction section 5 Element characteristic calculation section 6 Element data output section 7 Temporary storage section 8 Control section 9 Analog element data information file 10 Input / output dedicated device 11 Nate Work 12 Device for exclusive use of arithmetic processing 13 Control unit for exclusive use of input / output 14 Temporary storage unit for exclusive use of input / output 15 Control unit for arithmetic processing 16 Temporary storage unit for arithmetic processing

Claims (1)

[Claims] 1. An element value required for analog element design,
It consists of element required specifications such as size and element type, design rules including electrical and geometrical rules that must be adhered to when designing the element, and basic cell element data consisting of element element basic shape data and shape parameters. An element information input section for extracting information required by each section from analog element design information; a temporary storage section for temporarily storing information from this element information input section; and each element structure and shape parameter value from this temporary storage section A layout data generation unit for receiving mask pattern layer number information, generating analog element mask pattern information and storing the analog pattern in the temporary storage unit; receiving the mask pattern information and element extraction information from the temporary storage unit, and parasitic element An element extraction unit that generates element connection information including the element connection information and stores the element connection information in the temporary storage unit; Element characteristic calculation section that receives the characteristic information to generate analog element circuit characteristic information and stores it in the temporary storage section; receives the analog element mask pattern information and analog element characteristic information from the temporary storage section and edits these information. An analog element designing device comprising: an element data output section for outputting analog element data information; and a control section for controlling each of the arithmetic sections and the temporary storage section.