JPH07262233A - Method and device for deciding form of element in analog lsi - Google Patents

Abstract

PURPOSE:To automatically decide the form of an element satisfying an analog restriction. CONSTITUTION:In the ascertaining processing 31 of the same form element group as against plural kinds of elements mentioned by the element numbers of a net list, an approximate arrangement condition which is previously set so that they are set to be the same forms is inputted. It is judged whether the plural elements applied to the approximate arrangement condition exists on the net list or not. When the plural elements applied to the approximate arrangement condition exist, the element numbers are set to be one group, and respective groups are stored as intermediate data. In the deciding processing 33 of the element form, element form designation where a basic form designated for constituting the element is previously defined as against the element number is inputted, and it is judged whether the element numbers in the respective groups as intermediate data are applied to the element numbers designated for inputted element form designation or not. When they are applied, the plural basic forms are used for parameters showing the characteristics of the elements so as to decide the forms of the elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of determining a shape of an element in an analog LSI and a shape determining apparatus therefor, and more particularly to automatic shape determination of an element which satisfies layout restrictions in an analog LSI and can be highly integrated. It is a thing.

In recent years, bipolar / analog ICs have been required to be shortened in development period while being made larger in scale and highly integrated. Therefore, it is desired to reduce the layout processing time by automating the element shape determination in the layout.

[0003]

2. Description of the Related Art Conventionally, bipolar analog ICs (Inte
grated circuit), large scale and high integration are being promoted. Therefore, a CAD (Computer Aided Design) device is used in the circuit design of the analog IC, and the design time is shortened. Moreover, a verification program (circuit simulator) for verifying whether the designed analog IC operates normally is used, and the verification time is shortened by verifying the operation by a computer.

[0004]

By the way, the analog I
The layout of C has many restrictions on its layout. The restriction is that, for example, a pair of transistors forming a current mirror must be arranged adjacent to each other. Also,
For example, when designing a transistor that allows a current to flow ten times as much as that of one transistor, the desired current cannot be obtained simply by multiplying the shape of the transistor by ten times. Therefore, it is necessary to form ten adjacent transistors having the same shape to obtain a desired current. Due to these constraints, the layout of the elements constituting the macro and the shape of the elements at the time of the macro layout are determined by a skilled designer himself.

On the other hand, there are automatic layouts, but since the shape of the element for the layout must be set in advance for each element to be used, it takes a lot of time for the setting, and the analog There was a problem that the IC development period could not be shortened.

The present invention has been made to solve the above problems, and its object is a method of determining the shape of an element in an analog LSI capable of automatically determining the shape of the element satisfying analog constraints. And to provide a shape determining device.

[0007]

In order to achieve the above object, the present invention provides a method of determining the shape of an element in an analog LSI for determining the shapes of a plurality of types of elements described by element numbers in a preset netlist. Therefore, by inputting the proximity placement condition set in advance to have the same shape, it is determined whether a plurality of elements corresponding to the proximity placement condition are on the netlist. These element numbers are set as one group, each group is stored as intermediate data, and an element shape designation in which a basic shape designated to configure the element is defined in advance for the element number is input, and the element shape is input. It is determined whether or not the designated element number is the element number within each group stored in the intermediate data, and if there is an element number, the characteristics of each element within the group are indicated. The parameter is divided by the parameter that shows the characteristics of the basic shape, and if the quotient is an integer as a result of the division, the quotient is determined as the number of basic shapes that make up each element and the shape of that element is determined. .

If the result of the division is that it is not divisible and the element is a resistor, the remainder of the result of division is divided by a preset number, and the quotient and basic shape of the result of division are obtained. When the resistance value is formed by the resistance value and the resistance value which is a parameter showing the characteristics of the element, division is performed until the resistance value falls within a preset error range, and the resistance value within the error range The quotient of the results of the division is set as the number of basic shapes forming each element to determine the shape of the element.

Further, when the element number in each group stored as the intermediate data is not the element number designated in the element shape designation, and the element having the element number is a transistor or a capacitor, the elements have the same shape. Obtain the greatest common divisor of the parameters that show the characteristics of each element, and use the element with the greatest common divisor as a reference to find the number of reference elements to be used in accordance with the characteristics of each element. The shape of the element is determined by the number of the elements to be used, and when the element is a resistor, the size of one of the resistance values is used as a reference size, and the total area when each resistor is automatically generated by the reference size is determined. The number of elements to be formed is calculated based on the reference size when the total area is the smallest, and the shape of the element is determined based on the reference size and the number of elements to be formed.

[0010]

Therefore, according to the present invention, the proximity placement condition set in advance for making the same shape is input to a plurality of types of elements described by the element numbers in the preset net list, It is determined whether or not a plurality of elements corresponding to the close placement condition are on the netlist. When there are a plurality of elements that meet the close arrangement condition, these element numbers are set as one group and each group is stored as intermediate data.

Further, an element shape designation in which a basic shape designated for constructing the element is previously defined for the element number is input, and is input to the element number in each group stored as the intermediate data. It is determined whether or not there is a designated element number in the element shape designation. If there is an element number, the parameter indicating the characteristic of each element in the group is divided by the parameter indicating the characteristic of the basic shape, and if the quotient is an integer, the quotient is calculated for each element. The shape of the element is determined as the number of basic shapes constituting the element.

On the other hand, when the quotient is not an integer and the element is a resistance as a result of the division, the remainder of the division result is divided by a preset number. Then, when the resistance is formed by the quotient of the result of the division and the resistance value of the basic shape, the resistance value is divided into the resistance value that is a parameter showing the characteristics of the element within a preset error range. Is repeated. Then, the shape of the element is determined by using the quotient of the result of the division that is the resistance value of the error range as the number of basic shapes forming each element.

Further, when the element number in each group stored as the intermediate data is not in the element number designated in the element shape designation and the element having the element number is a transistor or a capacitor, the elements have the same shape. The greatest common divisor of the parameters showing the characteristics of each element is obtained. Then, with the element of the greatest common divisor being the reference, the number of reference elements to be used corresponding to the characteristics of each element is obtained, and the shape of the element is determined by the reference element and the number of reference elements. Is determined. On the other hand, when the element is a resistance, the size of one of the resistance values is used as a reference size, and the total area when each resistance is automatically generated based on the reference size is calculated.
Then, the number of forming each element is calculated with the reference size when the total area becomes the smallest, and the shape of the element is determined by the reference size and the number of forming each element.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
This will be described with reference to FIG. FIG. 2 is a schematic diagram showing a system configuration of a layout device to which the present invention is applied. The shape determining device 1 comprises a CAD (Computer Aided Design) device, and has a central processing unit (hereinafter referred to as CPU) 2, a memory 3, a magnetic disk device 4, a display 5 such as a CRT,
A keyboard (including a mouse) 6 and a magnetic tape device 7 are provided.

The CPU 2 operates on the basis of predetermined program data stored in the memory 3.
In the memory 3, the program data executed by the CPU 2 and various data necessary for the execution are stored in advance, and the processing results of the CPU 2 based on the program data are temporarily stored.

The memory 3 stores a plurality of files 11 to 21 shown in FIG. File 11 contains the elements of the analog IC and the connections between them (netlist)
Is stored. The netlist is generated from a circuit diagram previously designed by a CAD device for circuit design (not shown). The netlist is composed of a plurality of circuit blocks according to its operation, and each circuit block is composed of a plurality of elements or a macro of a plurality of elements. Then, the element number indicating each element and the parameter indicating the characteristics of the element (for example, in the case of a transistor, current flowing through the transistor) are simultaneously described in the netlist.

The file 12 stores the close placement, which is the constraint of the layout of the analog IC, and the close placement condition for determining the elements having the same shape. The file 13 stores intermediate data for temporarily storing an element for determining the shape.

The file 14 stores in advance the proximity arrangement designation in which a plurality of element numbers are defined in order to designate the elements having the same arrangement and the same arrangement. The file 15 stores an element shape designation in which a basic shape serving as a reference for forming the element is defined for a plurality of elements in advance. In the file 16, when determining the shape of the resistance, when the resistance value is formed from a plurality of resistances and the number of the resistances is calculated, the original resistance value and the resistance value composed of the plurality of resistances are calculated. The allowable error that defines the error between and is stored. File 17 contains file 1
The element correspondence designation defining the cell name corresponding to the shape of the element stored in the intermediate data 3 is stored. The file 17 also stores definitions that specify automatic generation of resistors and capacitors (capacitors). File 18 contains
Element automatic generation parameters that define conditions for automatically generating elements are stored. The file 19 stores the resistance width when the resistance shape is automatically generated. The file 20 stores element shape information in which the shapes and arrangement numbers of all the elements existing in the netlist stored in the file 11 are determined. In the file 21, the element number for which the shape of the element could not be determined is stored as an error element.

The files 11 to 19 are stored in the magnetic disk device 4, and are read from the magnetic disk device 4 and stored in the memory 3 in advance. On the other hand, file 20
Are temporarily stored in the memory 3 and then stored in the magnetic disk device 4 when the processing is completed.

When the shape determining process is started by operating the keyboard 6, the CPU 2 executes the element shape determining process shown in FIG. 1 based on the program data stored in the memory 3. That is, the CPU 2 executes each configuration of the identical shape element group identification processing 31, the identical shape element group identification addition processing 32, the element shape determination processing 33, and the element shape final determination processing 34 based on the program data. Has become.

In the identical shape element group identification process 31 as the identical shape element group identification means 31, the CPU 2 reads the netlist stored in the file 11. Also,
The CPU 2 reads the close placement condition stored in the file 12. Then, the CPU 2 searches the netlist for an element corresponding to the read proximity placement condition among the elements of the net (connection between elements) described in the read netlist. That is, the elements that need to be arranged close to each other need to have the same electrical characteristics and have the same shape. Therefore, when the element corresponding to the netlist exists, the CPU 2 stores the element number indicating the element described in the netlist and the size of the element stored in the file 12 in the file 13 as intermediate data.

This close placement condition is defined in advance as shown in FIG. 3, for example. For example, the emitter terminals of two transistors may be connected to each other as in the case of emitter coupling. The connection of these two transistors corresponds to the definition "NPN1: E, NPN2: E", "When the emitter terminals of NPN transistors are connected to each other, close arrangement is performed". Therefore, the CPU 2 groups both transistors that meet the close arrangement condition into one group, and stores the element number indicating the element name and the parameter indicating the characteristic of the element as the same shape designating element group in the intermediate data of the file 13. .

In addition, the two transistors forming the current mirror have the base terminal and collector terminal of one transistor connected to each other and to the base terminal of the other transistor. This connection of both transistors corresponds to the definition of "NPN1: C ・ B, NPN2: B", "When the collector and base terminals of the NPN transistor are connected to the base terminals of other NPN transistors, the adjacent arrangement is performed". To do. Therefore, the CPU 2 sets both transistors forming the current mirror into another group, and stores the element numbers of both transistors in the intermediate data of the file 13 as the close-arrangement designation and the same shape designation element. Then, when the identification processing 31 of the same-shaped element group is completed,
The CPU 2 shifts to the identification addition processing 32 of the same shaped element group.

Next, in the identification addition processing 32 for the elements of the same shape as the means for adding the identification of the elements of the same shape,
The CPU 2 extracts the elements corresponding to the close placement designation stored in the file 14. That is, the CPU 2 uses the file 1
Read out the proximity placement designation stored in 4. This proximity placement designation is performed in advance in the circuit design stage by setting elements existing in each of a plurality of circuit blocks or macros so that they are placed close to each other and have the same shape. ing. Therefore, the designated elements are formed in the same shape and are prevented from being arranged apart.

This proximity arrangement designation is defined in advance as shown in FIG. 4, for example. That is, the definition "S11, S20, S30"
Indicates that “element numbers S11, S20, and S30 on the netlist have the same shape and are arranged closely”. still,
The element numbers "S11", "S20", and "S30" are numbers corresponding to the order in which the transistors, resistors, capacitors, etc., described in the netlist are listed. In the case of (3), the elements existing in three circuit blocks are shown.

Then, the CPU 2 searches the netlist stored in the netlist file 11 for an element group consisting of a plurality of elements corresponding to the read out proximity arrangement designation. Then, when there is an element group corresponding to the netlist, the CPU 2 stores the element number of each element and the parameter indicating the characteristic of the element in the intermediate data of the file 13 as one group. Then, when the determination addition processing 32 is completed, the CPU 2 moves to element shape determination processing 33.

In the element shape determining process 33 as the element shape determining means, the CPU 2 searches the intermediate data for an element group having the same shape in advance based on the element shape designation stored in the file 15.

This element shape designation is based on the analog IC when the element shape / size is determined in each circuit block.
From the viewpoint of overall characteristics, when elements having the same shape and size (reference elements) are arranged with respect to the elements existing in each circuit block, unevenness is reduced in the shape after the arrangement, and the arrangement efficiency is improved.

That is, it is assumed that there is a transistor that allows a double current to flow in a transistor in one circuit block in another circuit block. At this time, if two transistors in one circuit block are arranged side by side with respect to a transistor that allows a double current to flow, there will be less unevenness in the shape after the arrangement. On the other hand, when the reference transistors are set to half of the transistors in one circuit block, the transistors in one circuit block have two reference transistors and the other circuit blocks have four reference transistors. When the two are arranged, the unevenness in the shape after the arrangement is reduced, and the efficiency of the arrangement is improved.

In some cases, the resistance value of one circuit block is, for example, 10 KΩ, and the resistance value of another circuit block is, for example, 5 KΩ. In this case, when viewed from the whole analog IC, it is more efficient to arrange a plurality of resistors of the same size in parallel in the resistors included in both circuit blocks. That is, the resistance of 10KΩ is 5KΩ
If two resistors are connected in series according to the magnitude of the resistance, the unevenness of the shape after the both resistors are arranged is reduced, and the arrangement efficiency is improved.

The element shape designation is defined as shown in FIG. The definition “S11: × 2” means “S11 and the element having the same shape as S11 are elements of × 2 (BIP).” That is, the elements having the same shape as the element numbers "S11" and "S11" are bipolar transistors. Due to their characteristics, a bipolar transistor of a size twice that of the basic shape is used, and a plurality of the basic shapes are arranged side by side. "S11" and "S11" are defined to form an element having the same shape.

When the element described in the element shape designation and another element having the same shape as the element exist in the intermediate data, the CPU 2 reads the parameter indicating the characteristic of each element from the intermediate data. Then, when the element is a transistor or a capacitor, the CPU 2 divides the parameter indicating the characteristic of the element by the parameter of the preset basic shape, and calculates how many reference elements are required.

For example, in the element shape designation of FIG. 5, the element number "S11" of the definition "S11: × 2" is the element number of the definition "S11, S20, S30" of the close placement designation shown in FIG. "S11"
Corresponding to. Therefore, the element numbers "S20" and "S30" correspond to elements having the same shape as "S11". The parameters indicating the characteristics of the element numbers "S11", "S20", and "S30" are set to "40", "40", and "60", respectively, and the parameter indicating the characteristics of the basic shape is set to "20". Then, the number of basic shapes that make up each element is "40", "40", "6".
Value obtained by dividing "0" by "20", that is, "2", "2", "3"
Becomes

Then, the CPU 2 updates the intermediate data by adding the number of basic shapes to be arranged to the grouped element groups (transistors etc.) on the intermediate data. At this time, the size of the element on the netlist may not be divisible by an integer with respect to the reference element size. For example, if the parameter indicating the element characteristics is "50" and the basic shape parameter is "20", it becomes "2.5" and is not an integer. In this case, the basic shape cannot be used for the device. Therefore, the CPU
2 stores the group including the element number of the element on the undivided netlist as an error in the file 21.

On the other hand, when the element described in the element shape designation is a resistor, the CPU 2 divides the resistance value of the element by the resistance value of the basic shape like the transistor and the like described above. And
If it is divisible by an integer, the CPU 2 updates the intermediate data by adding the number of basic shapes to be arranged to the element group (resistor) on the netlist.

At this time, if it is not divisible by an integer,
The CPU 2 divides the size of the element on the netlist by the reference size and divides the remainder by 1/2, 1/3, or the like. That is, in the case of resistors, when a plurality of resistors having the same resistance value are connected in parallel, the resistance value can be divided by the number of parallel connections. For example, it is assumed that a resistance of 35 KΩ is required and the reference element size is 10 KΩ. At this time, 35K
Dividing Ω by 10 KΩ gives a quotient of 3 and a remainder of 5. That is, if 3 resistors of 10 KΩ are connected in series, a resistance value of 30 KΩ can be obtained.
There is a shortage of KΩ.

Next, the CPU 2 divides the remaining 5KΩ by 1/2. Then, the value becomes 10 KΩ, and 5 KΩ can be obtained by connecting two 10 KΩ resistors having a reference size in parallel. Therefore, a resistance of 35 KΩ can be obtained by using five 10 KΩ resistors, of which three resistors are connected in series and two resistors connected in parallel to the three resistors are connected in series. That is, an arbitrary resistance value can be obtained by connecting resistors of a plurality of reference sizes in series and in parallel.

However, if too many resistors are connected in series and in parallel, the area occupied by the resistors increases and the area of the analog IC increases. Therefore, the area is prevented from increasing by setting the resistance value at a stage within a certain error range. This error range is defined by the allowable error stored in the file 16. And the definition "R
"= 99%" means "the accuracy when calculating the number of resistors is 99%". That is, the CPU 2 terminates the calculation when the sum of the resistance values of the resistors connected in series and in parallel reaches 99% or more of the designed resistance value on the netlist, and the resistance of the basic shape at that time is calculated. The number is added to each element group (resistor) on the netlist to update the intermediate data.

FIG. 6 shows the definition of the intermediate data stored in the file 13 by the above processing. Definition `` S11 (× 4),
S20 (× 4), S30 (× 6): NPN: × 2 ”means“ S11 ”and“ S20
, "S30" are NPN transistors, and
2 transistors each of the basic shape defined in
Arrange using two pieces, three pieces.

Further, "S22 (W = 40), S21 (W = 60): PMOS:"
"S22" and "S21" are P-channel MOS transistors, and their shapes are undetermined. This element number "S2
"2" and "S21" are elements that are not specified by the element shape specification of the file 15, so their shapes are not determined in the element shape determination processing 33.

Furthermore, "S41 (3K), S42 (1K), S43 (100): R: 1K
, "S41", "S42", "S43" are resistors,
The size is arranged by using a plurality of resistance sizes of 1 KΩ. When the element shape determination process 33 is completed, the CPU 2 proceeds to the element shape final determination process 34.

Next, in the element shape final determination processing 34 as the element shape final determination means, the netlist, the intermediate data, and the element correspondence designation stored in the file 17,
Based on the element automatic generation parameter stored in the file 18 and the resistance width stored in the file 19, the CPU 2
Finally determines the shape of the device. That is, the CPU 2 compares the element number of the element described in the net list of the file 11 with the element stored in the intermediate data of the file 13, that is, the element number designated by the close placement condition, the close placement designation, and the element shape designation. . Then, when the element number on the netlist is not in the designated element number, that is, in the intermediate data, the CPU 2 reads the parameter indicating the characteristic of the nonexistent element from the netlist, and the element number and the read parameter are used for the element shape. File 20 as information
To store.

When the element number on the net list is designated, that is, when the shape is described in the intermediate data, the CPU 2 determines the element number and the shape based on the element correspondence designation stored in the file 17. The element number, the number of cells used, and the cell name to be used are stored in the file 20 as element shape information. For example, the definition "S11
(× 4), S20 (× 4), S30 (× 6): NPN: × 2 ”.
Then, the CPU 2 corresponds to the definition “NPN: × 2” and defines the cell name definition “NPN:
(× 2): Read NPN2 ”. Then, the CPU 2 defines "S
11 (2), S20 (2), S30 (3): NPN: NPN2 "is stored in the file 20 as element shape information. The numbers in parentheses in the definition indicate the number of basic shapes used.

Further, when the element number on the net list is designated, that is, when the shape is not described in the intermediate data, the CPU 2 determines the shape based on the parameter indicating the characteristic of the element. At this time, when the corresponding element is a MOS transistor, a BIP transistor, and a capacitor, the CPU 2 calculates the greatest common divisor of the parameters showing the characteristics for all the elements described in the definition, and the size that becomes the greatest common divisor. Is calculated.

That is, when the size of the element is, for example, "20", "20", "30", the greatest common divisor of the size is "10". And each element is size "10"
The standard is "2 pieces", "2 pieces", "3 pieces"
It may be arranged by using them. Therefore, the CPU 2 stores the number of the element in the file 20 as the element shape information together with the element number. At this time, when the greatest common divisor is not an integer, the CPU 2 stores all defined element numbers in the file 21 as error elements.

For example, in the case of a P-channel MOS transistor, the definition of the intermediate data is "S22 (W = 40), S21 (W = 60): PMOS:".
Has not been determined in size. Therefore, the CPU 2 calculates the greatest common divisor corresponding to the element. With this definition,
The greatest common divisor is "W = 20", and the element "S22" is
There are two reference elements for "20", and the element "S21" is this "W =
The shape will be determined using three 20 "reference elements. Then, the CPU 2 uses this standard “W = 20”
The element correspondence designation definition "PMOS (W = 20): PMOS" for designating the cell name stored in the file 17 is read out.
Then, the definition `` S22 (W = 40), S21 (W = 60) with the cell name added:
"PMOS: PMOS20" is stored in the file 20 as element shape information. Therefore, the shapes of "S22" and "S21" are determined based on the size of the cell name "PMOS20".

Further, for the capacitance (capacitor), the shape can be automatically generated by the value thereof. Then, the CPU 2 calculates the greatest common denominator of the capacitance similarly to the case of the transistor, automatically generates the shape having the greatest common denominator, and determines the shape of each capacitor based on the automatically generated shape. Then, the number used for the capacitance is stored in the file 20 as the element shape information together with the element number.

On the other hand, when the corresponding element is a resistor, the shape can be automatically generated by designating the width of the resistor to be formed. The width of this resistance is preset and stored in the file 19. The CPU 2 calculates how many other resistors are needed with respect to the reference resistance value. Then, the CPU 2 obtains the area occupied by all the resistors calculated based on the required number and its shape, and calculates the reference resistor shape and the number of used resistors so that the area becomes the smallest.

That is, when there are resistances of 10 KΩ and 30 KΩ, when the resistance of 10 KΩ is used as a reference, the resistance of 30 KΩ is obtained by connecting three 10 KΩ resistors in series.
Four resistors as the reference are required. On the other hand, 30KΩ
When the resistance of 10 KΩ is used as a reference, the value can be obtained by connecting three resistances of 30 KΩ in parallel. Therefore, in this case as well, the number of resistances required is four. in this case,
Since the required number is the same, the area due to the resistance of 30 KΩ and the area due to the resistance of 10 KΩ are compared, and the resistance value with the smaller area is used as the reference.

Then, the CPU 2 defines the resistance definition stored in the intermediate data so as to be automatically generated by the resistance width of the file 19, and stores it in the file 20 as element shape information together with the reference resistance value.

In this case, the intermediate data definition "S41 (3K), S4
2 (1K), S43 (100): R: 1K "is defined by the resistance width" W = 5 "stored in the file 19 and the automatic generation definition" R :? "stored in the file 17. Definition `` S41 (3K), S42 (1K),
S43 (100): R: W = 5: 1K :? " The CPU 2 stores this definition in the file 20 as resistance element shape information.

Then, in the element shape final determination processing 34, when the element shape determination is completed for all the elements described in the net list of the file 20, the CPU 2 terminates the element shape determination processing.

As described above, in the present embodiment, in the identification processing 31 of the same-shaped element group, a plurality of elements of a plurality of types described by the element numbers of the preset netlist are set in advance in the close placement condition. Based on the above, it is determined whether or not the elements having the same shape are included in the element numbers on the netlist. When the plurality of elements are included, these element numbers are set as one group and each group is stored as intermediate data. Further, in the same-shape element group addition processing 32, a plurality of elements having the same shape are extracted on the basis of the preset proximity arrangement designation. Then, the plurality of extracted elements are set as one group, and each element number and the parameter indicating the characteristic of the element are stored in the intermediate data.

Then, by the element shape determination processing 33,
The CPU 2 inputs the element shape designation in which the basic shape designated in advance for configuring the element is defined for the element number. The CPU 2 determines whether the element number specified in the element shape designation is the element number stored in the intermediate data. And if there is a group containing the element number,
The CPU 2 divides the parameter indicating the characteristic of each element in the group by the parameter indicating the characteristic of the basic shape defined in the element shape designation. When the result of the division is that it is divisible, the quotient of the division is taken as the number of basic shapes forming each element, and the shape of the element is determined.

In the element shape determination process 33,
If the result of the division is not divisible and the element is a resistor, the remainder of division is divided by a predetermined number set in advance. The division is a resistance value within a preset error range with respect to the resistance value, which is a parameter indicating the characteristic of the element when the resistance value of the element is formed by the quotient of the result of the division and the basic shape parameter. Is divided until. Then, the quotient until reaching the error range is set as the number of basic shapes forming each element, and the shape of the element is determined.

Further, in the element shape final decision processing 34, when the element number of each group stored in the intermediate data is not in the element number specified in the element shape designation and the element is a transistor or a capacitor. , The greatest common divisor of the parameters showing the characteristics of each element having the same shape is obtained, and the element having the greatest common divisor is used as a reference. Then, the number of reference elements is obtained for the characteristics of each element, and the shape of each element is determined based on the reference elements and the number thereof. On the other hand, when the element is a resistor, each resistor is used as a reference size, and the total area when the shape of each resistor is automatically generated based on the reference size is obtained. And
The number of elements to be formed is calculated based on the reference size when the total area is the smallest, and the shape of the element is determined by the reference size and the number of elements forming each element.

As a result, the shape of the element in the macro described in the netlist of the file 11 can be automatically determined, and the element layout can be automatically performed using this determined element shape. Further, since the elements are arranged based on the close arrangement condition and the element arrangement condition of the elements, it is possible to perform the element arrangement satisfying the analog constraint.

The present invention may be carried out in the following modes other than the above embodiment. (1) In the above-described embodiment, the identification addition processing 3 of the same-shaped element group is performed based on the close placement designation stored in the file 15.
Although the second group synthesizing process is performed in step 2, it is also possible to perform the second group synthesizing process without identifying the adjacent placement specification and omitting the process 32 of identifying and adding the same-shaped element group.

(2) CAD for designing the circuit of the above embodiment
It may be implemented by being incorporated in the device. By adding a graphic display to the configuration of the layout device shown in FIG. 2, the configuration becomes similar to that of the CAD device and the incorporation into the CAD device becomes easy.

Further, it may be carried out by incorporating it in a device for arranging elements. If the format of the element shape information of the file 20 is the same as the format input to the device for arranging the element, the element can be efficiently arranged.

Further, in addition to the magnetic disk device 4 and the magnetic tape device 7, various storage devices such as a magneto-optical disk device and a CD-ROM device are connected to the shape determining device 1 so as to connect the program data and the files 11 to 11. 21 may be stored.

(3) In the above embodiment, each file 1
1 to 19 are carried out without being read into the memory 3. Further, the files 20 and 21 may be directly written in the magnetic disk device 4 or the like without being set in the memory 3. With this configuration, the memory 3 can be downsized.

[0063]

As described in detail above, according to the present invention,
There is an excellent effect that the shape of the element that satisfies the analog constraint can be automatically determined.

[Brief description of drawings]

FIG. 1 is a process flow diagram of a shape determination device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a configuration of a shape determining device according to an embodiment.

FIG. 3 is a diagram showing an example of a circuit condition of a close arrangement.

FIG. 4 is a diagram illustrating an example of proximity arrangement designation.

FIG. 5 is a diagram showing an example of element shape designation.

FIG. 6 is a diagram showing an example of intermediate data.

FIG. 7 is a diagram showing an example of an allowable error.

FIG. 8 is a diagram showing an example of element correspondence designation.

FIG. 9 is a diagram showing an example of element automatic generation parameters.

FIG. 10 is a diagram showing an example of element shape information.

[Explanation of symbols]

 2 CPU 11 file (netlist) 20 file (element shape information) 31 identification means for elements of the same shape 33 element shape determining means 34 element shape final determining means

Claims (6)

[Claims] 1. A method for determining the shape of an element in an analog LSI for determining the shapes of a plurality of types of elements described by element numbers in a preset netlist, the proximity being set in advance so as to have the same shape. By inputting the placement condition, it is judged whether or not there are a plurality of elements corresponding to the close placement condition on the netlist. If there are a plurality of elements, these element numbers are set as one group and each group is set as intermediate data. The element shape designation in which the basic shape designated to configure the element is defined in advance for the element number is input, and the element number in the element shape designation is stored in each of the intermediate data. If there is an element number in the group, it is judged whether or not there is an element number, and if there is an element number, the parameter showing the characteristic of each element in the group is The shape of an element in an analog LSI that divides each and determines the shape of the element by taking the quotient as the number of basic shapes that make up each element when the quotient is an integer as a result of the division. How to decide. 2. The method for determining the shape of an element in an analog LSI according to claim 1, wherein when the result of the division is not divisible and the element is a resistor, the remainder of the result of division is set in advance. When the resistance is formed by dividing the quotient of the division result and the resistance value of the basic shape, the resistance value, which is a parameter indicating the characteristics of the element, is a preset error Divide until the resistance value of the range is reached, and use the quotient of the result of the division that becomes the resistance value of the error range as the number of basic shapes forming each element to determine the shape of that element. Shape determination method. 3. The analog LSI according to claim 1 or 2.
In the method of determining the element shape according to the above, when the element number in each group stored as the intermediate data is not in the element number specified in the element shape designation, and the element with the element number is a transistor or a capacitor, , Find the greatest common divisor of the parameters that show the characteristics of each element with the same shape, find the number of the elements to be used corresponding to the characteristics of each element as the reference, and The shape of the element is determined by the element and the number of elements serving as the reference. When the element is a resistor, the size of one of the resistance values is used as the reference size, and each resistance is automatically generated based on the reference size. In this case, the total area is calculated, and the number of elements to be formed with the reference size when the total area is the smallest is calculated. Shape determination method for the device in an analog LSI which is adapted to determine the shape. 4. An apparatus for determining the shape of a constituent element in an analog LSI for determining the shape of a plurality of types of elements described by element numbers in a preset netlist, which is set in advance to have the same shape. The close placement condition is input, and it is determined whether a plurality of elements corresponding to the close placement condition are on the netlist. If there are a plurality of elements, these element numbers are set as one group and each group is The identification means (31) of the same shape element group to be stored as intermediate data and the element shape designation in which the basic shape designated to configure the element is defined in advance for the element number are input, and the element shape designation is performed. It is determined whether the element number in is in the element number in each group stored in the intermediate data, and if there is an element number, the characteristics of each element in the group are indicated. The parameter is divided by the parameter that shows the characteristics of the basic shape, and if the quotient is an integer as a result of the division, the quotient is defined as the number of basic shapes that make up each element An element shape determining device in an analog LSI, comprising: determining means (33). 5. The device for determining the element shape in an analog LSI according to claim 4, wherein the element shape determining means (33) is used when the result of the division is indivisible and the element is a resistor. Is a parameter obtained by dividing the remainder of the result of division by a predetermined number set in advance, and the resistance value when the resistance is formed by the quotient of the result of the division and the resistance value of the basic shape is a parameter indicating the characteristics of the element. The division is performed until the resistance value reaches a resistance value within a preset error range for a certain resistance value, and the quotient of the results of the division that results in the resistance value within the error range is taken as the number of basic shapes forming each element A device for determining the shape of an element in an analog LSI for determining 6. The analog LSI according to claim 4 or 5.
In the device shape determining device in, when the element number in each group stored as the intermediate data does not correspond to the element number specified in the element shape designation, and the element with the element number is a transistor or a capacitor. Is the greatest common divisor of the parameters showing the characteristics of each element having the same shape, with the element having the greatest common divisor being the reference, the number of reference elements to be used corresponding to the characteristics of each element,
The shape of the element is determined by the reference element and the number of the reference elements. When the element is a resistor, the size of one of the resistance values is set as the reference size, and each resistance is determined by the reference size. Calculate the total area when automatically generated, calculate the number of each element to be formed with the reference size when the total area is the smallest, and determine the shape of the element by the reference size and the number of forming each element A device for determining the shape of an element in an analog LSI provided with a final determining means (34) for determining the element shape.