JPH09167170A - Design method for electronic circuit, design method for semiconductor memory and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically execute the collective processing of the whole and an equivalent verification processing in the design of an electronic circuit having regular structure. SOLUTION: The regular repetitive structure part of the electronic circuit on a semiconductor memory is decided in a system with a minimum restriction which can decide general regularity as a regular structure mode. An item which can be changed with individual data is decided with individual data as structure definition information 2. Thus the degree of freedom is given to individual data and regularity can be defined. The electronic circuit is designed so that regularity is satisfied. Thus, data for verification 5 and 6 obtained by reducing data quantity can be obtained by setting the number of repetition times of regular repetitive parts to a desired one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effectively applied to a circuit design, a logic design, a layout design, a test pattern design, etc. of an electronic circuit having a regular repeating structure such as a semiconductor memory and a liquid crystal display panel. is there.

[0002]

2. Description of the Related Art A semiconductor memory can be mounted in high density because of its high regularity of circuits and patterns. Therefore, if the whole is handled collectively, the data for verification reaches tens of gigabytes for tens of megaelements.
The data amount exceeds the practically processable range. For this reason, in semiconductor memory, it is necessary to pay attention to the regularity and reduce the amount of target data to a realistic scale before evaluating logical simulation, circuit simulation, design rule check, etc. come. At this time, no effective technique has been provided so far regarding how to reduce the target data. Therefore, it is necessary to partially separate the constituent elements of the circuit, newly create verification data, and perform verification using this.

[0003]

As described above, the data for specifying a circuit such as a semiconductor memory is divided and subjected to verification processing without batch processing, so that the data amount of one processing unit can be reduced. Although it can be reduced, there is a problem that the overall processing time for verification is further increased. Therefore, it is realistic to manually delete the target data and perform various verifications using this data. However, in the process of deleting this data,
Problems such as mistakes such as deleting necessary parts, pseudo errors due to improper deletion, and insufficient checking may occur. For this reason, compression of data by extracting the rule structure and creating only one identical data and sharing the repeated part has also been considered. However, in order to extract this repetitive structure, it is necessary to expand the entire data and then extract the regular structure, which requires a huge amount of processing time and creates all the verification data. It takes a lot of time to perform, and it is also difficult to automatically check the extracted structure in the system when it is incorrect. It was revealed by the present inventor that it cannot be streamlined.

A silicon compiler (GDT) of Mentor Graphic Co., Ltd. is a system for predefining arrangement information of parts having a regular structure (hereinafter referred to as cells), and generating overall design data according to the arrangement information. . However, since these products do not have the idea of a model with a regular structure, it requires a huge amount of man-hours to create one definition, and data generation is possible, but the amount of data for checking is reduced. It was found that the scale of less than one-thousandth of the current memory products is the limit when including the check of the generated data without considering the above.

An object of the present invention is to verify an electronic circuit having a regular structure, by utilizing its regularity, a verification process equivalent to processing the whole that could not be realized conventionally in a lump. Is to be able to do automatically.

Another object of the present invention is to create data for verification by omitting a part of data of a regular structure part,
Conventional problems such as a mistake that deletes necessary parts in deleting data for omission or a false error due to improper deletion, or insufficient check due to insufficient data deletion man-hours It is to solve the problem and shorten the development period and the development man-hour of an electronic circuit having a regular repeating structure.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, for a regular repeating structure portion (mat) in an electronic circuit such as a semiconductor memory, the system defines a minimum constraint that can determine general regularity as a regular structure model. Items that can be changed in individual data are defined as individual pieces of structure definition information. Thereby, it is possible to define the regularity while giving each individual data a degree of freedom. The electronic circuit is designed so as to satisfy this regularity. Therefore, the regularity can be uniquely extracted with respect to the regular repeating portion in the electronic circuit having the repeating structure portion. Therefore, according to the regularity defined by the regular structure model, it is possible to obtain the verification data in which the data amount is reduced by setting the number of repetitions of the regular repeating portion as desired. The basic rule of the regular repeated part is the same whether the repeated part is the whole data as it is or the verification data with the repeated part omitted as desired. The design rule check can obtain a result substantially equivalent to the case where the whole is checked at once.

Further, since the verification data is generated based on the same cell definition and the same cell data as the generation of the whole data, a correction error or the like of the data can be eliminated.

In addition, the two-dimensional array coordinates and the area coordinates of a mat having a free size can be determined in the same manner, and in order to check the boundary between the mat and other areas, the specification of only the boundary area can be automated. Further, by changing the structure definition information, it is possible to similarly create a mat having a different number of two-dimensional arrays, used cells, the number of repetitions, etc. from the same constitutive model of the mat.

As a result, it is possible to automatically generate the data of the entire mat based on the structure definition information while eliminating a long manual processing time and mistakes. It is possible to reduce the amount of target data by automatically generating matte data that omits the regular part and only includes the necessary part, and realizes a verification process that is equivalent to the case of the whole target and high-speed. it can. Not only can the data be generated, but it is possible to automatically generate the information of the regular structure, for example, the area coordinates and the like from the structure definition.

A more detailed description will be given. Most of the target data is in the mat. Therefore, in order to complete the processing within a practical time, the point is to efficiently handle the mat data. Since the data in the mat has a regular structure, only a part of it is verified,
It is possible to use the result repeatedly for the remaining part, but it is important to separate the part required for processing from the part that can be omitted. Therefore, the system is to set the regular structure model of Matt. The rule structure model consists of a cell layout configuration, necessary items for various cells, and an abbreviation method when using regularity. According to this rule structure model, specific cell layout information (data name, number of repetitions, etc.) is created as a mat structure definition, which is required from this structure definition and the design data of the elements (cells) used in the structure definition. It is designed to generate various design data and verification data.

In the above process, first, design data of the above structure definition and elements used in the structure definition is created. At this time, the necessary data items are clear from the rule structure model, and by making the input in a conversational format using the graphic user interface, the editing operation is simplified and the creation errors are prevented by automatically checking for missing data and inconsistencies. Is possible.

Next, data inside the mat is created according to the created structure definition. When the verification processing is performed inside the mat, only a part (a few pieces) of the rule area defined by the rule structure model is generated and the verification processing is performed. Since the amount of data to be processed is about 10 to 1000 times the amount of data of the entire mat, the verification process can be completed within a practical time.

Further, when the verification processing is performed in consideration of the outside of the mat, it is necessary to perform processing including the boundary between the mat and the outside of the mat, and only the data determined to be necessary as boundary data in the regular structure model. Is generated and verification processing is performed. At this time, the necessary data in the mat is only the data for checking the boundary part in the entire mat, and can be 1% or less compared with the data of the entire mat.

In this way, by dividing into the inside of the mat, the outside of the mat, and the boundary portion, it is possible to carry out the processing equivalent to the whole batch. The processing resources are
Considering that usually one or more mats of one kind are used, the processing inside the mat is required for only one, and the total verification can be performed with a data amount of 1/10 to 1 / 10,000 or less.

Further, in the optical comparison inspection in the inspection process of the product, it is necessary to specify the coordinates or the position of the regular structure portion. Conventionally, a person should read and judge the position from the pattern, or program the data structure. It has been necessary to analyze and extract the regularity to create coordinate information. Conventionally, there is a problem that it takes time to automate the regularity extraction and the efficiency is low. However, in the above means, the structure definition information itself is the regularity information itself to be extracted, and the regularity is automatically grasped with almost no processing time, and the necessary verification processing data is created. You can

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

<< System Configuration >> FIG. 1 shows an example of a system configuration for implementing the method for designing a semiconductor integrated circuit according to the present invention. In this system, when designing a semiconductor integrated circuit having a physical and logical regular structure such as a semiconductor memory, a regular structure model is preliminarily defined by the system for this regular structure portion (called mat). By having the structure definition information corresponding to the regular structure model and the design data of the elements used in this structure definition information, the mat design data corresponding to the structure definition information is automatically generated.

The system shown in FIG. 1 is a structure definition for editing and checking cell data (cell data) 3 and structure definition data (data for forming regular structure data) 2 which are element parts which form a mat. An editing unit (including a structure definition editing program) 1, a data generation unit (including a data generation program) 4 for creating in-mat data 5 and mat boundary data 6 from the cell data 3 and the structure definition data 2 are further included. The data processing means 8 includes a program group for inputting the inner data 5, the mat boundary data 6, and the non-mat data 7 and performing various checks and data conversions. Of these, the cell data 3, the in-mat data 5, the mat boundary data 6, and the out-mat data 7 are circuit data which is an input format of circuit simulation, logical data which is an input format of logic simulation, mask pattern data which represents a mask pattern figure, and the like. These are various data used in the design and verification of the semiconductor integrated circuit. The out-of-mat data is manually created data. The mat boundary data 6 is data at the boundary between the in-mat data 5 and the out-mat data 7.

When the purpose of checking the inside of the mat is to generate the entire design data, the data generating means 4 automatically determines data that can be omitted from the structure definition model for the regular repeating portion. However, it is possible to create the in-mat data 5 in which only the necessary parts are created as data, and the regularly repeated parts are omitted.
Similarly, the data generating means 4 automatically determines the optional data from the structure definition model when the purpose is to check the boundary between the mat and the outside of the mat when generating the overall design data. Only the necessary portion can be created as the boundary data 6. For example, assuming that the entire design data of one mat is (A) of FIG. 2, the in-mat data 5 in which the repeated portions are omitted can be (B) of FIG. The in-mat data 5 is used as verification data for logic design, circuit design, and layout design, for example. The entire design data of one mat as shown in FIG. 2A and the in-mat data 5 omitting the regular repeating portion as shown in FIG. 2B have the same structure definition. According to (structural rules), the only difference is whether or not the repeated portion is omitted. Therefore, the logic verification and the design rule check based on the in-mat data 5 with the regular repeated portion omitted. Various verifications such as are equivalent to verifications based on the corresponding whole data.

Although the overall design data is not shown in FIG. 1, the overall design data in the mat can be obtained if the structure definition model is not omitted for the regular repeating parts. In the actual mask pattern creation,
The entire design data in the mat and the data outside the mat are used.

FIG. 3 shows a block diagram of the structure definition editing means 1 and the data generating means 4. These means are the CPU 13 that constitutes a small-to-medium-sized computer or a large-sized computer,
The memory 14, the input device 15, the display device 16, and an external storage device 9, 10, 11, 12, 22 such as a hard disk. The external storage device includes a load module file 9 for storing programs, a structure definition file 10 for storing structure definition data 2, a cell data file 11 for storing cell data 3, a work data file 12 for use during execution, and generated data 5 Or a generated data file 22 storing 6 is included. At the time of execution, the load module file 9, the structure definition file 10, the cell data file 11, and the work data file 12
Are read into the load module 17, the structure definition table 19, the cell data table 20, and the work table 21 on the memory 14, respectively. In the present embodiment, the rule structure model 18 is defined in the load module, but it is not necessarily limited to this, and a method of storing it in an external storage device and reading it at the time of execution is also possible. Also load module 17
It is possible to have it explicitly as a table in the table as well as implicitly express it by coding. It is also possible to have a plurality of models and select which model to use when using.

<< Regular Structure Model >> Next, the regular structure model 18 will be described. FIG. 4 shows an example of a hierarchical structure of a structure definition model applied to, for example, a semiconductor memory as a semiconductor integrated circuit designed using the above system.
According to the hierarchical structure shown in the figure, the highest layer is called a chip. The chip consists of a memory mat, an intermediate peripheral, and an indirect peripheral. In the present embodiment, the objects of the structure definition are the memory mat and the intermediate periphery. That is, the memory mat and the middle periphery have a regular structure part (mat) having a regular repeating part.
Is taken as an example. In the following description of the embodiments, when simply referred to as a mat, it means a memory mat and an intermediate periphery. The memory mat and the middle periphery do not have to be directly arranged, and there may be further middle layers. The memory mat consists of a memory array and a direct peripheral. The memory array consists of memory cells and connected cells. The immediate periphery consists of single-placed cells and array-placed cells. The middle periphery consists of single placement cells and array placement cells. FIG. 5 schematically shows the hierarchical structure of the semiconductor memory as a chip image. 30 is a chip, 31 is an indirect peripheral, 32 is a memory mat, and 35 is an intermediate peripheral. Inside each memory mat 32, a memory array indicated by 33 and a direct peripheral indicated by 34 are arranged.

Although the hierarchical structure of FIG. 4 defines that there is no intermediate hierarchy between the memory mat, the middle periphery, the memory array, the direct periphery, the memory cell, the connection cell, the single arrangement cell, and the array arrangement cell, It is not necessarily limited to this, and an intermediate layer may be provided. It is also possible to make the middle layer free and give each cell a type. Further, it is possible to define a nest structure in which the memory mat and the intermediate periphery are placed in the memory mat. What is needed is to clarify the configuration of each cell. Each component will be described below.

<< Cell Specifications >> First, cell specifications will be described. The cell frames of all the following cells are rectangular (figures inside cells may extend outside the cell frame). All cells may exist in plural types.

(1) Memory cell: The memory cell is included in the memory array 33 and is always arranged two-dimensionally. One two-dimensional arrangement of memory cells is called a memory field. Memory cell repeat pitch (px, py)
Must all be the same. In FIG. 6, which shows an example of the memory array, 40 is the memory field.

(2) Connected cells in the X direction: Connected cells in the X direction are included in the memory array 33 and are arranged one-dimensionally in the X direction. The repetition pitch is all px.
In FIG. 6, 41X is an array of the connecting cells in the X direction.

(3) Y-direction connected cells: Y-direction connected cells are included in the memory array 33 and are repeatedly arranged in the Y-direction one dimension. Repeat pitch is py. FIG.
42Y is an array of the connecting cells in the Y direction.

(4) Corner connecting cell; The corner connecting cell is included in the memory array 33, and is arranged only one differently from the adjacent cells. In FIG.
3. The X-direction connected cells (included in the array 41X) excluding the outermost edge of the memory array are, for example, intersecting cells for switching the left and right of complementary bit lines. The connection cells in the Y direction (42Y included in the array) excluding the outermost edge of the memory array are made of aluminum wiring parallel to the polysilicon wiring layer forming the gate of the selection MOS transistor of the memory cell in the word line of the word shunt structure. It is used as a contact cell for connecting to. An array of connected cells 41 surrounding the outermost edges of a number of matrix arranged memory fields.
Although X, 42Y, and 43 are the same as the memory cells, they do not actually function as a circuit, and the etching rate changes at the outermost edge where the regularity of the arrangement is interrupted, compared to the inside, so the pattern due to this Can be positioned as a cell to absorb the change in the circuit portion that is not substantially used.

(5) Array-arranged cell: The array-arranged cell is a cell which is repeatedly arranged one-dimensionally in the X or Y direction to form the direct periphery 34 or the intermediate periphery 35. The direct peripheral 34 constitutes a peripheral circuit for a memory mat directly corresponding to the direct peripheral 34, for example, a sense amplifier or a row decoder. The intermediate peripheral 35 constitutes a peripheral circuit common to a plurality of memory mats, for example, a mat selection decoder or a predecoder (global decoder) for selecting a memory mat. The indirect peripheral constitutes, for example, an external input / output buffer and a timing generator.

(6) Single-placement cell: A single-placement cell is a cell that is placed as a cell for connecting the array-placement cells, and forms a direct periphery or an intermediate periphery together with the array-placement cells. Cells.

<< Structure of Memory Array >> FIG. 6 shows the structure of the memory array 33. The cell frames of the cells are in contact with each other on the line so that there is no gap. The cell frame of the entire memory array is rectangular.

(1) Arrangement of memory cells: One or more of the memory fields 40 can be arranged in the X and Y directions, and they are arranged in a grid pattern without omission. The number of memory cells used in one memory array is limited to one.
The memory cell can be mirror-inverted for each memory field. In each memory field lined up in the X direction,
The number of repetitions in the Y direction / the Y coordinate of the cell frame are all common. Similarly, the memory field of each row arranged in the Y direction is X.
The number of repetitions in the direction and the X coordinate of the cell frame are all common.

(2) Arrangement of the connecting cells in the X direction; one kind of connecting cells in the X direction (included in the array 41X) is always arranged on the upper and lower sides of each memory field 40 (there is also one kind between the memory fields). . Allow multiple types of cells within a memory array (cells may be the same or different depending on location). In addition, the number of times the connected cells are repeated in the X direction and the X coordinate of the cell frame are the same between adjacent memory cells.

(3) Arrangement of connecting cells in the Y direction; one kind of connecting cells in the Y direction (included in the array 41Y) is always arranged on the right and left sides of each memory field 40 (one type between the memory fields). And). The presence of multiple types of Y-direction connected cells in one memory array is recognized (the cells may be the same or different depending on the location).
Then, the number of repetitions of the connecting cells in the Y direction and the Y coordinate of the cell frame are the same between the adjacent memory cells.

(4) Arrangement of corner connecting cells: The corner connecting cells 43 are always arranged outside the four corners of the memory field 40 in contact with the connecting cells in the X and Y directions. Confirm the existence of multiple types of corner connecting cells in one memory array (the cells may be the same or different depending on the location).

As described above, in this embodiment, in order to structurally simplify the designation of the repeating pitch, the cell frame is always provided and the cells are arranged without any gaps. However, the cell frame is not provided and the repeating pitch is structured. A method of specifying by definition is also possible. Although it is possible to use multiple types of memory cells and change the number of repetitions and the repetition pitch of the memory cells in the memory field, all repetition pitches lined up in each of the X and Y directions can be expressed by a positive number ratio. , The width of each memory field must be common. It is assumed that the connecting cells must be one column and the pitch must be the same as that of the memory cells, but it is also possible to determine that this also has the number of columns and a plurality of columns and the pitch may be different from the memory cells. However, it is necessary that all the repeating pitches lined up in each of the X direction and the Y direction can be expressed by a positive number ratio. Although the memory cell is always defined as a two-dimensional array, it is not always necessary and the X-direction array can be expressed as a Y-direction array in a nested manner. Further, there may be a hierarchical structure below each cell.

<< Structure of Memory Mat >> FIG. 7 shows an example of the structure of the memory mat. The cell frames of each cell are in contact with each other on the line and there is no gap. The cell frame of the entire memory array is rectangular.

(1) Arrangement of Memory Array; As the arrangement of the memory array 33, it is assumed that there is one arrangement shown in (A) or two arrangements shown in (B). In the case of two arrangements, the two memory arrays 33 are the same as each other,
Since the middle periphery 35 of the central portion is shared by the left and right memory arrays 33, the pattern figure of one memory array 33 is always subjected to Y-axis mirror inversion, and the Y coordinates of the arrangement are the same.

(2) Arrangement in the X-direction direct periphery: One kind of the X-direction direct periphery 341 is arranged above and below the memory array 33 as required (not essential). When there are two memory arrays 33, it is assumed that the upper and lower memory arrays 341 have the same direct peripheral portions 341 in the X direction, Y axis mirror reversal is always applied to one of them, and the Y coordinates of the arrangement are the same. In the X-direction direct periphery 341, a plurality of cells for the X-direction direct periphery are arranged in a line in the X direction.
The heights of the cells that form one direct periphery 341 in the X direction are the same. There are two types of cells that form the direct periphery 341 in the X direction: a single arrangement cell and an array arrangement cell in the X direction. The single arrangement cell has the same cell frame X coordinate as the corner connecting cell 43 of the adjacent memory array. The array-arranged cell has the same cell frame and X-coordinate as the X-direction connecting cell (included in 41X) of the adjacent memory array 33,
The repetition pitch is an integer multiple of px.

(3) Arrangement in the Y-direction direct periphery: One type of the Y-direction direct periphery 342 is arranged on the left and right sides of the memory array 33, if necessary (not essential). When the number of memory arrays 33 is 2, the peripheral area 3 directly in the Y direction at both ends 3
42 may be the same, and in this case, one side is always subjected to Y-axis mirror inversion, and the Y coordinates of the arrangement are the same. The Y-direction direct periphery 342 has a plurality of cells arranged in a line in the Y-direction. One Y-direction direct periphery 342
The widths of the cells that make up are common. Around Y direction 34
There are two types of cells that make up 2; a single array cell and an array array cell in the Y direction. The single arrangement cell has the same cell frame and Y coordinate as the corner connecting cell 43 of the adjacent memory array 33. The repeated array-arranged cells have the same cell frame and Y coordinate as the Y-direction connected cells (included in 42Y) of the adjacent memory arrays, and the repeating pitch is an integral multiple of py.

(4) Arrangement around the corners directly around the corners; the corners around the corners 343 are arranged outside the four corners of the memory array 33 so as to be in contact with the immediate surroundings in the X and Y directions, one by one. It is arranged only when there are both the direct surroundings 341 and 342. 2 memory arrays 33
In the case of the memory mat, the corner direct periphery 343 between the upper ends of the memory mat and the lower ends of the memory mat may be the same. become.

In the above, the number and type of memory arrays and the mirror inversion according to the need of the memory array, the number and types of the direct surroundings and the mirror inversion according to the need of the direct surroundings, and the width of the single connected cell The number of cells and the necessity of corner connecting cells are not necessarily limited to the above-mentioned definition, and it is sufficient that the structure of the memory mat can be clarified.

<< Structure of Intermediate Periphery >> FIG.
5 is shown. The cell frames of each cell are in contact with each other online and there is no gap. It is assumed that the cell frame around the entire middle is rectangular. There are two types: an intermediate periphery in the X direction (an intermediate periphery in the X direction) and an intermediate periphery in the Y direction (an intermediate periphery in the Y direction).

(1) X-direction middle periphery: A plurality of cells are arranged in a line in the X-direction in the X-direction middle periphery.
The heights of the cells forming one peripheral portion in the X direction are the same. There are two types of cells forming the middle portion in the X direction, that is, a single arrangement cell and an array arrangement cell in the X direction. The single arrangement cells and the array arrangement cells are alternately arranged (single arrangement cells at both ends). The array-arranged cells have the same repetition pitch as the cells within one middle periphery. Single placement cells may all be different or only some of the same cells may be placed within one middle perimeter.

(2) Y direction middle periphery: A plurality of cells are arranged in a line in the Y direction in the Y direction middle periphery.
The heights of the cells constituting one Y-direction middle periphery are all the same. There are two types of cells forming the middle portion in the Y direction: a single arrangement cell and an array arrangement cell in the Y direction. The single arrangement cells and the array arrangement cells are alternately arranged (single arrangement cells at both ends). The array-placed cells are all the same in repeat pitch as the cells within one middle perimeter. Single placement cells may have all different or some of the same cells placed within one intermediate perimeter.

As described in this example, the single-arrangement cells and the array-arrangement cells are alternated, both ends are single-arrangement cells, and the array-arrangement cell type and the repeating pitch are one kind. Can be changed to another rule as long as the structure definition around the middle is clear.

<< Terminal Name Rule >> Next, the definition of the terminals in the memory mat and the peripheral area will be described. First, wiring on the memory mat and the middle periphery (sky wiring) is prohibited. However, it is possible to wire over the layers only in a layer that does not have a connection relationship with the memory mat and the middle periphery. From this, the terminals of the memory mat and the intermediate periphery are the outermost sides of the memory mat and the intermediate periphery among the terminals of the cells forming the memory mat and the intermediate periphery. The input / output attribute of each terminal is the same as the attribute of the cell terminal, and the terminal name is automatically named based on the cell terminal name. There are the following two types of this terminal, and the naming rule of each terminal name is shown below.

(1) No naming rule (mainly non-repeatable terminals such as power supply terminal, mat select terminal, R
/ W terminal or the like for a single control signal terminal); in this case, the terminal name is the same as the cell terminal name. If there are multiple identical terminal names, consider each as an equivalent terminal (all terminals requiring external connection).

(2) There is a naming rule (mainly for repeatable terminals such as address signal input terminals, data signal input / output terminals, etc.); in this case, as illustrated in FIG. , The cell terminals are divided into groups with the same name on the upper, lower, left, and right sides, and each group is numbered according to the specification of the coordinate value order. At this time, the naming format for the terminals is, for example, the terminal name # number of the cell as the terminal name. The specified content can be a target cell name (s), a terminal name, the number of digits, a start value, an end value, an increment, decimal / hexadecimal, and a target terminal range. Equivalent and equipotential terminals cannot be used.

In the present embodiment, the terminal name and its naming rule are not indispensable, and can be omitted when it is not necessary to carry out one of the verifications described later that requires a terminal. Further, the terminal name format in the terminal naming rule is not limited to the above format, and the format is not particularly limited as long as it can identify all, for example, give different names individually. Furthermore, according to the naming rule for terminal names, groups are created according to the cell terminal names, but it is also possible to group multiple terminals of the cell into the same group or conversely divide one terminal of the cell into multiple groups. With, you can specify different pin names for each group, which improves the freedom of naming.

<< Definition of Address Allocation of Decoder >> As an end of the rule structure model, the address allocation definition of the decoder will be described. FIG. 10 shows an example of the address allocation definition of the decoder. Decoder directly around 3
4 and intermediate perimeter 35 only. The decoder is a decoder basic circuit cell 50 and a decoder perforation cell 5.
It shall be composed of 1. Decoder basic circuit cell 50
Has a decoder basic circuit for a plurality of addresses and terminals at a perforated position and a decode output position. The decoder perforation cell 51 has an input address line and perforation data, and is connected to the decoder basic circuit cell 50 at the same origin to connect the address input to the decoder basic circuit cell 50. The number of addresses to be perforated is equal to the number of addresses of the decoder basic circuit cell 50. When the high-order address / the low-order address is divided into the perforations, a plurality of decoder perforation cells 51 can be overlapped on one decoder basic circuit cell 50. The target address of each perforated cell 51 is called an address group. There are a plurality of perforated cells 51 in each address group depending on the combination of connections, and they are distinguished by the decoder cell number. Correspondence between the decoder perforated cell name, the decoder basic circuit cell name, the address group name, and the decoder cell number is defined by the structure definition. The decoder perforation cells 51 are sorted by the coordinate value for each decoder basic circuit cell 50 and arranged according to the designation. The specified contents are the address group name of the target, the order of the decoder cell number to be arranged → ascending order (1 → N, 1 → N) and alternate (1 → N, N
→ 1) Specify the number of repetitions of the same decoder cell and the range of the target decoder basic circuit cell.

<< Structure Definition Information >> Next, the structure definition information will be described. Structure definition information in the case of following the rule structure model described above is shown in FIGS. These figures show the logical structure, and the relation of the items of each data is represented by the direct product (×), direct sum (+) and repetition (*) of the regular expression. Direct product indicates that higher order data is created by a set of lower order data, and direct sum means that higher order data is created by any one of the lower order data,
Repetition means that upper data is created by a plurality of lower data. 12 and 13 are connected to each other at a symbol & 1 portion and a symbol & 2 portion.
As shown in FIG. 11, the structure definition information includes a block structure definition, a terminal definition, and a decode definition. As shown in FIGS. 12 and 13, the block structure definition includes a memory mat and an intermediate periphery. By combining this structure definition information with the above-mentioned rule structure model, information for generating matte data is completed.

For example, the memory array of structure definition information is
As shown in FIG. 12, an X-direction memory field configuration (the number of memory fields, a memory cell arrangement number for each memory field), a Y-direction memory field configuration (a memory field number, a memory cell arrangement number for each memory field),
It consists of individual memory array elements. The element is provided with an element position sequence number or an element type as a sequence number or a coordinate number that increases from the lower left to (0, 0) in the upper right direction for each element. The element type is any one of a memory field, an X-direction connection, a Y-direction connection, and a corner connection. Then, it has an arrangement cell name corresponding to an element of that type and information as to whether or not mirror inversion is performed.

The mat type of the structure definition information is specified by ARY1 and ARY2 as shown in FIG. 7A or 7B.

The direct periphery of the structure definition information has information on the X direction, Y direction, and corners, as shown in FIGS. The X direction has an upper element and a lower element, and each element has an element position sequence number as a sequence number or coordinate number that increases in the upper right direction with the lower left as (0, 0), and the element type. Equipped with. The types of elements are either single arrangement or repeating (array arrangement). Then, it has an arrangement cell name corresponding to an element of that type and information as to whether or not mirror inversion is performed. The Y direction has elements on the left, elements in the middle, and elements on the right, and these elements are individually provided with single placement or repetition as described above, and the placement cell name and mirror inversion information. The corner has an upper left element, a lower left element, an upper element, a lower element, an upper right element and a lower right element, as shown in FIG.
Each of them has an arrangement cell name and mirror inversion information.

As shown in FIG. 13, the middle periphery of the structure definition information has information in the X direction or the Y direction, and the information in the X direction is the X direction array configuration (the number of arrays, the number of cells arranged in each array). And element information, and each element has an element position sequence number as a sequence number or coordinate number that increases in the upper right direction with the lower left as (0, 0), and the element type. The type of the element is a single arrangement or an array arrangement, and has an arrangement cell name corresponding to the element of that type and information on whether to perform mirror inversion. The same applies to the Y direction.

As shown in FIG. 11, the terminal definition is made up of element block names, that is, arrangement cell names, terminal names and number definitions. The number definitions consist of the number of digits, start position, and
It has information about the end value, increment, notation and target range.

As shown in FIG. 11, the decode definition has the necessary number of pieces of information on the basic circuit block name, the connection definition, and the connection rule. The connection definition has an address group name such as an upper address or a lower address and information about a connection block, and the connection block information includes a required number of information about the connection order and a block name corresponding to the connection order.
The connection rule also includes address group names and arrangement rule information, and the arrangement rule information has a required number of repetition types (for example, ascending order or alternate), the number of repetitions and the target range.

<< Structure Definition Editing >> FIGS. 14 to 16 show examples of setting screens on the display means (not shown) for performing the block structure definition, the decoder definition and the terminal definition. For example, on the screen shown in FIG. 14, the name of each cell, arrangement information, and repetition information are specified.
Various settings are made by the graphic user interface. The structure definition once set is also corrected on the setting screen as shown in FIG. 14, but the element cell may need to be modified along with the modification of the structure definition. For example, when the array pitch of cells is changed in the structure definition, it may be desired to change the size of cells or the like accordingly.

FIG. 17 shows a system configuration focusing on the editing of the structure definition in consideration of making it possible to modify the element cell. A control means 60 is provided for referencing the contents of the structure definition table 19 generated by the structure definition editing means 1 and for editing layout elements. The control means 60 sets the edit mode of the specified data by specifying the cell data correction such as the circuit, logic, and layout for the required cell, and then accepts the edit. At this time, in order to make it easy to understand the periphery of the cell to be edited, in the case of logic or circuit data, the data of all the adjacent cells is displayed. 3. If not repeated, a single arrangement is made, and an edit pattern is created including adjacent cells. The edit pattern formed in this way is converted into work data for an editor (data conversion 62) and passed to the layout editor 61 for editing by a function such as edit-in-place. Therefore, the layout element cell can be edited while looking around the edit target. All cells other than the edit target cell are made uneditable. The edited contents are inversely converted (data conversion 63) and returned again as layout data. In the figure, the creation of the highest working cell is an instruction to create a working cell in which cells to be edited and cells around the cell to be edited are created, and the corresponding data is converted into data.
Is subject to. After conversion, deletion of the top working cell is instructed.

<< Data Generation >> Next, a process of generating in-mat data and the like based on the structure definition information and cell data will be described. This data generation is performed separately for each of layout data, circuit data, logic data, and the like.

First, generation of layout data will be described. First, the CPU 13 reads the structure definition information and the cell information used in the structure definition into the memory 14, and creates the structure definition table 19 shown in FIG. The structure definition table 19 is a table based on the structure definition information of FIGS. 11 to 13, and is not particularly limited, but the cell name, the arrangement rotation angle, the mirror arrangement, and the cell frame coordinates (Xmi).
(n, Ymin, Xmax, Ymax) is set as one unit data, and these are arranged in a matrix, and the information of the number and width (arrangement pitch) of the unit data arranged in the horizontal direction is associated with each horizontal direction of the unit data. Similarly, information on the number and width of unit data arranged in the vertical direction is associated with each vertical direction of the unit data. The unit data arranged in a matrix conforms to the element position sequence numbers described in FIGS. 12 and 13. The element position sequence number is (X = 0, Y = 0) at the lower left, and X increases toward the right,
The order number is such that Y increases in the upward direction.

According to the above structure definition table, the whole mat data or mat data obtained by reducing the data by the specified number of repetitions is generated in the following procedure. When generating a mat with the number of repetitions of the two-dimensional array being 2, for example,
(1) First, the lower left cell having the element position sequence number (0, 0) is arranged. (2) The cell frame coordinates of the cell are checked from the structure definition table 19, the relative arrangement coordinates are obtained so that the cell frames of the adjacent cells come into contact with each other, and the arrangement number is set to 2. (3) The relative placement coordinates of the cells (cells whose element order numbers have been increased by 1) adjacent to the cells placed in (2) above are determined, and if they are single cells, one is placed, and if they are arrays, The number of repetitions is set as 2.
By sequentially arranging up to the data on the upper right of the structure definition table 19 (data of the cell having the last element sequence number),
It is possible to create a mat layout arrangement in the case where the number of regular repeating portions is two.

Next, the terminals are generated by the following procedure.
(1) The cell name and the terminal name are read from the terminal definition information of the structure definition information. (2) All terminal positions are calculated from the layout coordinates of the designated cell and the layout data of the cell. (3) If there is no naming rule, this is output. (4) If there is a naming rule, the terminal positions are sorted by coordinates, and the terminal name is assigned and output according to the naming rule.

Address assignment of the decoder is similarly performed in the following procedure. (1) Read the decoder definition of the structure definition information. (2) Find all the placement coordinates of the designated cell and sort by the placement coordinates. (3) Place perforated cells according to the decoder definition.

This completes the generation of layout data. Next, a procedure for generating each of the circuit data, the logic data, and the pattern data will be shown.

FIG. 19 shows an example of a mat circuit. It is meaningless to reduce the number of iterations and verify the circuit for the circuit data to be subjected to the circuit simulation, and the most important issue is to extract a portion having no connection relation from the regular structure. FIG. 20 shows a circuit example of a dynamic memory cell. In generating the circuit data, for example, taking a memory cell as an example, as shown in FIG. 20, the circuit data of the designated memory cell (all circuits), the circuit data connected to this (the omitted circuit 1), and The circuit data of each cell is prepared in advance by dividing it into three stages of the other circuit data (the omitted circuit 2). All the circuits are data representing the circuit configuration of the memory cell itself. The abbreviated circuit 1 is an equivalent representation of the gate capacitance and storage capacitance of the memory cell as the parasitic capacitance of the word line and the bit line. The omitted circuit 2 means a memory cell that is not connected to the target portion. After preparing the circuit data of these circuit cells, based on the specification of the cell at the required position,
As shown in FIG. 21, circuit data of a necessary part is generated. For example, in an actual circuit simulation for a memory mat, for example, all circuits are adopted for both ends and a central portion on a diagonal line of the memory mat, and for all memory cells that share a word line and a bit line with all circuits. The omitting circuit 1 can be used, and the omitting circuit 2 can be used for the other memory cell portions. This makes it possible to obtain a circuit model in which portions having no connection relation are substantially omitted from the regular structure of the circuit. When the circuit data of the memory cell required for the circuit simulation is prepared, first, the target circuit data (all circuits) of the designated cell is read out on the table. Next, the omitting circuit 1 of the cells which are adjacent to this is output, and the connecting circuits in the mat are output sequentially following the connecting relationship. Finally, the omission circuit 2 is output for the ones having no connection relation. After that, the generation of mat circuit data is completed by performing contraction on the output data.
There are the following methods for extracting the circuit connection information, and one of them is used. (1) A method of extracting connection information between adjacent cells using terminal information of layout data.
(2) Between adjacent cell symbols in circuit data,
A method that regards terminals that have the same relative order of terminals on each side as being connected. The circuit data of the memory cell portion generated as described above is a circuit equivalent to the circuit shown in FIG.

Next, generation of logical data will be described.
FIG. 22 shows a circuit example of a one-transistor type dynamic memory cell, FIG. 23 shows a truth table of the memory cell of FIG.
FIG. 24 shows a functional expression of the memory cell of FIG. 22, and FIG. 25 shows a functional model of a memory cell array using the memory cell of FIG. Either the truth table or the functional expression may be used, and the other can be generated from one.
The functional expression of FIG. 24 shows the contents of the truth table of FIG. In FIG. 23, "0" is a low level for writing,
"1" is a high level for writing, "L" is a low level for reading, "H" is a high level for reading, and M is a precharge level of the bit line (a level between "0" and "1"). , And the respective levels have a relationship of 0 <L <M <H <1. * Means indefinite, A means don't care with an arbitrary value. W [i] is the word line of row number i, D [j] is the bit line of column number j, and X [i, j] is the storage node of the memory cell whose matrix position is {i, j} (on the selected MOS transistor side). ) Is meant.

Based on the function definition of each cell, a function definition when the cell is made into an array is generated. At this time, by designating the number of cell repetitions, it becomes possible to create the logic data of the memory cell array of any size for the logic simulation. The functional model of the entire mat can be completed by synthesizing the functional models of each array unit.

<< Circuit Verification >> A circuit simulation can be performed using the circuit data of only the necessary portions created by the data generation. A huge amount of time is required to manually create all the circuits, but the present invention makes it possible to instantaneously obtain a desired circuit. Therefore, by repeating verification for each part, the memory mat and the intermediate A simulation equivalent to that for all surroundings is possible.

<< Logic Verification >> First, a functional model of the memory mat and the intermediate periphery having a number of repetitions is generated, and the logical verification in the memory mat and the intermediate periphery is performed. The entire design data of one memory mat and the middle periphery and the data 5 in the mat (memory mat and the middle periphery) in which the regular repeated parts are omitted are both the same structure definition (structure rule).
Therefore, the logic verification based on the in-mat data 5 in which the regular repeated portion is omitted is performed only in the point that the repeated portion is omitted. It is equivalent to the verification for the surroundings. After that, a functional model relating to external input / output in the memory mat and the intermediate peripheral (interface between the memory mat and the intermediate peripheral and their outsides) is generated, and combined with the indirect peripheral circuit, the entire logical simulation is performed.

<< DRC (Design Rule Check) >> As shown in FIG. 26, the DRC is a portion around the indirect portion, a portion around the memory mat and the middle portion, and a mat boundary portion (indirect portion between the memory mat and the portion around the middle portion). It is implemented in three parts: the boundary part with the peripheral part).
(1) The indirect peripheral portion 31 checks the non-matte data according to the indirect peripheral rule. If the DRC has a function of excluding the designated block, the block name of the mat is designated and excluded from the target. If this function is not provided, data excluding matte is generated, and DRC is performed on this data (including a check for peripheral data jumping into the matte area). (2) In the mat, a mat in which the number of cell repetitions is about 3 is generated, and the mat internal rule is checked. The decoder part checks all combinations by perforating them (including checking that there is no protrusion in the area outside the mat). (3) For the mat boundary part, the data having both the indirect periphery and the entire mat is windowed only for those boundary parts (about several tens of μm), and the mat inner rule is checked. If the DRC has a window function, it is used. If there is no window function, only boundary data is generated and DRC is performed on it.

<< Connection Check >> The connection check is shown in FIG.
As shown in FIG. 7, the procedure is as follows. (1) The mat terminal is automatically generated according to the structure definition based on the terminal of the mat element cell (the terminal naming rule is specified). (2) At the chip level, check the connection between the wiring and the mat terminal. Therefore, it is not necessary to use the mat pattern, the data amount is only the peripheral data, and the connection check equivalent to the chip batch can be performed. (3) Since the inside of the mat is equivalent to the entire mat and can be checked at high speed, circuit / layout data with the number of cell repetitions in the mat set to 2 and 3 is generated and the wiring is checked using this (mathematical induction method). Therefore, even if the number of repetitions is> 3, the wiring relationship is the same. The decoder generates and checks data including perforations / connections for all circuits.

<< Auxiliary Data Generation >> The CPU 13 uses the structure definition information to specify a two-dimensional array area, a unit area, a mat area, etc., and generates auxiliary data such as coordinate information necessary for optical comparison inspection and the like.

According to the above embodiment, the following operational effects can be obtained.

The entire design data of one mat and the in-mat data 5 in which the regular repeating portion is omitted follow the same structure definition (structure rule), and whether the repeating portion is simply omitted or not is determined. The data in the mat 5 that omits the regular repeated part, because it only differs in points
Various kinds of verification such as logic verification and design rule check based on the above are equivalent to verification based on the corresponding whole data. That is, the basic rule of the regular repeated part is the same whether the repeated part is the whole data as it is or the verification data in which the repeated part is omitted as desired. The logic verification and the design rule check can obtain a result substantially equivalent to the case where the whole is collectively checked.

Therefore, regarding the circuit simulation, the circuit simulation can be performed by using the circuit data of only the necessary portion. It takes a huge amount of time to manually create all the circuits, but according to the present embodiment, a desired circuit can be instantly obtained. Therefore, by repeating verification for each part, the mat ( A circuit simulation equivalent to that of all of the memory mat 32 and the intermediate periphery 35) can be performed.

With respect to the logic simulation, a functional model of the mat having a number of iterations of several is generated, and the logic verification in the mat is performed. Design data for the entire mat and data within the mat without regular repeating parts 5
Both have the same structural definition, and differ only in whether or not the repeated portion is omitted. Therefore, the logic verification based on the in-mat data 5 in which the regular repeated portion is omitted corresponds to that. It is equivalent to the verification for the entire memory mat and the intermediate periphery. Further, it is possible to generate a functional model regarding external input / output (an interface between the memory mat and the intermediate peripheral and their outsides) in the mat, and combine the functional model with the indirect peripheral to perform the entire logical simulation.

Regarding the design rule check,
It can be divided into three parts: an indirect peripheral part, a mat part, and a mat boundary part. The indirect peripheral portion 31 verifies the non-matte data according to the indirect peripheral rule. Regarding the inside of the mat, a mat having the number of cell repetitions of about 3 is generated, and verification is performed by the inside-mat rule. Regarding the mat boundary part, a window is applied only to those boundary parts for the data having both the indirect periphery and the entire mat, and the verification is performed by the in-mat rule.

Regarding the connection check, mat terminals are automatically generated according to the structure definition based on the terminals of mat element cells, and the connection between the wiring and the mat terminals is checked at the chip level. Therefore, it is not necessary to use the mat pattern, and the data amount is only the peripheral data, and the connection check equivalent to the chip batch can be performed. Regarding the inside of the mat, it is equivalent to the entire mat and is checked at high speed.
It is possible to generate circuit / layout data in which the number of repetitions of cells in the mat is 2 and 3, and use this to check the connection.

The data of the entire mat can be automatically generated based on the structure definition information while eliminating a long manual processing time and mistakes. Automatically generate matte data that omits regular parts and only needs parts,
It is possible to reduce the amount of target data, and it is possible to realize a verification process that is equivalent to the case where the entire target is targeted and is fast.
Not only can the data be generated, but it is possible to automatically generate the information of the regular structure, for example, the area coordinates and the like from the structure definition.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto and needless to say, various modifications can be made without departing from the scope of the invention. Yes. For example,
The block structure definition is not limited to the above-described embodiment, and can be performed in another format depending on the identification information (element name) of each individual element cell, the arrangement coordinates or arrangement pitch of the element cells, the presence or absence of mirror inversion for the pattern, and the like. Although the memory design has been described as an example in the above embodiments, the present invention is not limited to this, and can be applied to a semiconductor integrated circuit for data processing including a large number of regular repetitions. .

[0085]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, for a regular repeating structure portion (mat) in an electronic circuit such as a semiconductor memory, the system defines a minimum constraint that can determine general regularity as a model. Items that can be changed in individual data are defined as individual pieces of structure definition information. Thereby, it is possible to define the regularity while giving each individual data a degree of freedom. The electronic circuit is designed so as to satisfy this regularity. Therefore, the regularity can be uniquely extracted with respect to the regular repeating portion in the electronic circuit having the repeating structure portion. Therefore, according to the regularity defined by the model, it is possible to obtain verification data in which the data amount is reduced by setting the number of repetitions of the regular repeating portion as desired.

The basic rule of the regular repeated part is the same whether the repeated part is the whole data as it is or the verification data in which the repeated part is omitted as desired. The logic verification and the design rule check of can obtain the result substantially equivalent to the case where the whole is collectively checked.

Further, since the verification data is generated based on the same cell definition and the same cell data as the generation of the whole data, a correction error or the like of the data can be eliminated.

Also, the two-dimensional array coordinates and the area coordinates of the mat of any size can be determined in the same manner, and in order to check the mat and other boundaries, the specification of only the boundary area can be automated.

By changing the structure definition information, it is possible to similarly create mats having different two-dimensional array numbers, used cells, repetition numbers, etc. from the same constitutive model of the mat.

As a result, it is possible to automatically generate the data of the entire mat based on the structure definition information while eliminating a long manual processing time and mistakes. It is possible to reduce the amount of target data by automatically generating matte data that omits the regular part and only includes the necessary part, and realizes a verification process that is equivalent to the case of the whole target and high-speed. it can. Not only can the data be generated, but it is possible to automatically generate the information of the regular structure, for example, the area coordinates and the like from the structure definition.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a system configuration for implementing a method for designing a semiconductor integrated circuit according to the present invention.

FIG. 2 is a comparative explanatory diagram showing (A) the entire design data for one mat and (B) the in-mat data with the repeated portion omitted.

FIG. 3 is a block diagram of an example of a structure definition editing unit and a data generating unit.

FIG. 4 is an explanatory diagram illustrating an example of a hierarchical structure of a structure definition model applied to a semiconductor memory.

FIG. 5 is an explanatory diagram schematically showing a chip image of a hierarchical structure of a semiconductor memory.

FIG. 6 is an explanatory diagram showing an example of definition of a memory array in a hierarchical structure.

FIG. 7 is an explanatory diagram showing an example of definition of a memory mat in a hierarchical structure.

FIG. 8 is an explanatory diagram illustrating an example of definition of an intermediate periphery in a hierarchical structure.

FIG. 9 is a diagram illustrating an example of terminal definition.

FIG. 10 is an explanatory diagram illustrating an example of address allocation definition of a decoder.

FIG. 11 is an explanatory diagram showing a terminal definition and a decode definition in the structure definition information in the case of following the rule structure model.

FIG. 12 is an explanatory diagram showing a part of a memory array, a type, and a direct peripheral of a memory mat among the block structure definitions according to the rule structure model.

FIG. 13 is an explanatory diagram showing the rest of the immediate periphery and the intermediate periphery of the block structure definition in the case of following the rule structure model.

FIG. 14 is an explanatory diagram showing an example display mode of a block structure definition setting screen.

FIG. 15 is a diagram illustrating an example display mode of a decoder definition setting screen.

FIG. 16 is a diagram illustrating an example display manner of a terminal definition setting screen.

FIG. 17 is a system configuration block diagram focusing on structure definition editing in consideration of enabling modification of element cells.

FIG. 18 is an explanatory diagram of an example of a structure definition table.

FIG. 19 is an explanatory diagram showing a circuit example of a mat.

FIG. 20 is an explanatory diagram showing an example of circuit data of cells generated by dividing one circuit cell into three types.

FIG. 21 is an explanatory diagram showing a part of circuit data for circuit verification, which is generated by using circuit data of a cell.

FIG. 22 is a circuit diagram of a one-transistor type dynamic memory cell.

23 is an explanatory diagram of an example of data expressing the memory cell of FIG. 22 in a truth table format.

24 is an explanatory diagram of an example of data in a functional expression format of a memory cell, which is equivalent to the data in FIG.

25 is an explanatory diagram showing a functional model of a memory cell array using the memory cell of FIG. 22. FIG.

FIG. 26 is an explanatory diagram of a case where DRC is divided into three parts of an indirect peripheral part, a mat part, and a mat boundary part.

FIG. 27 is an explanatory diagram of an example of a connection check.

[Explanation of symbols]

 1 structure definition editing means 2 structure definition data 3 cell data 4 data generation means 5 mat inside data 6 mat boundary data 7 mat outside data 13 CPU 14 memory 18 structure definition model 19 structure definition table 20 cell data table 30 chip 31 indirect peripheral 32 Memory mat 33 Memory array 34 Direct peripheral 35 Intermediate peripheral

Claims (9)

[Claims] 1. A method of designing an electronic circuit having a physical and logical regular structure through data processing by a computer, wherein a regular structure model for predefining a certain regularity for a regular structure portion is provided. Define and generate structure definition information for designating a required rule structure according to this rule structure model, and correspond to the structure definition from design data of the elements used in the structure definition and the structure definition information. A method for designing an electronic circuit, characterized in that design data of the entire ruled structure part is generated. 2. When generating the entire design data, the required repeating structure scale is specified for a regular repeating part included in the regular structure part for the purpose of checking the inside of the regular structure part, 2. Based on the designated repeating structure scale, omissible data is automatically determined from the structure definition information for the rule structure portion, and verification data of only the necessary portion is created. A method for designing the described electronic circuit. 3. When generating the entire design data, optional data is automatically determined from the structure definition information for the purpose of checking the boundary portion between the rule structure portion and the outside of the rule structure portion. 2. The method for designing an electronic circuit according to claim 1, wherein verification data of only a necessary portion is created as data of the boundary portion. 4. The structure definition information includes identification information of each element used in the structure definition, arrangement position information of the element, and the number of repeated arrangements of the element. Method of designing electronic circuits. 5. A method of designing a semiconductor memory through data processing by a computer, wherein a certain regularity is defined in advance for a regular structure portion having a physically and circuitally regular repeating portion of the semiconductor memory. For defining a regular structure model for a chip, a memory mat included in the chip, a first peripheral shared by a plurality of memory mats, and a memory included in the memory mat. An array and a second perimeter unique to the memory array, a first element cell as the memory array includes, the first
Has a hierarchical structure consisting of a second element cell included in the periphery of and a third element cell included in the second periphery, for designating a required rule structure in accordance with this rule structure model. Of each of the first to third element cells of
A process for generating structure definition information including identification information, arrangement position information, and the number of repeated arrangements, and a rule structure corresponding to the structure definition from the design data of the element cell used in the structure definition and the structure definition information. Repetition structure scale required for the element cells included in the rule structure part for the purpose of checking the inside of the rule structure part when generating the design data of the whole part and the whole design data And a process of automatically determining optional data from the structure definition information for the rule structure part based on the specified repeating structure scale and creating verification data of only the necessary part. A method for designing a semiconductor memory, comprising: 6. When generating the entire design data, optional data is automatically determined from the structure definition information for the purpose of checking the boundary portion between the rule structure portion and the outside of the rule structure portion. 6. The method for designing a semiconductor memory according to claim 5, wherein verification data of only a necessary portion is created as data of the boundary portion. 7. A data processing system for designing an electronic circuit having a physical and logical regular structure, wherein a regular structure model for predefining a certain regularity for a regular structure portion is defined. First storage means, structure definition editing means for generating structure definition information for designating a required rule structure in accordance with the rule structure model defined in the first storage means, and used in the structure definition A data processing system, comprising: data generation means for generating design data of the entire rule structure portion corresponding to the structure definition from element design data and the structure definition information. 8. The data generating means, for the purpose of checking the inside of the rule structure part when generating the entire design data, the necessary repetition for the regular repetition part included in the rule structure part. It is possible to specify the structure scale and automatically determine the optional data from the structure definition information for the rule structure part based on the specified repetitive structure size, and create verification data for only the necessary part. The data processing system according to claim 7, characterized in that. 9. The data generating means, when generating the entire design data, extracts data that can be omitted from the structure definition information for the purpose of checking the boundary portion between the rule structure portion and the outside of the rule structure portion. 9. The data processing system according to claim 7, wherein it is possible to automatically determine and create verification data only for a necessary portion as boundary data.