JP2000215220A - Logical cell characterizing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logical cell characterizing device requiring enormous calculation and to requiring the time for circuit simulation. SOLUTION: The logical cell characterizing device is constituted of a circuit dividing means for dividing a logical cell to be processed into plural function parts based on an inputted network list, an individual characterizing means corresponding to respective divided function parts and capable of independently executing characterizing processing in each circuit constituting each function part and a post characterizing means 3 for generating characterized data for the whole logical cell based on the characterized data individually obtained by the individual characterizing means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a logic cell characterization device, and more particularly to a function of generating delay data for circuit simulation.

[0002]

2. Description of the Related Art A delay simulation of a logic circuit is executed before and after a layout design, and a simulation that faithfully reflects a layout situation is performed to determine whether or not the designed logic circuit operates normally. This is what is done for you. In order to execute a delay simulation, a delay model of the entire logic circuit must be generated from delay data of all logic cells constituting the logic circuit. In this case, it is necessary to perform a delay calculation that faithfully reflects the layout situation for the logic cells that drive all the logic nets. In this case, the delay data of the logic cell, which is the minimum unit of the logic circuit, is required. Becomes

For example, the delay data of a logic cell includes the signal delay time from the input terminal to the output terminal when the slope time of the input signal (the time required for the input signal to make a full swing) and the load capacitance are changed. It is given as a signal gradient time data group of the output terminal. These are generally represented by data tables.

Conventionally, such delay data has been obtained by characterizing a transistor netlist of a logic cell, transistor parameters, and characterization conditions using a circuit simulator.

[0005]

The conditions for characterizing a logic cell are variations of the slope of the input signal and the load capacitance, and there are as many as the number obtained by multiplying the number of variations. For example, if there are five variations, there are 5 × 5, that is, 25 variations. In the conventional apparatus, by performing the circuit simulations by this number, the characterizing data that is the source of the delay data is obtained.

However, the required number of circuit simulations is not determined by this alone. For example, there are a large number of logic cells constituting a logic circuit, and the number is as large as several hundreds. Assuming that the number is 300, if there are 25 types of characterization conditions, it is necessary to execute an enormous number of circuit simulations of the number obtained by multiplying them, that is, 300 × 25 types = 7500 times. is there.

On the other hand, a circuit simulation is performed by a numerical calculation process using a computer from a transistor netlist of a logic cell, a transistor parameter, and a characterization condition, so that a large amount of computer time is required.

For this reason, ICs for specific applications (ASIC: Ap)
In the case of designing a replication specific IC, it takes about one month to perform a circuit simulation of all the characterization conditions for all the logic cells constituting the IC.

As described above, in the case of the conventional method (apparatus), a lot of computer resources and processing time are required to generate the delay data of the logic cell.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has been made to reduce the computer resources and processing time required for creating logic cell delay data without deteriorating the accuracy of logic cell delay data. The purpose is to realize a method (apparatus) that enables it.

[0011]

Means for Solving the Problems (A) In order to solve the above-mentioned problems, in the logic cell characterization device according to the first invention (Claim 1), (1) based on the read netlist, A circuit dividing means for dividing a logic cell to be processed into a plurality of functional units, and (2) independently executing a characterization process for a circuit constituting each functional unit corresponding to each of the divided functional units. And (3) post-characterizing means for generating characterization data for the entire logic cell based on the characterization data individually obtained by the characterization means for each functional section. To (B) In order to solve such a problem, in the logic cell characterization device according to the second invention (claim 2), in which a plurality of logic cells are processed, and the characterization process is sequentially performed on each logic cell, 1) a circuit dividing means for dividing one logical cell selected as a processing target into a plurality of functional units based on the read netlist; and (2) a character of the functional unit for each of the divided functional units. In the rise processing, a processed determination means for determining whether a processing result for each function obtained for a logic cell for which the characterization processing has already been completed cannot be used, and (3) processing corresponding to each of the divided functional units. Function units that independently execute the characterization process for the circuits constituting each of the function units for which the existing data is determined to be unusable by the completion determination unit And characterized means (4)
For the functional unit corresponding to each of the divided functional units, and for the functional unit for which the existing data is determined to be usable by the processed determination unit, the existing data is read out and interpolated, and the character of the circuit constituting the functional unit to be currently processed Characterizing means for each functional unit with an interpolation function for executing a rise process,
(5) Characterization data storage means for storing the characterization data obtained by the functional unit-specific characterization means or the function-specific characterization means with an interpolation function; A post-characterizing means for generating characterizing data of the entire logic cell based on the characterizing data individually obtained by the characterizing means for each functional unit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (A) Basic (Concept) Configuration First, a basic (concept) configuration of a logical cell characterization device according to the present invention will be described with reference to FIG. As shown in FIG. 1, the logical cell characterization device according to the present invention includes three basic elements, a pre-characterizing unit 1, a characterization unit 2, and a post-characterizing unit 3.

The pre-characterizing means 1 includes a netlist (transistor, resistor,
An element-level netlist including capacitance and inductance) is read from storage means (whether built-in or external) not shown, and a plurality of (two or more) logic cells to be processed are read. (For example, a drive circuit section, a buffer circuit section, an output circuit section, and the like (including a plurality of circuit sections)).

The characterization means 2 is a means for individually executing characterization processing for each functional unit provided from the pre-characterizing means 1. In the characterization process, the processes for each functional unit may be executed in parallel, or may be executed sequentially in time series. In this process, the characterization conditions and the transistor parameters are read from storage in a storage unit (not shown).

The post-characterizing means 3 constitutes characterizing data (logical cell delay data) for the entire logic cell from the characterizing data for each functional unit obtained by the characterizing means 2. (B) First Embodiment FIG. 3 shows a configuration of a logic cell characterization device according to a first embodiment. Note that the present embodiment is based on the premise that a logic cell to be processed is composed of two functional units, a drive circuit unit and an output circuit unit.

The logic cell characterization device according to the present embodiment comprises a circuit dividing means 11 as pre-characterizing means 1, a driving circuit characterization means 12A and an output inverter characterization means 12B as characterization means 2, It comprises post-characterizing means 13 as characterization means 3.

The circuit dividing means 11 reads the netlist of the logic cells to be processed from the storage means (not shown) and, as shown in FIG. 4, outputs an output inverter circuit (corresponding to the output circuit section) and a driving circuit. (Corresponding to the above-described drive circuit unit). Although FIG. 4 illustrates a CMOS inverter circuit as an output inverter circuit, the invention is not limited to the CMOS inverter circuit. For example, it may be constituted by a single MOS transistor element, or may be constituted by one or a plurality of bipolar transistor elements. Needless to say, the polarity of the transistor is not limited.

The drive circuit characterization means 12A
This is a means for reading only the transistor parameters and the input waveform conditions among the characterization conditions from storage means (not shown), and executing characterization processing for the drive circuit provided from the circuit dividing means 11. In addition,
The drive circuit characterization means 12A executes a circuit simulation in a case where all the slope conditions are used as input waveform conditions and the load condition is an output inverter circuit.

Table 1 shows an example of characterizing data in the case where an output signal falls, as an example of a result of executing a circuit simulation on a drive circuit (inverter) of a buffer circuit constituting a logic cell.

[Table 1] In this example, the input waveform conditions are 200, 400, 800,
When setting the six types of input tilt times of 1000, 2000, and 5000 picoseconds, the falling signal times as the characterizing data are 236, 270, and 35, respectively.
4, 375, 447, and 500 picoseconds, and the falling signal slope times are 459, 468, 529, and 59, respectively.
8, 866, and 1410 picoseconds.

Output inverter characterization means 12
B is a means for reading only the transistor parameters and the load conditions from the characterization conditions from the storage means (not shown) and executing the characterization processing for the output inverter circuit provided from the circuit dividing means 11.

The output inverter characterization means 12B uses the output (input to the output inverter circuit) gradient time of the drive circuit obtained by the drive circuit characterization means 12A as the input waveform condition. The output inverter characterization means 12B executes a circuit simulation for all load conditions.

Table 2 shows an example of characterizing data when an output signal rises as an example of a result of executing a circuit simulation on an output inverter circuit of a buffer circuit constituting a logic cell as a processing target.

[Table 2] This table corresponds to Table 1, but of course, since the circuit to be characterized is an output inverter circuit,
The case where the output signal rises corresponds to the case where the input signal (output signal of the drive circuit) falls.

In this example, the load conditions are 200, 400,
800, 1000, 1500, and 2000 femtofarads are set, and the input waveform condition is set to the output fall time of the drive circuit, that is, 459, 468, 529, and 5
When setting to six types of 98, 866 and 1410 picoseconds, the characterization data shown in Table 2 (6 × 6 total 3
6) are obtained.

The post-characterizing means 13 includes the driving circuit characterizing data (Table 1) obtained by the driving circuit characterizing means 12A and the characterizing data (Table 2) obtained by the output inverter characterizing means 12B. Then, delay data (output signal delay time and output signal inclination time under each characterization condition) as characterization data for the entire logic cell (buffer) is created.

Table 3 shows the post-characterizing means 13
5 shows an example of the result of the creation processing. In addition,
Table 3 is created based on Tables 1 and 2.

[Table 3] Specifically, the post-characterizing means 13
The rising delay time under the input slope condition and the first load condition, the falling signal delay time of the drive circuit under the first input slope condition, and the output inverter under the first input slope condition and the first load condition. It is determined by the sum of the delay time of the rising edge of the circuit. That is, the post-characterizing means 13 determines whether the falling signal delay time of the driving circuit under the first input gradient condition is "236" picoseconds, and the output inverter circuit under the first input gradient condition and the first load condition. The value of “650” picoseconds in Table 3 is obtained by the sum of the rising output delay time “414” picoseconds.

Similarly, the post-characterizing means 13
Is the rise delay time under the first input slope condition and the second load condition, the fall signal delay time of the drive circuit under the first input slope condition, the first input slope condition, and the second load condition. It is obtained by the sum of the rising output delay time of the output inverter circuit below. That is, the post-characterizing means 13 determines whether the falling signal delay time “236” picoseconds of the drive circuit under the first input gradient condition and the output inverter circuit under the first input gradient condition and the second load condition. Rise output delay time “52
The value of "757" picosecond in Table 3 is obtained by the sum of 1 "picosecond.

When this is generalized, when N types of input inclination conditions and M types of load conditions are set as the characterization conditions of the logic cell, the post-characterizing means 13 outputs the Nth N-th output signal. Input slope condition and Mth
The rise or fall delay time of the load condition is defined as the fall or rise signal delay time of the drive circuit under the Nth input slope condition, the Nth input slope condition and the Mth load condition. At the rise or fall of the output inverter circuit.

At this time, the post-characterizing means 13 uses the characterizing data obtained by the output inverter circuit as the characterizing data of the logic cell, that is, delay data, as the output inclination time of the logic cell. The post-characterizing means 13
Uses the Nth input slope condition of the drive circuit as the Nth input slope condition of the output signal.

Thus, the operation of the first embodiment is completed. By the way, the processing time of the characterization device generally occupies most of the processing time of the circuit simulation. It is also known that the processing time spent for circuit simulation tends to increase exponentially in proportion to the number of transistors forming the circuit.

Therefore, by dividing and characterizing a logic cell into a drive circuit and an output inverter circuit,
The reduction of the number of transistors constituting the characterization target, that is, the number of transistors constituting the circuit to be simulated, has the effect of reducing the circuit simulation time.

Also, since the characterization conditions of the drive circuit need only be the input inclination conditions, the number of circuit simulations can be reduced, and as a result, the characterization time can be reduced. (C) Second Embodiment Next, a second embodiment will be described. FIG. 5 shows a configuration of a logic cell characterization device according to the second embodiment. Note that the present embodiment is also based on the premise that a logic cell to be processed is composed of two functional units, a drive circuit unit and an output circuit unit.

The present embodiment is an extension of the technique described in the first embodiment to a case where a plurality of logic cells are to be characterized, and more efficiently utilizing existing processing results. This makes it possible to perform simple processing.

For this reason, in the logic cell characterization device according to the present embodiment, in addition to the configuration of the first embodiment, the output inverter characterization data interpolation means 12C, the characterizing determination means 14, the output inverter characterization data A storage unit 15 and an unprocessed logic cell determination unit 16 are newly provided.

Among them, the characterizing completed judging means 1
Reference numeral 4 denotes a unit provided for determining whether or not the same configuration as that of the output inverter circuit divided by the circuit dividing unit 11 has appeared in the constituent elements of another characterized logic cell.

More specifically, when the characterizing completion judging means 14 receives the output inverter circuit from the circuit dividing means 11, the characterizing judging means 14 accesses the output inverter characterizing data storage means 15 and already has the same (for example, CMOS)
(In the case of a type inverter circuit, the dimensions of the P-type transistor and the N-type transistor are the same). This is because, as described above, when an existing processing result exists, the time required for the processing is reduced by using the processing result.

As for the drive circuit, which is one of the divided circuits, the information is directly supplied to the drive circuit characterization means 12A after division, as in the first embodiment, and is subjected to characterization processing.

Returning to the description of the characterizing completion determination means 14, Characterized determination means 14 determines the determination result,
If the corresponding data does not exist, the process proceeds to the process of the output inverter characterization means 12B, and the characterization process is executed in the same procedure as in the first embodiment. However, the output inverter characterization unit 12B in the present embodiment stores the obtained output inverter characterization data in the output inverter characterization data storage unit 15.

On the other hand, as a result of the determination, if the corresponding data exists,
Is the output inverter characterizing data interpolation means 1
Proceed to 2C processing. Here, the output inverter characterizing data interpolating means 12C executes the interpolation processing of the characterizing data of the output inverter circuit from the characterizing data of the characterizing output inverter circuit and the characterizing data of the driving circuit.

Hereinafter, a specific example will be described. Here,
Table 2 (an example of characterizing data of the output inverter circuit) used in the description of the first embodiment is regarded as data that has been characterized. In this case, Table 4 shows an example of characterizing data of the driving circuit (inverter). The following description will be made assuming that what is performed is obtained.

[Table 4] Table 4 shows that the input waveform conditions were 200, 400, and 80.
When setting six types of input tilt times of 0, 1000, 2000, and 5000 picoseconds, falling signal times as characterization data are 248, 284, and 3 respectively.
72, 394, 469, and 525 picoseconds, and the falling signal inclination times are 482, 491, 555, and 62, respectively.
8, 909, 1481 picoseconds.

On the other hand, the characterized data stored as Table 2 is
There are six types of input waveform conditions of 68, 529, 598, 866, and 1410 picoseconds × full load condition.

If the characterization data of the output fall time of the drive circuit matches the input waveform condition of the characterized output inverter circuit, the stored characterization data is used as is for the output inverter circuit. It may be used as characterization data, but generally does not match as shown in Tables 2 and 4.

For this reason, the output inverter characterizing data interpolation means 12C generates the characterizing data. FIG. 6 shows an example of characterizing data interpolation of the output inverter circuit. Here, an interpolation example in the case where the input waveform condition is 482 picoseconds and the load capacity is 200 femtofarads is shown.

In the figure, the rise delay time of the characterized data is plotted with a square mark, and the rise slope time is plotted with a diamond mark.

What is desired here is a rising delay time in the case of 482 picoseconds and a rising gradient time as the input gradient time, so that the 468 picosecond characterization data and the 529 picosecond characterization data are used. 493 ps and 4 respectively
14 picoseconds are obtained. If this is expressed by a general formula,
The following equation is obtained.

Yt = {Yn−Yn−1) / (Xn−Xn−1)} (Xt−Xn−1) + Yn−1 (1) where Xt is the slope of the input waveform to be obtained, and Xn− 1 <X
It is assumed that the condition of t <Xn is satisfied. Yn is the characterizing data for the input tilt condition Xn, and Yn-1 is the characterizing data for the input tilt condition Xn-1.

[Table 5] Table 5 shows an example of the characterization data of the complete output inverter circuit interpolated from the characterization data of Tables 2 and 4.

When the characterization data for the output inverter circuit is obtained as described above, the processing shifts to the processing of the host characterization means 13.

In the host characterization means 13, as in the first embodiment, the characterization data of the driving circuit (Table 4) and the characterization data of the output inverter circuit (Table 2 or Table 5, ie, the output inverter). From the characterization means 12B or the output inverter characterization data interpolation means 12C) to the delay data as characterization data as an entire logic cell (buffer) (output signal delay time and output signal slope time under each characterization condition) )).

Table 6 shows the post-characterizing means 13
Shows an example of the result of the creation processing by the above.

[Table 6] In the first embodiment, a series of processing is terminated after the processing. In the case of the present embodiment, the unprocessed logic cell determination means 16 provided after the post-characterizing means 13 is used. As a result, it is determined whether or not the characterization process has been completed for all the logic cells, and a series of processes is completed only when it is determined that the characterization process has been completed for all the logic cells.

If an unprocessed logic cell exists, one unprocessed logic cell is selected by the unprocessed logic cell determination means 16 and the characterization process for the logic cell is performed by the circuit division means. It starts from 11.

Thus, the operation of the second embodiment is completed. As described above, according to the second embodiment, when characterizing a plurality of logic cells, attention is paid to the fact that the output inverter circuit often becomes the same, and existing characterizing data is used. Since the circuit simulation time can be reduced, it is possible to further reduce the time required for performing circuit simulation on a plurality of logic cells. (D) Other Embodiments In the above embodiment, the case where the logic cell is divided into the driving circuit and the output inverter circuit in the circuit dividing means 11 has been described, but the configuration of the output circuit section is limited to the output inverter circuit. However, the present invention can be applied to various existing circuits such as a differential output circuit and a source follower (emitter follower) output circuit.

In the above embodiment, the case where the output inverter characterizing data interpolating means 12C generates characterizing data by linear interpolation has been described. However, the interpolation method is not limited to this, and various existing interpolation methods can be used. Can be appropriately selected.

In the above-described embodiment, the configuration in which the interpolation processing is executed only for the output inverter circuit in the divided circuit configuration has been described. However, the configuration may be such that the interpolation processing is also executed for the drive circuit.

In the above description, the case where the second embodiment is applied to a case where a plurality of logic cells are to be processed has been described. However, the first embodiment is characterized by the characterization of each logic cell to be processed. You may apply to processing as it is. Even in this case, the effect of reducing the processing time can be realized as compared with the conventional apparatus.

In the above-described embodiment, the functional configuration of the logic cell characterization device is represented by hardware (that is, represented by “means”). Needless to say, the present invention is not limited to software processing on a computer. It can also be realized as

[0055]

As described above, according to the logic cell characterization apparatus according to the first aspect of the invention, the logic cell to be processed is divided into a plurality of functional units, and the characterization process is executed for each functional unit. Finally, based on these individually obtained characterization data, the characterization data for the entire logic cell is generated,
The effect of shortening the processing time due to the reduction in the scale of the circuit to be characterized can be used, and the processing time of the entire logic cell can be significantly reduced as compared with the conventional device.

Further, as described above, according to the logic cell characterization device of the second invention, when a plurality of logic cells are to be processed, the previously obtained characterization data may be used. Focusing on a certain point, when existing characterizing data can be used, the processing required for calculating the characterizing data can be simplified, so that more efficient characterizing processing can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conceptual configuration of a logic cell characterization device according to the present invention.

FIG. 2 is a block diagram showing a conceptual configuration of a logical cell characterization device according to the first embodiment.

FIG. 3 is a diagram showing an example of a concept of dividing a logic cell by a circuit dividing means.

FIG. 4 is a block diagram illustrating a conceptual configuration of a logical cell characterization device according to a second embodiment.

FIG. 5 is a diagram illustrating an example of an interpolation operation performed by an output inverter characterizing data interpolation unit;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Pre-characterizing means, 2 ... Characterizing means, 3 ... Post characterizing means, 11 ... Circuit dividing means, 12A ... Drive circuit characterization means, 12
B: output inverter characterizing means, 12C: output inverter characterizing data interpolating means, 13 ...
Post-characterizing means, 14 ... Characterized determination means, 15 ... Output inverter characterization data storage means, 16 ... Unprocessed logic cell determination means.

Claims (2)

[Claims] 1. A logic cell characterization device, comprising: a circuit dividing means for dividing a logical cell to be processed into a plurality of functional units based on a read netlist; Based on the characterizing means for each functional part, which individually executes the characterization processing for the circuits constituting each functional part, and the characterization data individually obtained by the characterizing means for each functional part, And a post-characterizing means for generating the characterizing data of (1). 2. A logic cell characterization apparatus which processes a plurality of logic cells and sequentially executes a characterization process for each logic cell, wherein one logic selected as a processing target based on a read netlist is provided. A circuit dividing means for dividing the cell into a plurality of functional units; and for each of the divided functional units, a process result for each function obtained for a logic cell for which the characterization process has been completed is added to a characterization process of the functional unit. A processing determination unit for determining whether or not the data can be used; and a circuit corresponding to each of the functional units after the division and for which the processing determination unit determines that the existing data cannot be used. Function characterization means to execute the characterization process independently for each function unit In response, for the functional unit for which the existing data is determined to be usable by the processed determination unit, the existing data is read out and interpolated, and the interpolation for executing the characterization process for the circuit constituting the functional unit to be currently processed is performed Characterizing means for each functional part with function; Characterizing data storage means for storing characterizing data obtained by the characterizing means for each functional part or the characterizing means for functional part with interpolation function; And post-characterizing means for generating characterizing data of the entire logic cell based on the characterizing data individually obtained by the characterizing means and / or the characterizing means for each functional unit having the interpolation function. Logic cell characterization device.