JPH1040281A - Mask rom layout pattern verification device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mask ROM layout pattern verification device which visually recognize ROM truth value data and coordinate value data at once and which can reduce labor and time, which are required for verification by adding ROM data, address decoder information and coordinate value data to layout data. SOLUTION: A ROM truth value data generation means 7 generates ROM truth value data based on address decoder information 4 and ROM data 1. A layout data generation means 12 generates layout data from coordinate value data based on ROM truth value data and coordinate value information 9 where the rectangular arrangement position of ROM is mentioned. A layout data information addition means 13 adds ROM data 1, address decoder information 4 and coordinate value information 9 to layout data and generates and displays added information layout data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM layout pattern verification apparatus for verifying a layout pattern created for writing ROM data in an integrated circuit having a built-in mask ROM.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a configuration of a conventional mask ROM layout pattern verification device. In the figure, 1 is ROM data, 2 is ROM data reading means, 3 is ROM data storage means, 4 is address decoder information, 5 is address decoder information reading means, 6 is address decoder information storage means, and 7 is ROM truth value data. Creation means, 8 is ROM truth value storage means, 9 is coordinate value information, 10 is coordinate value information reading means, and 11 is coordinate value data storage means.

The ROM truth value storage means 8 outputs ROM truth value data as a ROM truth value list 20. 21 is a ROM data recreating means for recreating ROM data from data in the address decoder information storage means 6, and 22 is a ROM data recreating means for recreating ROM data and RO data.
ROM data comparing means for comparing the data with the data in the M data storage means 3;
The ROM data comparing means 22 is implemented manually. Reference numeral 23 denotes an outer peripheral portion of the coordinate value data stored in the coordinate value data storage means 11 (maximum X coordinate, all Y coordinates and minimum X coordinate, all Y coordinates, all X coordinates, maximum Y coordinate and all X coordinates, minimum Y coordinate). Outer peripheral portion layout data generating means for reading out the outer peripheral portion layout data.
Reference numeral 4 denotes an outer periphery layout data storage unit that stores the outer periphery layout data output by the outer periphery layout data creating unit 23, and 25 denotes an outer periphery layout data storage unit 2.
4 is a display for displaying outer peripheral portion layout data output from the display unit 4;

Next, the operation will be described. FIG. 10 is a flowchart showing the flow of the mask ROM layout pattern verification operation. First, in step ST1, ROM data 1 for verification is created, and in step ST2, address decoder information 4 is read from the ROM address information of the product (integrated circuit with a built-in mask ROM) to be developed using an editor.
Create Next, in step ST3, the address decoder information 4 is read and stored.
The OM data 1 is read and stored. Next, step ST
5 and their address decoder information 4 and R
ROM truth value data is created and stored from the OM data 1, and the ROM truth value data is stored in the RO in step ST6.
Output as M truth value list 20.

Next, in step ST7, the verifier refers to the output ROM truth value list 20 and manually rewrites the ROM data based on the address decoder information 4 stored in the address decoder information storage means 6. Create and
The ROM data recreated in step ST8 and R
The original ROM data 1 stored in the OM data storage means 3 is visually compared and checked. As a result, if there is an abnormality, the process returns to step ST2 and the address decoder information 4 is created again.

On the other hand, if there is no abnormality, the process branches to step ST9 to read the coordinate value of the position where the ROM rectangle is generated from the layout data of the integrated circuit with a built-in mask ROM, and to create the coordinate value information 9 using an editor. I do. Next, in step ST10, the coordinate value information reading means 10 reads the coordinate value information 9 to create coordinate value data, and stores it in the coordinate value data storage means 11. Next, in step ST11, the outer peripheral portion layout data creating means 23 uses the coordinate value data stored in the coordinate value data storage means 11 to read the outer peripheral portion of the ROM portion (maximum X coordinate, all Y coordinates, minimum X coordinate, Y coordinate, all X
Coordinates, maximum Y coordinates, all X coordinates, minimum Y coordinates) are created, and the outer peripheral layout data is stored in the outer peripheral layout data storage means 24.

The outer periphery layout data created in this way and stored in the outer periphery layout data storage means 24 is displayed on the display 25 in step ST12. In step ST13, the verifier visually checks the outer peripheral portion layout data displayed on the display 25. If there is an abnormality, the process proceeds to step S13.
Returning to T9, the coordinate value information 9 is created again. On the other hand, if there is no abnormality, the series of layout pattern verification operations ends.

[0008]

Since the conventional mask ROM layout pattern verifying apparatus is constructed as described above, it is necessary to confirm the ROM truth value data as to whether the ROM code is correctly arranged in the layout, and to check the layout data. The verifier must visually check the coordinate value data to determine whether it is located at the correct position in the integrated circuit with the built-in mask ROM, and check the ROM truth value data and the coordinate value data at once. Not only cannot do it, but also create validation data manually,
That is, since the ROM data is re-created, there has been a problem that much labor and time are required for the confirmation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. By adding ROM data, address decoder information, and coordinate value data to layout data, it is possible to confirm ROM truth value data and to read coordinate value data. It is an object of the present invention to obtain a mask ROM layout pattern verifying apparatus that can perform the verification at once and visually, and can reduce the labor and time required for verification.

[0010]

According to the first aspect of the present invention, there is provided a mask ROM layout pattern verifying apparatus, comprising: a ROM truth value data created by a ROM truth value creating means based on address decoder information and ROM data;
Layout data creating means for creating layout data from coordinate value data based on coordinate value information describing a rectangular arrangement position, and additional information layout by adding ROM data, address decoder information, and coordinate value data to the layout data. It is provided with layout data information adding means for creating data.

According to a second aspect of the present invention, there is provided a mask ROM layout pattern verification apparatus, further comprising: ROM data;
There is provided additional information layout data display means for changing the display form of the additional information layout data created by adding address decoder information and coordinate value data in accordance with the display information.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of a mask ROM layout pattern verification apparatus according to Embodiment 1 of the present invention. In the figure, 1 is R for verification.
ROM data describing an OM code.
ROM data reading means for reading the OM data 1; 3 a ROM for storing the read ROM data 1
Data storage means. Reference numeral 4 denotes address decoder information describing ROM address information corresponding to an integrated circuit with a built-in mask ROM, which is a product to be developed. Reference numeral 5 denotes address decoder information reading means for reading the address decoder information 4; Address decoder information storage means for storing the address decoder information 4. Reference numeral 7 denotes a ROM truth value creating means for creating ROM truth value data based on the ROM data stored in the ROM data storage means 3 and the address decoder information 4 stored in the address decoder information storage means 6. .., 8 are ROM truth data storage means for storing the ROM truth data output by the ROM truth data creation means 7. Reference numeral 9 denotes coordinate value information describing the position in the layout pattern in which the ROM rectangle corresponding to the integrated circuit with a built-in mask ROM is to be developed. Coordinate value information reading means 11 is a coordinate value data storage means for storing the coordinate value data created by the coordinate value information reading means 10. These parts correspond to those of the related art shown with the same reference numerals in FIG.

Reference numeral 12 denotes layout data creation for creating layout data based on the ROM truth value data stored in the ROM truth value storage means 8 and the coordinate value data stored in the coordinate value data storage means 11. Means. Reference numeral 13 denotes ROM data storage means 3 for storing the layout data created by the layout data creation means 12.
, The additional information layout data by adding the ROM data 1 stored in the address data, the address decoder information 4 stored in the address decoder information storage means 6, and the coordinate value data stored in the coordinate value data storage means 11. This is layout data information adding means to be created. Reference numeral 14 denotes additional information layout data storage means for storing the additional information layout data output from the layout data information adding means 13, and reference numeral 15 denotes a display for displaying the additional information layout data output from the additional information layout data storage means 14. It is.

Next, the operation will be described. FIG. 2 is a flowchart showing the flow of the mask ROM layout pattern verification operation. First, in step ST21, ROM data 1 for verification is created, and in step ST22, address decoder information 4 is created using an editor from ROM address information of the integrated circuit with a built-in mask ROM to be developed. Next, step ST2
In step 3, the coordinate value of the position where the ROM rectangle is generated is read from the layout data of the integrated circuit with a built-in mask ROM, and the coordinate value information 9 is created using an editor.

Thereafter, the process proceeds to step ST24, in which the address decoder information reading means 5 of the integrated circuit with the built-in mask ROM to be developed is read by the address decoder information reading means 5, and is stored in the address decoder information storage means 6. Next, in step ST25, the ROM data 1 to be verified by the ROM data reading means 2 is read.
Is read and stored in the ROM data storage means 3. Next, the process proceeds to step ST26, where the ROM truth value generating means 7 reads the ROM data 1 stored in the ROM data storage means 3 based on the address decoder information 4 stored in the address decoder information storage means 6. ROM
The truth data is created and stored in the ROM truth data storage means 8. The operation so far is the same as that of the conventional mask ROM layout pattern verification device except for the creation of the coordinate value information 9.

Next, in step ST27, the coordinate value information reading means 10 reads the coordinate value information 9 to create coordinate value data and stores it in the coordinate value data storage means 11. As the coordinate value data, the value read from the coordinate value information 9 may be used as it is. Next, in step ST28, the layout data creating means 12 calculates the layout data from the ROM truth value data stored in the ROM truth value storage means 8 based on the coordinate value data stored in the coordinate value data storage means 11. Create FIG. 3 shows an image diagram of the layout data. As shown in the drawing, the layout data is obtained by arranging the ROM rectangles at positions corresponding to the respective coordinate value information in the ROM memory.

Next, in step ST29, the layout data information adding means 13 stores the layout data created by the layout data creating means 12 in the ROM.
ROM data 1 stored in data storage means 3, address decoder information 4 stored in address decoder information storage means 6, and coordinate value data stored in coordinate value data storage means 11 are added. Information layout data is created and stored in the additional information layout data storage unit 14. FIG. 4 shows an image diagram of the additional information layout data. ROM as shown
Address decoder information 4, ROM data 1, and coordinate value data are added to each ROM rectangle arranged in the memory.

The additional information layout data created in this way and stored in the additional information layout data storage means 14 is stored in the display 1 in step ST30.
5 is displayed. In step ST31, the verifier visually checks whether or not the additional information layout data displayed on the display 15 is abnormal. As a result, if there is an abnormality, the process returns to step ST22 to create the address decoder information 4 again. on the other hand,
If there is no abnormality, the series of layout pattern verification operations ends.

As described above, according to the first embodiment,
R as additional information for each ROM rectangle in the layout data
Since the OM data 1, the address decoder information 4, and the coordinate value data are displayed, the ROM truth value data and the coordinate value data can be verified at once in a short time.
Further, since the ROM data 1 and the address decoder information 4 can be checked at once, the R
There is an effect that it is not necessary to re-create the OM data.

Embodiment 2 In the first embodiment, the case where the additional information layout data is displayed on the screen as it is has been described. However, when the additional information layout data is displayed on the screen, the ROM rectangle is displayed with its display brightness set to be visually easy to understand. The display may be changed or the display color may be changed.

FIG. 5 is a block diagram showing a configuration of a mask ROM layout pattern verification device according to a second embodiment of the present invention. In the figure, reference numeral 16 denotes display information for changing the display mode such as display brightness and display color of a ROM rectangle when displaying additional information layout data, and 17 denotes display information reading means for reading the display information 16. Based on the display information 16 read by the display information reading means 17, additional information layout data stored in the additional information layout data storage means 14 is displayed on the display 15 by changing its display form. Display means. The other portions are denoted by the same reference numerals as those of the corresponding portions of the first embodiment shown in FIG. 1, and description thereof will be omitted.

FIG. 6 is an explanatory diagram showing a display example in which the display form of the ROM rectangle is changed according to the contents of the ROM data 1, and the RO data in which the ROM data 1 is "1" is displayed.
The M rectangle is highlighted or displayed in a predetermined color.
FIG. 7 is an explanatory diagram showing a display example when the display form of the ROM rectangle is changed for each ROM data bit.
The ROM rectangle of the ROM data bits “0” and “2” is highlighted or displayed in a predetermined color. In FIGS. 6 and 7, the highlight or the display in a predetermined color is indicated by hatching.

Next, the operation will be described. FIG. 8 is a flowchart showing the flow of the mask ROM layout pattern verification operation. Note that first, at step ST41, R
After creating the OM data 1, in step ST49, the layout data information adding unit 13 creates the additional information layout data by adding the ROM data 1, the address decoder information 4, the coordinate value data, and the like to the layout data.
The operation up to the storage of this in the additional information layout data storage means 14 is the same as the operation of the first embodiment shown in steps ST21 to ST29 in FIG. 2, and therefore the description thereof is omitted here.

When the additional information layout data created by the layout data information adding means 13 is stored in the additional information layout data storage means 14, the process proceeds to step ST50, where the display information reading means 17 sets
The display information 16 for changing the display mode such as the display brightness and the display color of the OM rectangle is read. Next, step ST
At 51, the additional information layout data display means 18
According to the display information 16 read by the display information reading means 17, the display form of the additional information layout data stored in the additional information layout data storage means 14 is changed as shown in FIG. To be displayed. In step ST52, the verifier changes this display mode and visually checks whether or not the additional information layout data displayed on the display 15 is abnormal. As a result, if there is an abnormality, the processing is performed to create the address decoder information 4 again in step ST42.
And if there is no abnormality, the series of layout pattern verification operations ends.

As described above, according to the second embodiment,
In addition to the effects of the first embodiment, since the additional information layout data is displayed in a different display form, it is possible to visually check the additional information layout data visually, and find an abnormal part. Has the effect of becoming easier.

[0026]

As described above, according to the first aspect of the invention, the layout data adding means adds ROM data, address decoder information and coordinate value data to the layout data created by the layout data creating means. Since the additional information layout data is configured to be displayed, the ROM truth value data and the coordinate value data can be checked at once, and the manual re-creation of the ROM data is not required. Therefore, the mask RO
The M layout pattern verification can be simplified, the labor required for the verification can be reduced, and the verification time can be shortened.

According to the second aspect of the present invention, since the display form of the additional information layout data is changed according to the display information, the mask ROM layout pattern verification can be visualized, and the abnormal portion can be more easily identified. There is an effect that can be found.

[Brief description of the drawings]

FIG. 1 is a mask ROM according to a first embodiment of the present invention;
FIG. 2 is a block diagram illustrating a configuration of a layout pattern verification device.

FIG. 2 is a flowchart showing a flow of a layout pattern verification operation according to the first embodiment of the present invention;

FIG. 3 is an image diagram showing layout data according to the first embodiment of the present invention.

FIG. 4 is an image diagram showing additional information layout data according to the first embodiment of the present invention.

FIG. 5 is a mask ROM according to a second embodiment of the present invention;
FIG. 2 is a block diagram illustrating a configuration of a layout pattern verification device.

FIG. 6 is an explanatory diagram showing a display example of additional information layout data according to the second embodiment of the present invention.

FIG. 7 is an explanatory diagram showing another display example of the additional information layout data according to the second embodiment of the present invention.

FIG. 8 is a flowchart showing a flow of a layout pattern verification operation according to the second embodiment of the present invention;

FIG. 9 is a block diagram showing a configuration of a conventional mask ROM layout pattern verification device.

FIG. 10 is a flowchart showing a flow of a conventional layout pattern verification operation.

[Explanation of symbols]

1 ROM data, 4 address decoder information, 7 R
OM truth value data creating means, 9 coordinate value information, 12 layout data creating means, 13 layout data information adding means, 16 display information, 18 additional information layout data displaying means.

Claims (2)

[Claims] 1. A ROM for an integrated circuit with a built-in mask ROM
A mask ROM layout pattern verifying device for verifying a layout pattern created for writing data, comprising: address decoder information describing ROM address information corresponding to the integrated circuit having a built-in mask ROM; ROM truth value data creating means for reading ROM data corresponding to a circuit and creating ROM truth value data; and coordinates based on coordinate value information describing an arrangement position of a ROM rectangle corresponding to the mask ROM built-in type integrated circuit. Value data and a ROM created by the ROM truth value creating means.
Layout data creating means for creating layout data from the truth value data; and additional information layout data created by adding the ROM data, address decoder information, and coordinate value data to the layout data created by the layout data creating means. A mask ROM layout pattern verifying device, comprising: 2. An additional information layout data display means for displaying the additional information layout data created by the layout data information addition means in a different display form according to given display information. Item 3. A mask ROM layout pattern verification device according to Item 1.