JPH05190810A - Mask-rom-layout-pattern verification apparatus - Google Patents

Abstract

PURPOSE:To save labor, time and cost required for verification by omitting the visual confirming work for the displays of the lists of ROM truth value data and the layout pattern of a mask ROM and the tests for the fabrication and the operation of an LSI. CONSTITUTION:The truth value data of the kind of a device having the maximum ROM capacity are held for verification in a verifying truth-value-data storage means 1 for every series. A testing layout pattern corresponding to the kind of the device under development is formed in a verifying layout-pattern forming means 15 based on the truth value data. This pattern is compared with the mask ROM layout pattern of the kind of device under development in a layout comparing means 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM layout pattern verification device used for verifying a layout pattern created for writing a ROM code in a mask ROM built-in type LSI.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing the structure of a conventional mask ROM layout pattern verification device. In the figure, 4 is a ROM code file in which a ROM code for verification is described, and 5 is a ROM code file 4.
ROM code file reading means for reading, ROM address information file 6 for describing ROM address information corresponding to the product type, 7 for ROM address information file 6
Means for reading the ROM address information file. Reference numeral 8 is ROM truth value data creating means for creating truth value data based on the data read from the ROM code file 4 and the ROM address information file 6, and 9 is R
The ROM truth value data storage means for storing the ROM truth value data output by the OM truth value data creation means 8 is shown.
RO is stored in the ROM truth value data storage means 9.
The ROM truth value list which output M truth value data to a printer is shown.

On the other hand, reference numeral 10 is a coordinate value information file which describes at which position on the layout pattern the ROM rectangle corresponding to the product type is to be arranged, and 11 is the coordinate value information which reads the coordinate value information file 10 and creates coordinate value data. File reading means 12 is a coordinate value data storage means for storing the coordinate value data output by the coordinate value information file reading means 11. Further, reference numeral 13 is a mask ROM layout pattern creation for reading the truth value data and the coordinate value data corresponding to the products stored in the ROM truth value data storage means 9 and the coordinate value data storage means 12, respectively, and creating a mask ROM layout pattern. Means, 14 is a mask RO
Mask R output by M layout pattern creating means 13
Reference numeral 24 denotes a mask ROM layout pattern storage means for storing the OM layout pattern, and reference numeral 24 denotes a display of the mask ROM layout pattern output from the mask ROM layout pattern storage means 14 on the display.

Further, 25 is an LSI manufacturing means for manufacturing a mask ROM built-in type LSI based on the mask ROM layout pattern output from the mask ROM layout pattern storage means 14, and 26 is an LSI manufacturing means 25.
An LS that performs an operation test on the LSI manufactured in 1. using the ROM code described in the ROM code file 4.
I operation test means is shown.

Next, the operation will be described with reference to FIG.
First, read the ROM code for verification and perform RO
While creating the M code file 4 (step S2
1) The ROM address information file 6 is created from the ROM address information of the product to be developed using an editor (step S22). Similarly, the coordinate value for generating the ROM rectangle is read from the layout data of the product to be developed, and the coordinate value information file 10 is created using the editor (step S23).

Next, the ROM address information file 6
And read the ROM code file 4 (step S
24, 25), and ROM truth value data is created (step S26). The created ROM truth value data is output as the ROM truth value list 23 (step S27), and the verifier visually checks it (step S28). If there is an abnormality as a result, the process returns to step S22, and RO
Recreate the M address information file 6.

If there is no abnormality in the ROM truth value list, the coordinate value information file 10 is read (step S29),
A mask ROM layout pattern is created based on the truth value data and the coordinate value data (step S30). The created mask ROM layout pattern is displayed on the display (step S31), and the verifier visually checks it (step S32). If there is an abnormality, the process returns to step S23 to recreate the coordinate value information file.

If there is no abnormality in the mask ROM layout pattern, the mask ROM built-in type LSI is actually manufactured based on this pattern (step S33), and the operation test is performed on the manufactured LSI (step S34).
The result is determined (step S35), and if there is no abnormality, the verification process ends, but if there is an abnormality, the ROM address information file is created (step S22) and the procedure is repeated.

[0009]

As described above, the prior art is as follows.
The verifier visually checks the printed ROM truth value list and the mask ROM layout pattern displayed on the display, and the ROM code is the ROM in the LSI.
In order to confirm whether or not the mask ROM layout pattern is correctly arranged and whether or not the mask ROM layout pattern is correctly arranged, it takes a lot of labor and time for the confirmation. Also, in order to verify whether the ROM code is correctly written in the ROM in the LSI, a new type of mask ROM
Each time the verification is required in the development of the built-in type LSI, the LSI has to be actually manufactured and an operation test has to be performed. Therefore, more labor and time are required, and the verification cost is increased. ..

An object of the present invention is to eliminate the need for visual confirmation, LSI manufacturing and operation test.
It is an object of the present invention to provide a mask ROM layout pattern verification device capable of reducing the labor, time and cost required for verification.

[0011]

A first mask ROM layout pattern verification apparatus according to the present invention is a mask RO
For each series of M built-in type LSIs, the verification truth value information storage means for storing the truth value information of the kind having the maximum ROM capacity among the products of this series, and the verification stored in the verification truth value information storage means The verification truth value data creating means for reading the verification truth value information and creating the verification truth value data corresponding to the newly developed product, and the verification truth pattern data and the coordinate value data are read to create the verification layout pattern. And a verification layout pattern creating means,
A layout pattern comparing means for comparing the verification layout pattern and the mask ROM layout pattern is provided.

A second mask ROM layout pattern verifying apparatus according to the present invention further comprises the verifying truth value data created by the verifying truth value data creating means in the first mask ROM layout pattern verifying apparatus, and the ROM. RO created by the truth value data creating means
It is provided with a truth value data comparing means for comparing with the M truth value data.

A third mask ROM layout pattern verification apparatus according to the present invention is the largest ROM among the series of mask ROM built-in type LSIs among the series.
A verification layout pattern information storage unit that stores where on the layout pattern a ROM rectangle of a product model having a capacity is arranged, and a layout pattern stored in the verification layout pattern information storage unit are read and a new product model is developed. A verification layout pattern creating means for creating a corresponding verification layout pattern and a layout pattern comparing means for comparing the verification layout pattern with the mask ROM layout pattern are provided.

[0014]

In the first mask ROM layout pattern verification device, truth value information of a product having the maximum ROM capacity among the products of this series is held for verification in advance for each series, and a new product is developed. Based on the held verification information, the verification truth value data corresponding to the product type, and the verification truth value data and the coordinate value data are used to create a verification layout pattern. Then, the mask ROM layout pattern of the type to be developed is compared with this to verify the mask ROM layout pattern.

In the second mask ROM layout pattern verification device, further, the verification truth value data created from the truth value information of the product having the maximum ROM capacity as described above, and the created product corresponding to the product to be developed. A comparison is also made with the ROM truth value data. Thus, when an abnormality occurs in the layout pattern comparison, it becomes easy to specify whether the cause is the ROM truth value data or the mask ROM layout pattern.

In the third mask ROM layout pattern verification device, a verification layout pattern is stored in advance for each series, in which position on the layout pattern the ROM rectangle of the product having the largest ROM capacity among the products of this series is stored. Since the information is held for verification, when developing a new product, a verification layout pattern corresponding to this product is created based on the held information. Then, the mask ROM layout pattern is verified by comparing it with the mask ROM layout pattern.

[0017]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a mask ROM layout pattern verification device of this embodiment. In the figure, reference numeral 1 denotes a verification truth value information storage means for storing, for verification, truth value information of a product having the largest ROM capacity in each series of mask ROM built-in type LSIs.
Here, the verification truth value information is a unique truth value in which “1” and “0” are alternately arranged as shown in FIG. 2, for example.

Reference numeral 2 is verification information that reads verification truth value information from the verification truth value information storage means 1 and that includes a series name and a bit configuration input from a keyboard and the number of arrays of truth values in the X and Y directions. In accordance with 20, the verification truth value data creating means for automatically creating verification truth value data corresponding to the type of product to be developed, 3 stores the verification truth value data corresponding to the kind output from the verification truth value data creating means 2. 3 shows verification truth data storage means. Reference numeral 4 is a ROM code file in which a ROM code in consideration of the verification truth value data is described, and hereinafter, the same reference numerals as those in FIG. 6 indicate the same or corresponding portions.

Reference numeral 15 reads the verification truth value data and the coordinate value data corresponding to the product stored in the verification truth value data storage means 3 and the coordinate value data storage means 12, respectively, and creates a verification layout pattern. A verification layout pattern creating unit, 16 is a verification layout pattern storage unit that stores the verification layout pattern output by the verification layout pattern creating unit 15. FIG. 3 shows an image of the verification layout pattern stored in the verification layout pattern storage means 16.

Reference numeral 17 is a mask ROM layout pattern storage means 14 and a verification layout pattern storage means 16.
The layout pattern comparing means reads the layout patterns respectively stored in and and compares them.

Next, the operation will be described with reference to FIG.
First, read the ROM code in consideration of verification and read R
While creating the OM code file 4 (step S
1) The ROM address information file 6 is created from the ROM address information of the product to be developed using an editor (step S2). Further, the coordinate value for generating the ROM rectangle is read from the layout data of the product to be developed, and the coordinate value information file 10 is created using the editor (step S3). Up to now, it is the same as the conventional one.

Next, the verification information 20 is input from the keyboard (step S4). Next, based on the truth value information stored in the verification truth value information storage means 1, the verification truth value data corresponding to the product type to be developed is created according to the above verification information (step S5). Further, the coordinate value information file 10 is read (step S6). Then, the verification truth value data stored in the verification truth value data storage unit 3 is read, and a verification layout pattern is created based on the coordinate value data stored in the coordinate value data storage unit 12 (step S7).

On the other hand, the ROM address information file 6 of the type to be developed and the ROM code file 4 are read (steps S8 and S9), and the ROM truth value data is created from the ROM code based on the ROM address information (step S8). S10). Also, coordinate value information file 1
0 is read (step S11), and a mask ROM layout pattern is created from the ROM truth value data (step S12). These processes are also similar to the conventional one.

Finally, the verification layout pattern created in step S7 and the mask R created in step S12.
The OM layout pattern is compared (step S1).
3). If the comparison result is not normal (step S1)
4) Then, the process returns to step S2 to create the ROM address information file 6 again, but if it is normal, the verification process ends. It is not necessary to visually check the list of the ROM truth value data or the display of the mask ROM layout pattern, and it is not necessary to actually manufacture the LSI and perform the operation test thereof.

Example 2. In the first embodiment described above, the verification truth value data stored in the verification truth value data storage means 3 and the ROM truth value data stored in the ROM truth value data storage means 9 are read. ,
If the truth value data comparing means for comparing the two is provided, when an abnormality occurs in the layout pattern comparison by the layout pattern comparing means 17, depending on whether the comparison result by the truth value data comparing means is normal or not. , Is the cause of the abnormality in the ROM truth value data,
Alternatively, it can be verified in a short time whether the mask ROM layout pattern exists.

Example 3. In the above-described embodiment, the truth value information of the product having the maximum ROM capacity is held for each series, and the verification truth value corresponding to this product is developed every time a new product is developed based on this information. The data was created, and the verification layout pattern was created from the verification truth value data and the coordinate value data. The layout pattern information for use may be created and held. FIG. 5 shows an example thereof.
In the figure, 18 is an R of a product having the maximum ROM capacity in each series of mask ROM built-in type LSIs.
A verification layout pattern information storage means for storing the position of the OM rectangle, 19 reads data from the verification layout pattern information storage means 18, and in accordance with the verification information 20 input from the keyboard, the verification layout pattern corresponding to the product type to be developed. Is a verification layout pattern creating means.

In the present embodiment, the layout pattern comparison means 17 includes the verification layout pattern read from the verification layout pattern storage means 16,
The verification is performed by comparing with the mask ROM layout pattern read from the mask ROM layout pattern storage means 14, and in this case also, the list of the ROM truth value data and the display of the mask ROM layout pattern are visually checked and the LSI is manufactured. No operational tests are required.

[0028]

As described above, according to the present invention, truth value information or layout pattern information of the type having the maximum ROM capacity is held for each series, and the developed type is dealt with based on the information. By creating the verification layout pattern and comparing it with the mask ROM layout pattern of this development type, there is an effect that labor, time and cost required for the verification can be reduced.

When a means for comparing the verification truth value data corresponding to the development type created based on the truth value information of the type having the maximum ROM capacity and the ROM truth value data of the development type is added, In comparing layout patterns, when an abnormality occurs, it is possible to verify in a short time whether the cause is the ROM truth value data or the mask ROM layout pattern.

[Brief description of drawings]

FIG. 1 is a block diagram of a mask ROM layout pattern verification device showing an embodiment of the present invention.

FIG. 2 is an image diagram showing an example of verification truth value data.

FIG. 3 is an image diagram showing an example of a verification layout pattern.

FIG. 4 is a flowchart showing the operation of FIG.

FIG. 5 is a block diagram showing another embodiment.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a flowchart showing the operation of FIG.

[Explanation of symbols]

 1 Verification Truth Value Information Storage Means 2 Verification Truth Value Data Creation Means 8 ROM Truth Value Data Creation Means 11 Coordinate Value Information File Reading Means 13 Mask ROM Layout Pattern Creation Means 15, 19 Verification Layout Pattern Creation Means 17 Layout Pattern Comparison Means 18 Layout pattern information storage means for verification

Claims (3)

[Claims] 1. A mask ROM layout pattern verification device for verifying a layout pattern created for writing a ROM code to a mask ROM built-in type LSI, wherein each of the mask ROM built-in type LSI series has the largest product type among the series. Verification truth value information storage means for storing truth value information of a product having a ROM capacity, and verification truth value information stored in the verification truth value information storage device for verification corresponding to a newly developed product A verification truth value data creating means for creating truth value data, a coordinate value information file reading means for reading where a ROM rectangle is arranged on a layout pattern, and coordinate value information file reading means for creating coordinate value data, The verification truth pattern data and coordinate value data are read, and the verification layout pattern And verification for the layout pattern generating means for generating, describing the ROM address information corresponding to the development of varieties RO
M address information file and ROM corresponding to this product type
Read the ROM code file that describes the code,
ROM truth value data creating means for creating ROM truth value data, mask ROM layout pattern creating means for reading coordinate value data and ROM truth value data and creating a mask ROM layout pattern, verification layout pattern and mask ROM layout A mask ROM layout pattern verification device comprising: a layout pattern comparison means for comparing with a pattern. 2. A truth value data comparison means for comparing the verification truth value data created by the verification truth value data creation means with the ROM truth value data created by the ROM truth value data creation means. 2. The mask ROM layout pattern verification device according to claim 1, wherein. 3. A mask ROM layout pattern verifying device for verifying a layout pattern created for writing a ROM code to a mask ROM built-in type LSI, wherein each of the mask ROM built-in type LSI series has the largest product type among the series. A verification layout pattern information storage unit that stores where on the layout pattern a ROM rectangle of a product having a ROM capacity is to be arranged, and a layout product newly developed by reading the layout pattern stored in the verification layout pattern information storage unit A verification layout pattern creating means for creating a verification layout pattern corresponding to the above, and a coordinate value information file that describes where to place the ROM rectangle on the layout pattern, and a coordinate value information file for creating coordinate value data is read. hand RO that describes the ROM address information corresponding to the stage and the development type
M address information file and ROM corresponding to this product type
Read the ROM code file that describes the code,
ROM truth value data creating means for creating ROM truth value data, mask ROM layout pattern creating means for reading coordinate value data and ROM truth value data and creating a mask ROM layout pattern, verification layout pattern and mask ROM layout A mask ROM layout pattern verification device comprising: a layout pattern comparison means for comparing with a pattern.