JP2766921B2 - Layout pattern generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM type L
The present invention relates to an apparatus for generating a layout pattern of a ROM code to be written into an SI.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a configuration of a conventional mask ROM layout pattern generating device. In the figure, reference numeral 1 denotes series information storage means, which is a mask ROM.
It stores the series information of the LSI type having the largest ROM capacity in each series of the built-in LSI, that is, the bit configuration and the address decoder information per bit. The address decoder information generating means 2 is a means for reading series information from the series information storage means 1 and automatically generating address decoder information corresponding to the ROM capacity and the number of bits of the LSI to be created. The address decoder information storage means 4 stores the address decoder information provided from the address decoder information generation means 2.

The ROM code file 8 contains an LSI
ROM code to be written is stored in the ROM
The code reading means 9 reads the ROM code to be created from the ROM code file 8 in byte units,
Based on the address decoder information provided from the address decoder information storage means 4, truth value data mapping information of the ROM to be created (which describes in what order the ROM rectangles are generated) is created. The truth data storage means 10 stores the truth data mapping information of the ROM given from the ROM code reading means 9.

The coordinate value file 5 stores data for arranging the truth data mapping information of the ROM at a predetermined coordinate position on the mask, and the coordinate value data reading means 6 generates the data. The data for arranging the power ROM is read from the coordinate value file 5 and stored in the coordinate value data storage means 7.

[0005] Mask ROM layout pattern generating means
11 generates a mask ROM layout pattern based on the truth value data mapping information of the ROM from the truth value data storage means 10 and the coordinate value data from the coordinate value data storage means 7, and sends the mask ROM layout pattern to an LSI manufacturing apparatus (not shown). Output.

Next, a procedure for creating a mask ROM layout pattern in such a layout pattern generator will be described with reference to a flowchart shown in FIG.
First, a coordinate value file 5 storing coordinate value data on a mask for arranging truth value data mapping information in a ROM is created from graphic data of an LSI (S11). The ROM code to be written to the LSI is, for example, EPROM
And creates the ROM code file 8 (S
12). Next, it is determined whether the series information corresponding to the LSI to be created is stored in the series information storage unit 1 or not (S13). If it is not stored, a series information file (not shown) corresponding to the LSI to be newly created is created (S1).
4), the created series information is stored in the series information storage means 1
(S15).

Next, the LSI series name to be created, R
The OM capacity and the number of bits are input to the address decoder information generating means 2 (S16). When the address decoder information corresponding to the type to be created in S13 is stored in the series information storage means 1, it is not necessary to create a new series information file, and the ROM code file 8 is created (S12). After that, the series name, ROM capacity and bit number of the LSI to be created are input to the address decoder information generating means 2 (S16).

Then, the address decoder information generating means 2
Based on the input data and the series information stored in the series information storage means 1, address decoder information of an LSI to be created is generated and stored in the address decoder information storage means 4 ( S1
7). In the ROM code reading means 9, the ROM code of the LSI to be created is read from the ROM code file 8 in byte units (S18), and the address decoder information is read from the address decoder information storage means 4 and based on these. Then, the truth data mapping information of the ROM is created and stored in the truth data storage means 10 (S19).

It is determined whether the reading of the ROM code is completed (S20). If the reading is not completed, the ROM code is read into the ROM code reading means 9 (S18), and the truth data mapping information of the ROM is created (S19). Are repeated until the reading of the ROM code is completed.
When the reading of the ROM code is completed, the coordinate value data of the LSI to be created is read from the coordinate value file 5 into the coordinate value data reading means 6 and stored in the coordinate value data storage means 7 (S21). Then, the mask RO layout pattern generating means 11 uses the truth value data mapping information and coordinate value data of the ROM to generate a mask RO.
An M layout pattern is generated (S22).

[0010]

As described above, the conventional layout pattern generating apparatus, based on the series information stored in the series information storage means 1 when a new LSI with a built-in mask is to be created. Generate address decoder information, and according to this address decoder information,
The layout pattern of the LSI with a built-in mask is generated.

When the series information for generating the address decoder information of this new LSI with a built-in mask is not stored in the series information storage means 1, for example,
Depending on the generated address decoder information, R
The OM truth value data mapping information is an arrangement angle (90
°, 180 °), when the truth data mapping information of the ROM is created, or when the codes of the truth data mapping information of the ROM are all inverted, the series information is newly added as described above. Create a file,
The bit configuration and the address decoder information per bit had to be registered in the series information storage means 1, which required time and effort. In addition, there is a possibility that a creation error may occur at the stage of creating data to be registered in the series information storage unit 1. Further, there is a problem that the number of data to be registered in the series information storage means 1 increases, and the maintenance becomes complicated accordingly.

The present invention has been made in view of the above circumstances, and has address decoder information editing means. The address decoder information generated based on the series information of an LSI having the maximum ROM capacity in a series for each series is provided. By editing to the address decoder information of the LSI to be created, new series information for generating the address decoder information of the LSI to be created can be created.
An object of the present invention is to provide a layout pattern generation device that generates an LSI layout pattern.

[0013]

A layout pattern generating apparatus according to the present invention stores information for generating the address decoder information of an LSI having the largest ROM capacity in a series, and generates and stores this information. R to be
The address decoder information generated by the capacity and the number of bits of the OM is edited by the address decoder information editing means into address decoder information corresponding to the ROM to be created.
A mask ROM layout pattern is generated from the address decoder information, the ROM code, and the coordinate value data.

[0014]

In the layout pattern generating apparatus according to the present invention, information for generating address decoder information of an LSI having a maximum ROM capacity in a series is stored, and address decoder information corresponding to an LSI to be created is generated. Is not stored, the address decoder information generated based on the stored information and the ROM capacity and the number of bits of the LSI to be created corresponds to the LSI to be created by the address decoder information editing means. Edited to the address decoder information.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is a block diagram showing a configuration of a layout pattern generation device according to the present invention. 1 in the figure
Is series information storage means, which is series information of the LSI type having the largest ROM capacity in each series of LSIs with built-in mask ROM, that is, the bit configuration and 1 bit.
It stores address decoder information per bit.
The address decoder information generating means 2 reads the series information from the series information storage means 1 and generates an LS to be created.
This is a means for automatically generating address decoder information corresponding to the ROM capacity and the number of bits of I. The address decoder information editing means 3 comprises the address decoder information generating means 2
This is a means for editing the address decoder information generated in step (1), for example, for exchanging the X and Y address decoders of the address decoder information or inverting the code of the address decoder information. The address decoder information storage means 4
The address decoder information provided from the address decoder information editing means 3 is stored.

The ROM code file 8 contains an LSI
ROM code to be written is stored in the ROM
The code reading means 9 reads the ROM code to be created from the ROM code file 8 in byte units,
Based on the address decoder information provided from the address decoder information storage means 4, truth data mapping information of the ROM is created. The truth data storage means 10 stores the truth data mapping information of the ROM given from the ROM code reading means 9.

The coordinate value file 5 stores data for arranging the truth data mapping information in the ROM at a predetermined coordinate position on the mask, and the coordinate value data reading means 6 creates the coordinate value data. The data for arranging the code of the ROM to be read is read from the coordinate value file 5, and the coordinate value data storage means 7 stores this.

Mask ROM layout pattern generating means
11 generates a mask ROM layout pattern based on the truth value data mapping information of the ROM from the truth value data storage means 10 and the coordinate value data from the coordinate value data storage means 7, and sends the mask ROM layout pattern to an LSI manufacturing apparatus (not shown). Output.

Next, the procedure for creating a mask ROM layout pattern in the layout pattern generating apparatus of the present invention will be described with reference to the flowchart shown in FIG. First, a coordinate value file 5 storing coordinate value data for arranging truth value data mapping information in a ROM on a mask is created from graphic data of an LSI (S31). The ROM code to be written to the LSI is, for example, EPROM
And creates the ROM code file 8 (S
32). Then, the series name of the LSI to be created, RO
The M capacity and the number of bits are input to the address decoder information generating means 2 (S33).

Based on the data input to the address decoder information generating means 2 and the series information stored in the series information storage means 1, the LS to be created is determined.
I address decoder information is generated (S34).

It is determined whether the series information corresponding to the address decoder information of the LSI to be created is stored in the series information storage means 1 or not (S35). If not, S34 is performed. The address decoder information generated in (1) is edited into address decoder information of the LSI to be created by the address decoder information editing means 3 (S36).

Hereinafter, editing of the address decoder information will be described. If the address decoder information generated in S34 is such that the truth value data mapping information of the ROM which differs from the LSI to be created only in the ROM code arrangement angle is created, the address decoder information editing means 3 The X and Y decoders of the generated address decoder information are exchanged. FIG. 3 is an explanatory diagram showing address decoder information obtained by exchanging the X and Y address decoders. The X decoder 12 has a code 14 and the Y decoder 13 has a code 15. By transposing the respective codes 14 and 15, the X decoder 12 becomes the code 15 and the Y decoder 13
Has the code 14. Such X, Y decoders 12, 13
Is replaced with address decoder information in which the arrangement angle of the ROM of the LSI differs by 90 °.

The address decoder information thus generated is stored in the address decoder information storage means 4 (S37). If the address decoder information generated in S35 corresponds to the LSI to be created, there is no need to edit the address decoder information by the address decoder information editing means 3 and the address decoder information generating means 2 The generated address decoder information is stored in the address decoder information storage means 4 (S3).
7).

In the ROM code reading means 9, the R
LSI ROM to be created from OM code file 8
The code is read one byte at a time (S38), the address decoder information is read from the address decoder information storage means 4, and based on these, truth data mapping information of the ROM is created. It is stored (S39).

It is determined whether the reading of the ROM code is completed (S40). If the reading is not completed, the ROM code is read into the ROM code reading means 9 (S38), and the ROM truth value mapping information is created (S39). Are repeated until the reading of the ROM code is completed.
When the reading of the ROM code is completed, the coordinate value data of the LSI to be created is read from the coordinate value file 5 into the coordinate value data reading means 6 and stored in the coordinate value data storage means 7 (S41). Then, the mask RO layout pattern generating means 11 uses the truth value data mapping information and coordinate value data of the ROM to generate a mask RO.
An M layout pattern is generated (S42).

As described above, in the layout pattern generation device of the present invention, the generated address decoder information can be edited by the address decoder information editing means in correspondence with the address decoder information of the LSI to be created. A mask ROM layout pattern can be generated without creating new series information.

In the layout pattern generating apparatus of the present invention, all the codes of the address decoder information generated by the address decoder information generating means 2 are obtained by reversing the codes of the truth data mapping information of the ROM of the LSI to be created. In some cases, the address decoder information editing means 3 edits the code of the address decoder information.
FIG. 4 is an explanatory diagram for inverting the code of the address decoder. The address decoder 16 has a code 17 and has a code 18 by inverting the code. Thus, the address decoder information generated by the address decoder information generating means 2 is edited into address decoder information in which all codes are inverted. The edited address decoder information generates a mask ROM layout pattern according to the procedure described above.

[0028]

As described above, the layout pattern generating apparatus of the present invention has the address decoder information editing means, and has the largest ROM in the series for each LSI series.
Series information of LSI with capacity and L to be created
Since the address decoder information generated based on the ROM capacity and the number of bits of the SI can be edited in correspondence with the address decoder information of the LSI to be created, information for newly generating the address decoder information is created. Without this, an LSI layout pattern can be generated.
Further, the present invention has excellent effects such as the reliability of the generated mask ROM layout pattern being improved, the number of data stored in the series information storage means being reduced, and the maintenance being easy. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a layout pattern generation device according to the present invention.

FIG. 2 illustrates a layout pattern generator according to the present invention;
9 is a flowchart illustrating a procedure for creating an OM layout pattern.

FIG. 3 is an explanatory diagram showing address decoder information obtained by exchanging X and Y address decoders;

FIG. 4 is an explanatory diagram for inverting a code of an address decoder.

FIG. 5 is a block diagram showing a configuration of a conventional layout pattern generating device.

FIG. 6 shows a conventional layout pattern generation device using RO
9 is a flowchart illustrating a procedure for creating an M layout pattern.

[Explanation of symbols]

 1 Series information storage means 2 Address decoder information generation means 3 Address decoder information editing means 5 Coordinate value file 6 Coordinate value data reading means 8 ROM code file 9 ROM code reading means 11 Mask ROM layout pattern generation means 12,13,16 Address decoder 14,15,17,18 code

Claims (1)

(57) [Claims] 1. An address decoder information for specifying an arrangement of a ROM code of an LSI, and an RO to be written to a ROM.
Generates truth data mapping information of the ROM by the M code, and generates a mask ROM layout pattern based on the truth data mapping information of the ROM and coordinate value data for determining coordinate values on a mask where the truth data mapping information is to be arranged. In a layout pattern generator, a series information storage means for storing information for generating the address decoder information of an LSI having a maximum ROM capacity in a series, and the information and a ROM to be created
Address decoder information generating means for generating address decoder information from the capacity and the number of bits, address decoder information editing means for editing the address decoder information into address decoder information of a ROM to be created,
ROM code reading means for reading the OM code and address decoder information of the ROM to be created and creating truth value mapping information of the ROM; coordinate value data reading means for creating the coordinate value data;
Means for reading OM truth data mapping information and coordinate value data and generating a mask ROM layout pattern.