CN107728045A - FPGA method of testings based on Ultra Flex - Google Patents
FPGA method of testings based on Ultra Flex Download PDFInfo
- Publication number
- CN107728045A CN107728045A CN201710592692.7A CN201710592692A CN107728045A CN 107728045 A CN107728045 A CN 107728045A CN 201710592692 A CN201710592692 A CN 201710592692A CN 107728045 A CN107728045 A CN 107728045A
- Authority
- CN
- China
- Prior art keywords
- fpga
- test
- vector
- flex
- ultra
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
- G01R31/318519—Test of field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
FPGA method of testings based on Ultra Flex, are related to ic test technique, and the present invention comprises the steps：1) Verilog models are established, generate FPGA configuration file and simulation waveform file；2) configuration file, generation programming vector are read；3) read step 1) simulation waveform file, generate test vector；4) Ultra Flex configuration templates and test template are established, uses Ultra Flex compilation tool compiling programming, test vector；5) call Ultra Flex configuration template to read programming vector automatically, call the Ultra Flex automatic read test vector of test template, realize the on-line testing to FPGA.The present invention can improve testing efficiency, reduce testing time cost.
Description
Technical field
The present invention relates to ic test technique, more particularly to Xlinx companies FPGA.
Background technology
Field programmable gate array (Field-Programmable Gate Array, abbreviation FPGA) is a kind of semi-custom
Circuit, developed by programming devices such as PAL, GAL, CPLD.FPGA programmable features are by it no longer as custom circuit one
Sample can not change circuit structure, and internal large-scale gate circuit also overcomes internal gate circuit number deficiency of general programmable period
The shortcomings that.At present FPGA be dispersed throughout data acquisition and interface logic, high performance digital signal processing, automotive electronics, military affairs,
Each important field such as medical treatment.And with the increase of the market demand and the lifting of semiconductor process technique, it may be programmed industry
Development is swift and violent, and FPGA also develops towards the direction that integrated level is higher, performance is stronger, inside structure is more complicated.Thereupon, put
In face of user and FPGA production firms is the test problem of extensive resource inside FPGA, and ATE (Automatic
Test Equipment, ATE) test machine when somewhat expensive, how efficiently, comprehensive test FPGA it is straight
Connect the design cycle for having influence on product and holistic cost.Therefore, present FPGA tests is no longer design in the past, production complete with
End process afterwards, but develop into an important component of the system engineering through whole design, production procedure, setting
The reliability of chip operation is just should be considered as ensureing at the beginning of meter, before putting goods on the market, it is necessary to which it is given birth to
Production test.With the expansion of chip-scale and the increase of complexity, how effectively FPGA comprehensively to be tested, be always
One of the study hotspot in integrated circuit testing field.
FPGA be programming device, it is necessary to programmed configurations after just possess corresponding function, and internal resource huge number,
Easily the digital resource of ten million, so in test process, one-time programming configuration can not possibly cover FPGA whole resources, it is necessary to
According to the species programming and testing several times of FPGA internal resources.Common testing methods are plug-in one piece of FPGA on test circuit plate
Supporting memory chip, every time test are all programmed to memory chip using PC, then deposited using FPGA with supporting
The agreement of memory chip configures FPGA, recycles the ATE (Automatic Test Equipment, ATE) to survey
Examination.Tested by all standing for performing said process repeatedly to complete to FPGA internal resources.But the FPGA of ten million gate leve is complete
Coverage test is, it is necessary to configure hundreds of thousands of times, the above method just requires a great deal of time could complete with manpower.
The content of the invention
The technical problem to be solved by the invention is to provide a kind of FPGA method of testings of automation.
It is the FPGA method of testings based on Ultra-Flex that the present invention, which solves the technical scheme that the technical problem uses,
Comprise the steps：
1) Verilog models are established, generate FPGA configuration file and simulation waveform file；
2) read configuration file in a manner of script, generation meet FPGA programmed configurations sequential and Ultra Flex to
Measure the programming vector of form；
3) read step 1 in a manner of script and eda tool coordinate) simulation waveform file, generation meets Ultra
The test vector of Flex vector format；
4) Ultra Flex configuration templates and test template are established, uses Ultra Flex compilation tool compilation step 2)
Programming, test vector with step 3) generation；
5) call Ultra Flex configuration template to read programming vector automatically, call Ultra Flex test template certainly
Dynamic read test vector, realizes the online programming to FPGA and test.
Further, in addition to step 6)：Change configuration file, return to step 2).Specifically, for a FPGA
The programmed configurations vector of different mode is generated, such as：Serial programming, parallel 8 programmings, parallel 32 programmings etc.；And to cover entirely
Lid test FPGA internal resource, then need to configure different functions to FPGA, using different test vectors, so to FPGA
Configuration and test be one circulation process.
For a FPGA to be measured, the test platform of complete set can be established according to above-mentioned 6 step operations.Test is flat
After platform is established, it is no longer necessary to which artificial interference, Ultra Flex test machines can call corresponding hard according to the template having been cured
Part resource and software resource, FPGA automatic test is realized, collect test data, feedback test result.
Verilog models refer to that according to FPGA internal resources module to be measured writing code using Verilog describes a spy
Fixed digital circuitry functions model.With reference to eda software, Verilog models can generate programmed configurations bit stream corresponding with function
With test emulation wave file.
Programming vector sum test vector refers to that file occurs for the waveform of Ultra Flex test machines, and test machine calls vector,
Binding test machine hardware module can generate the signal for meeting FPGA modularization designs and test sequence.Utilize Ultra Flex test machines
The signal generating module and logic comparison module of passage, signal both can be transmitted to fpga chip, the reality that FPGA is responded can be realized again
When detect, automatic decision tests whether to pass through.
Ultra Flex configuration, test template main function are that the content in configuration vector sum test vector is passed through bar
With the hardware module of test machine, corresponding operation is produced, including waveform occurs, chip response capture to be measured, test result is sentenced
Disconnected and feedback, test data collection etc..
The invention has the advantages that realizing online programmings of the FPGA on Ultra Flex test machines, make FPGA's
Programming and test can be performed automatically by test machine, and generate programming vector with script, eliminate the interference of human factor.
Allow in this way volume production test FPGA improve testing efficiency, reduce testing time cost.
Brief description of the drawings
Fig. 1 is the flow chart of the present invention.
Fig. 2 is the FPGA programmed configurations timing diagrams that embodiment is related to.
Embodiment
Generation test vector and calling test machine resource realize the basic invention of real-time detection of the transmission and response of signal all
It is similar.Because FPGA internal resource species is more, quantity is big, to realize that all standing is tested, it is necessary to repeatedly configuration, Qian Wanmen
Level FPGA resource all standing test, or even need thousands of times of configuration hundreds of.The collocation method of prior art is, in test circuit
Plug-in one is carried out stored bits stream with the supporting flash chips of FPGA to be measured on plate, utilizes flash chip and FPGA communication protocol
To be programmed to FPGA, after the completion of programming, FPGA possesses corresponding function, recalls test vector test.A but flash
Chip can only store a kind of configuration bit-stream, if necessary to test the different resource inside FPGA, it is necessary to continuous programming
New bit is flowed in flash.Programming realizes that not only speed is slow but also needs manual operation, is using PC
One process to waste time and energy.
FPGA configuration bit-stream is converted into Ultra Flex by the present invention using the software of instrument and independent development can be with
The vector of identification, then establishes Ultra Flex templates, calls Ultra Flex hardware to simulate between flash and FPGA
Agreement, realize online programming.FPGA configuration and test can thus be connected, reach the purpose of automatic test.
The present invention using instrument automatically generate Xilinx companies FPGA Ultra Flex (Teradyne Inc. it is a high-end
Test machine) on programmed configurations vector sum test vector, vector is run by Ultra Flex test machines and realized to FPGA's
Online programming, whole testing process is automated, improve testing efficiency.
As one embodiment, the online programming to FPGA tests is realized on Ultra Flex test machines.Flow such as Fig. 1
It is shown, Verilog models are built first, generate the programmed bit stream and simulation waveform file of ASCII fromat；Reuse script and
Eda tool is converted to bit stream and simulation waveform file the atp files of Ultra Flex test function identifications, passes through test machine
It is compiled as pattern files (programming, test vector)；Test machine program is finally write, calls pattern files and test hardware
Module realizes FPGA online programming and test.
Certain ten million gate leve FPGA programmed configurations sequential is as shown in Fig. 2 whole flow process mainly includes 3 parts：Upper electricity is clear
Zero, programming mode selection and bit stream load.FPGA includes 8 specific pins related to programming：CS_B (chip-select pin),
RDWR_B (Read-write Catrol pin), PROG_B (clearing pin), DONE (result pin), INIT_B (initialization pin), M0/
M1/M2 (model selection pin, 3).FPGA configuration mode needs to input the pin in addition to DONE in the programming incipient stage
Corresponding signal, drag down PROG_B, empty the programming data of last time, then draw high INIT_B controls FPGA and enter certain programming mould
Formula (typically chooses Parallel Programming Models, accelerate configured rate), and last can is sent into bit stream according to the programming mode of selection
.After programming successfully, DONE pins can export high level, and no person is low level.
The use of Ultra Flex test machines is more complicated, and only the step on test machine is briefly described here.According to
Generation programming vector sum test vector form, set test machine waveform occurring mode and frequency input signal (timing),
DC level input, output threshold value (level)；The corresponding hardware module of code call is write again, vector is converted to actual
Input waveform is sent into the FPGA of test to be programmed；The output of detection DONE pins judges whether programming succeeds, and test machine is sentenced automatically
Whether consistent with the expectation of test vector, the feedback test result of response of disconnected fpga chip.
Claims (2)
1. the FPGA method of testings based on Ultra-Flex, it is characterised in that comprise the steps：
1) Verilog models are established, generate FPGA configuration file and simulation waveform file；
2) configuration file is read in a manner of script, generation meets FPGA programmed configurations sequential and Ultra Flex Vector Lattices
The programming vector of formula；
3) read step 1 in a manner of script and eda tool coordinate) simulation waveform file, generation meets Ultra Flex's
The test vector of vector format；
4) Ultra Flex configuration templates and test template are established, uses Ultra Flex compilation tool compilation step 2) and step
Rapid 3) programming of generation, test vector；
5) call Ultra Flex configuration template to read programming vector automatically, call Ultra Flex test template to read automatically
Test vector is taken, realizes the on-line testing to FPGA.
2. the FPGA method of testings based on Ultra-Flex as claimed in claim 1, it is characterised in that also including step 6)：
Change configuration file, return to step 2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710592692.7A CN107728045A (en) | 2017-07-19 | 2017-07-19 | FPGA method of testings based on Ultra Flex |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710592692.7A CN107728045A (en) | 2017-07-19 | 2017-07-19 | FPGA method of testings based on Ultra Flex |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107728045A true CN107728045A (en) | 2018-02-23 |
Family
ID=61201292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710592692.7A Pending CN107728045A (en) | 2017-07-19 | 2017-07-19 | FPGA method of testings based on Ultra Flex |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107728045A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109444723A (en) * | 2018-12-24 | 2019-03-08 | 成都华微电子科技有限公司 | A kind of chip detecting method based on J750 |
| CN110632499A (en) * | 2019-09-23 | 2019-12-31 | 珠海格力电器股份有限公司 | Test vector generation method based on test object and storage medium |
| CN111983438A (en) * | 2020-08-31 | 2020-11-24 | 中国电子科技集团公司第五十八研究所 | On-line programming test method for FPGA |
| CN112083321A (en) * | 2020-09-17 | 2020-12-15 | 安庆师范大学 | Circuit testing method, storage medium and device based on hidden Markov model |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104515947A (en) * | 2014-12-12 | 2015-04-15 | 中国电子科技集团公司第五十八研究所 | Rapid configuration and test method for programmable logic device in system programming |
-
2017
- 2017-07-19 CN CN201710592692.7A patent/CN107728045A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104515947A (en) * | 2014-12-12 | 2015-04-15 | 中国电子科技集团公司第五十八研究所 | Rapid configuration and test method for programmable logic device in system programming |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109444723A (en) * | 2018-12-24 | 2019-03-08 | 成都华微电子科技有限公司 | A kind of chip detecting method based on J750 |
| CN109444723B (en) * | 2018-12-24 | 2020-07-24 | 成都华微电子科技有限公司 | Chip testing method based on J750 |
| CN110632499A (en) * | 2019-09-23 | 2019-12-31 | 珠海格力电器股份有限公司 | Test vector generation method based on test object and storage medium |
| CN110632499B (en) * | 2019-09-23 | 2021-04-23 | 珠海格力电器股份有限公司 | Test vector generation method based on test object and storage medium |
| CN111983438A (en) * | 2020-08-31 | 2020-11-24 | 中国电子科技集团公司第五十八研究所 | On-line programming test method for FPGA |
| CN112083321A (en) * | 2020-09-17 | 2020-12-15 | 安庆师范大学 | Circuit testing method, storage medium and device based on hidden Markov model |
| CN112083321B (en) * | 2020-09-17 | 2023-06-30 | 安庆师范大学 | Circuit testing method, storage medium and device based on hidden Markov model |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106291336B (en) | A kind of real-time method for down loading of FPGA test configurations code stream and system | |
| CN107728045A (en) | FPGA method of testings based on Ultra Flex | |
| US5867395A (en) | Gate netlist to register transfer level conversion tool | |
| CN106771991B (en) | Automatic testing method applied to antifuse Field Programmable Gate Array (FPGA) before programming | |
| CN110046387A (en) | A kind of SM2 module verification platform and verification method based on UVM | |
| CN102169846B (en) | Method for writing multi-dimensional variable password in parallel in process of testing integrated circuit wafer | |
| CN109739766A (en) | A kind of system and method for fast construction FPGA digital simulation model | |
| CN103308846B (en) | Method and device for detecting functional performance of integrated chip based on model identification | |
| CN109582525A (en) | Test code verification method, verifying device, equipment and storage medium | |
| US7047174B2 (en) | Method for producing test patterns for testing an integrated circuit | |
| CN104515947A (en) | Rapid configuration and test method for programmable logic device in system programming | |
| CN104793171A (en) | Fault simulation based smart meter fault detection method | |
| CN115684896B (en) | Chip testability design test method, test platform, and generation method and device thereof | |
| CN115098400B (en) | FPGA software simulation test environment establishment method based on SVA formal verification | |
| CN109426594A (en) | A kind of chip debugging apparatus, method and computer readable storage medium | |
| US6609230B1 (en) | Method for design verification using modular templates of test benches | |
| US8868396B1 (en) | Verification and debugging using heterogeneous simulation models | |
| CN103678075A (en) | Complex microprocessor test method based on automatic vector generation technology | |
| CN113341296B (en) | ATE-based SOC chip testing method | |
| CN115684894B (en) | Test method and test platform for chip testability design | |
| CN103165405A (en) | Mutli-dimensional variable code real-time generation method through general purpose interface bus (GPIB) interface | |
| CN113434390B (en) | FPGA logic comprehensive tool fuzzy test method based on variation | |
| GB2412444A (en) | Tools and methods for circuit scan test models | |
| CN107908912A (en) | A kind of automatic method for checking line power and being connected to ground | |
| Melnik et al. | Modeling methods of the test inputs for analysis the digital devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20180223 |
|
| WD01 | Invention patent application deemed withdrawn after publication |