CN106777571A - A kind of FPGA algorithmic block automatic Verification platform realized based on System Verilog - Google Patents
A kind of FPGA algorithmic block automatic Verification platform realized based on System Verilog Download PDFInfo
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- CN106777571A CN106777571A CN201611081219.4A CN201611081219A CN106777571A CN 106777571 A CN106777571 A CN 106777571A CN 201611081219 A CN201611081219 A CN 201611081219A CN 106777571 A CN106777571 A CN 106777571A
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- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract
The present invention provides a kind of FPGA algorithmic block automatic Verification platform realized based on System Verilog, including top layer test module, test and excitation automatically-generating module, virtual interface link block, algorithms library, reference model set up module and check module automatically.Top layer test module opens test command, data are produced in excitation automatically-generating module, measurand and reference model are delivered to by virtual interface link block, measurand is processed as requested after receiving data, reference model is also processed data, the data of generation are passed through empty mouth link block and are delivered to automatic to check that module compares treatment, checks that module exports the result of comparison by last measurand, reference model.The present invention is separated test platform with measurand by the way of the virtual interface of Systerm Verilog, test platform is not changed significantly with the change of test object, and reuse rate is high.
Description
Technical field
The present invention relates to nuclear power station FPGA emulation testings field, particularly relate to a kind of realize based on System Verilog
FPGA algorithmic block automatic Verification platform.
Background technology
General nuclear power plant instrument control equipment can be related to the On Configuration of algorithmic block.To ensure the correctness of algorithmic block, need
Algorithmic block is tested in detail, the algorithmic block being related in configuration algorithm figure is more, and to modules as far as possible
Exhaustive more example, to ensure that algorithmic block runs correctly in several cases.If manually input stimulus, then check
Method does test, test case can be caused to cover incomplete, the problems such as waste substantial amounts of human resources.
Also there is the test of automation at present for the test of algorithmic block, by the generation of Random Test Stimulus, reference model
Build, the result that the result for finally collecting is exported with reference model is compared in real time, realize the inspection of automation.Typically
The setting of this automation, be directed to single measurand and carry out test, or measurand has identical to be input into, output connects
Mouth, or the function of measurand is similar.
But the function of algorithmic block is various, the form of the input interface of different algorithmic block is different, causes test platform
Reusability is low, often surveys a module, it is necessary to manufacture the input data of different forms, to calculate the corresponding expection of input stimulus
Value, substantially reduces the efficiency of automatic test.
DUT pairs of traditional automatic test platform test as if fixed, or input, output interface be similar but right
It is many in interface variation, when the big test object of changes of function is emulated, platform is changed on a large scale, make the weight of platform
Relatively low with property, test and excitation does not have randomness, and the various informative property of test module input interface causes the degree of automation to drop
It is low.
The content of the invention
Situation of the purpose of the present invention aiming at above-mentioned prior art, it is proposed that one kind is based on System Verilog realities
Existing FPGA algorithmic block automatic Verification platform, by using the mode of System Verilog virtual interfaces, realizes flat
The reusability of platform, is reduced because of the change of test object, and the amplitude of variation of platform is excessive, influences the problem of the efficiency of test.
The purpose of the present invention is achieved through the following technical solutions：It is a kind of based on System Verilog realize can
Programmed logic algorithmic block automatic Verification platform, including the connection of top layer test module, test and excitation automatically-generating module, virtual interface
Module, algorithms library, reference model set up module and check module automatically；
The top layer test module is used for interface statement, and for calling the test and excitation automatically-generating module, virtual connection
Mouth link block, algorithms library, reference model set up module and check module automatically；
The virtual interface link block is used to stating that test and excitation automatically-generating module, reference model to set up module, automatic
The virtual interface of module and measurand connection is checked, and these virtual interfaces are classified, automatically generated with the test and excitation
Module, reference model set up module and check that module is connected with automatic, set up automatic performing for task；
The test and excitation automatically-generating module is used for the generation of test and excitation, and the data to being input into carry out the life of randomization
Into or constraint excitation scope, the data of test and excitation are delivered in measurand and reference model by virtual interface；
The algorithms library is used to storing the reference model to be set up module and builds the conventional algorithm of reference model；
It is corresponding with measurand for calling algorithm to set up from the algorithms library that the reference model sets up module
Reference model, carries out the treatment of anticipatory data, and the data after treatment are transmitted into automatic inspection module by virtual interface；
It is pre- that the real time data and reference model that the automatic inspection module is used for automatic contrast measurand output are exported
Issue evidence.
Further, described algorithms library is also connected by DPI interfaces with C language, calls the mathematical function in C language.
Further, the algorithm of described algorithms library sets according to tested object, including the computing that takes absolute value, two points look into
Look for method, the transfer algorithm of data integer full mold.
The beneficial effects of the invention are as follows：
The present invention separates test platform with measurand by the way of Systerm Verilog virtual interfaces, surveys
The module for trying platform interior is connected using virtual interface, so as to ensure the independence of various pieces.Avoid the change of design, band
To the change that test platform is larger.This test platform builds the test for adapting to various algorithmic blocks, improves the efficiency of checking,
In addition this platform has a very strong flexibility, such as tackle used in nuclear power station to simulation hand pick up algorithm aman, input signal is all
Influenceed by signal is enabled, to improve verification efficiency, set up an aman_interface, including all of input signal and one
Individual enable signal, when signal intensity is enabled, all of input signal changes therewith.
Using above-mentioned platform, to distinct interface, when the algorithmic block of difference in functionality is verified, it is only necessary to the lower reference of modification
The function of model, and measurand interface type, just complete separate modular checking.
Additionally, building for algorithmic block reference model, has DPI to connect using Systerm Verilog with C language built-in function
Mouthful, call the mathematical function commonly used in C language, such as exp, power, log, abs to build the general algorithms library of verification platform, aid in
The foundation of measurand reference model.
Brief description of the drawings
Fig. 1 is a kind of FPGA algorithmic block automatic Verification platform realized based on System Verilog of the present invention
Paralell composition；
Fig. 2 is a kind of FPGA algorithmic block automatic Verification platform realized based on System Verilog of the present invention
Data flow figure.
Specific embodiment
The FPGA algorithmic block based on System Verilog realizations a kind of to the present invention is automatic below in conjunction with the accompanying drawings
Change verification platform to be described further：The embodiment is only illustrative of the invention and is not intended to limit the scope of the invention, ability
Modification of the field technique personnel to the various equivalent form of values of the invention falls within the application appended claims limited range.
As shown in figure 1, being a kind of FPGA algorithmic block realized based on System Verilog of the present invention
Automatic Verification platform, including top layer test module, test and excitation automatically-generating module, virtual interface link block, algorithms library, ginseng
Examine model building module and automatic inspection module；
The top layer test module is used for interface statement, and the interface that measurand is connected is linked into verification platform, opens
The operation of dynamic verification platform；The top layer test module calls test and excitation automatically-generating module, virtual interface link block, algorithm
Storehouse, reference model set up module and check module automatically, as follows：
Import alg_pkg::*；
`include"real_sig_if.sv"
`include"bool_sig_if.sv"
`include"real_sig.sv"
`include"bool_sig.sv"
`include"bool_aman_if.sv"
`include"bool_aman_sig.sv"
`include"autocheck.sv"
`include"auto_stimula.sv"
`include"test_bench.sv"
....
The virtual interface link block is used to stating that test and excitation automatically-generating module, reference model to set up module, automatic
The virtual interface of module and measurand connection is checked, and these virtual interfaces are classified, with test and excitation generation module, reference
Model building module checks that module is connected with automatic, sets up automatic performing for task, as follows：
The test and excitation automatically-generating module is used for the generation of test and excitation, and the data to being input into carry out the life of randomization
Into or constraint excitation scope, the data of test and excitation are delivered in measurand and reference model by virtual interface.
The algorithms library is used to store builds the conventional algorithm of reference model, the characteristics of the algorithm is directed to tested object
And set, the computing that such as takes absolute value, binary chop, the transfer algorithm of data integer full mold；Described algorithms library also passes through
DPI interfaces are connected with C language, call the mathematical function in C language.
Data type usually designer oneself definition of measurand is input to, is needed this in reference model
Data type conversion is planted into real number, facilitates the treatment of later data, this algorithm is written in algorithms library, it is straight in reference model
Connect to call and use；Additionally the binary chop used in algorithmic block can be written to algorithms library with System Verilog
In.It is as follows：
Class math_alg；
static function real bits_to_real(bit[29:0]bits)；
........
Endfuntcion
Endclass
It is corresponding with measurand for calling data to set up from the algorithms library that the reference model sets up module
Reference model, carries out the treatment of anticipatory data, and the data after treatment are transmitted into automatic inspection module by virtual interface.
It is pre- that the real time data and reference model that the automatic inspection module is used for automatic contrast measurand output are exported
Issue evidence.
Enter line interface statement in top layer test module, statistics is test for algorithmic block, and its data type used there are two kinds,
One kind is real_sig, and one kind is bool_sig, enable bit ena of the real_sig data types comprising data, quality position
Quality, measurement range selection position select, value bit value, bool_sig data type include enabling signal ena_l, quality position
Quality_l, value bit value_l, set up following interface statement：
The transaction processor of interface driver is set up, is easy to calling for test and excitation automatically-generating module, such as bool_sig：
The present invention is separated verification platform and measurand using virtual interface, reduces what test platform was changed by design
Influence.The species of the algorithmic block of test is various, and interface is also different, when interface name is changed, using the platform, uses
Family need not change the method for driving this port, as long as in top layer test module, virtual interface to be tied to the entity of correspondence connection
Interface, and correction reference model.Data flow is as shown in Figure 2 in test process.
During test execution, test execution is opened by top layer test module, data first are produced in excitation automatically-generating module,
Measurand DUT and reference model are delivered to by virtual interface link block.Measurand DUT is located after receiving data
Reason, reference model is also processed data, and the data that last measurand DUT, reference model will be produced pass through empty mouth and connect
Module is delivered to and automatic checks that module compares treatment, checks the result that module output is compared, test completion.
Key point of the invention is the connected mode that virtual interface is used in test platform and measurand, of the invention excellent
Point：
(1) by the way of the virtual interface of Systerm Verilog, test platform is separated with measurand, makes test
Platform does not change significantly with the change of test object；
(2) this test platform is more flexible, only needs to change measurand, and the work(for checking for the test of algorithms of different block
The test of algorithmic block can be can be achieved with, in experiment, 96 tests of algorithmic block is completed using the test platform, test effect ratio
It is more satisfactory；
(3) this verification platform contains algorithms library, the test to disparate modules, writes reference model or audit function, calls
Related algorithms library, improves verification efficiency.
Embodiment 1：The checking of POW (power function) algorithmic block
It is respectively the truth of a matter and power, an output that POW algorithmic blocks have two inputs.Three kinds of types of input are long real
Form, first defining interface are real_sig_if, and the input of virtual interface type is stated in virtual interface link block, and output is defeated
Enter signal respectively with test and excitation automatically-generating module, automatic to check that module is connected, output signal checks that module is connected with automatic,
Top layer test module states the interface signal of input and output, is connected respectively to measurand and the corresponding letter of virtual interface link block
On number.Test and excitation automatically-generating module is called, it is satisfactory defeated that the module calls randomly generated test problems randomize to produce
Enter data type, according to the requirement of data form in reference model sets up module, call bits_to_real letters in algorithms library
Input data, is changed into corresponding real number by number, recycles DPI interfaces, calls the POW functions in C language, completes POW modules ginseng
The foundation of model is examined, expected output valve is calculated, checks that module is compared the value with measurand DUT output valves automatic
Compared with the range of requiring, then test passes through error, not in the range of requiring, does not pass through.
Embodiment 2：Simulation hand grasps the checking of algorithmic block
Simulation hand behaviour's algorithmic block includes 6 inputs of bool_signal types, 10 parameter inputs and 5 of real types
The output of individual bool_signal types, 6 input signals are controlled by signal ena, and when ena changes, 6 input signals are together sent out
Changing.According to the feature, an interface statement of bool_aman_if is set up, signal, and 6 are enabled comprising a bool type
Individual input signal.The input signal of bool_aman_if is stated in top layer test module, the argument of real_sig_if types is defeated
Enter, and bool_sig_if output signal.Call virtual interface link block in top-level module, realize the interface of measurand with
Virtual interface link block is connected, and calls test and excitation automatically-generating module to check module with automatic, by virtual interface link block
Two modules are connected.Random function is called in test and excitation generation module, random test use-case is produced；Reference model sets up mould
Block calls the function write in advance in algorithms library, sets up the reference model consistent with aman functions of modules；aman_alg::av_
Alg functions realize Core Feature, and the output of valve position is exported according to the requirement for setting speed.It is automatic to check that module receives measurand
The result for setting up module output with reference model carries out automatic contrast treatment, exports the result for comparing, and test is completed.
Claims (3)
1. it is a kind of based on System Verilog realize FPGA algorithmic block automatic Verification platform, it is characterised in that bag
Include top layer test module, test and excitation automatically-generating module, virtual interface link block, algorithms library, reference model set up module and
It is automatic to check module；
The top layer test module is used for interface statement, and for calling the test and excitation automatically-generating module, virtual interface to connect
Connection module, algorithms library, reference model set up module and check module automatically；
The virtual interface link block is used to state that test and excitation automatically-generating module, reference model set up module, automatic inspection
Module and the virtual interface of measurand connection, and classify these virtual interfaces, with the test and excitation automatically-generating module,
Reference model sets up module and checks that module is connected with automatic, sets up automatic performing for task；
The test and excitation automatically-generating module be used for test and excitation generation, to be input into data carry out randomization generation or
The scope of excitation is constrained, the data of test and excitation are delivered in measurand and reference model by virtual interface；
The algorithms library is used to storing the reference model to be set up module and builds the conventional algorithm of reference model；
The reference model sets up module for calling algorithm to set up the reference corresponding with measurand from the algorithms library
Model, carries out the treatment of anticipatory data, and the data after treatment are transmitted into automatic inspection module by virtual interface；
The automatic inspection module is used for the real time data of automatic contrast measurand output and the expected numbers of reference model output
According to.
2. a kind of FPGA algorithmic block realized based on System Verilog according to claim 1 is chemically examined automatically
Card platform, it is characterised in that described algorithms library is also connected by DPI interfaces with C language, calls the mathematical function in C language.
3. a kind of FPGA algorithmic block based on System Verilog realizations according to claim 1 or 3 is automatic
Change verification platform, it is characterised in that the algorithm of described algorithms library sets according to tested object, including the computing that takes absolute value,
The transfer algorithm of binary chop, data integer full mold.
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Cited By (7)
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| CN108829382A (en) * | 2018-06-05 | 2018-11-16 | 北京中电华大电子设计有限责任公司 | A method of reference model, which is established, with Python improves automatic Verification platform efficiency |
| CN109101389A (en) * | 2018-08-01 | 2018-12-28 | 济南浪潮高新科技投资发展有限公司 | A kind of test vector generating method and device for PCIE interface |
| CN109116065A (en) * | 2018-09-21 | 2019-01-01 | 北京广利核系统工程有限公司 | A kind of test method and device of high dither filtering |
| CN109375606A (en) * | 2018-09-21 | 2019-02-22 | 北京广利核系统工程有限公司 | A kind of algorithm library test method |
| CN110704260A (en) * | 2019-09-11 | 2020-01-17 | 无锡江南计算技术研究所 | Reusable method for processor IO register test excitation |
| CN111061629A (en) * | 2019-11-21 | 2020-04-24 | 中国航空工业集团公司西安航空计算技术研究所 | Graphic command pre-decoding unit verification platform based on Verilog |
| CN112069756A (en) * | 2020-09-02 | 2020-12-11 | 中国航空工业集团公司西安飞行自动控制研究所 | Programmable logic verification architecture and implementation method thereof |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108829382A (en) * | 2018-06-05 | 2018-11-16 | 北京中电华大电子设计有限责任公司 | A method of reference model, which is established, with Python improves automatic Verification platform efficiency |
| CN108829382B (en) * | 2018-06-05 | 2021-09-21 | 北京中电华大电子设计有限责任公司 | Method for improving efficiency of automatic verification platform by building reference model with Python |
| CN109101389A (en) * | 2018-08-01 | 2018-12-28 | 济南浪潮高新科技投资发展有限公司 | A kind of test vector generating method and device for PCIE interface |
| CN109116065A (en) * | 2018-09-21 | 2019-01-01 | 北京广利核系统工程有限公司 | A kind of test method and device of high dither filtering |
| CN109375606A (en) * | 2018-09-21 | 2019-02-22 | 北京广利核系统工程有限公司 | A kind of algorithm library test method |
| CN110704260A (en) * | 2019-09-11 | 2020-01-17 | 无锡江南计算技术研究所 | Reusable method for processor IO register test excitation |
| CN111061629A (en) * | 2019-11-21 | 2020-04-24 | 中国航空工业集团公司西安航空计算技术研究所 | Graphic command pre-decoding unit verification platform based on Verilog |
| CN112069756A (en) * | 2020-09-02 | 2020-12-11 | 中国航空工业集团公司西安飞行自动控制研究所 | Programmable logic verification architecture and implementation method thereof |
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