CN100405323C - Method for realizing supporting of EJTAG detection in instruction grade random detection - Google Patents
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Abstract
This invention discloses a method supporting EJTAG test in dictation random testing. It includes the following steps: add SDBBP/DRET dictation to the library; add corresponding restriction to the dictation stencil; generate engine to improve the random testing; add executive mechanism of SDBBP/DRET to the simulator and add debugging control register; add input/output signals and comparison logic in simulating circumstance; pre-store EJTAG debugging exceptional processing program in memorizer. This invention not only preserves advantages of traditional dictation random testing, but also supports testing and validating the debugger on the EJTAG.
Description
Technical field
The present invention relates to the micro-processor verification technology, particularly a kind of method of in the instruction grade stochastic test, supporting to strengthen JTAG (Enhanced Joint Test Action Group is hereinafter to be referred as EJTAG) test.
Background technology
The instruction grade stochastic test is the common method of general purpose microprocessor checking, as shown in Figure 1, generally includes five parts: instruction database 11, command template 12, generation engine 13, instruction-level simulator 14, simulated environment 15.Comprise all effective instructions that processor is supported in the instruction database 11; Command template 12 is a series of configuration files, the configuration that is used to instruct, standard and filtration; Producing engine 13 can effectively support the instruction under the configuration file constraint to generate; Instruction-level simulator 14 is the simplest reference models of microprocessor to be verified, supports instruction-level emulation, and the correct execution result of instruction is provided; Simulated environment 15 is to be wrapped in outer field a series of logics of processor to be verified and operation, mainly comprises initialization, I/O and Compare Logic, can carry out initialization, I/O and signal and relatively wait sequence of operations.When carrying out the instruction grade stochastic test, produce engine and from instruction database, choose satisfactory operational code according to the constraint that command template provides, add the operand that meets constraint, produce an instruction that meets constraint, offer simulated environment, after treated device is carried out, the result is outputed to Compare Logic in the simulated environment; Simultaneously, this instruction also offers instruction-level simulator, and the analog result of instruction is as also offering Compare Logic in the simulated environment with reference to value, the mistake in relatively can measurement processor designing by the two.
Along with embedded system is widely used in growing field, the checking of embedded microprocessor nuclear also more and more comes into one's own, and many verification techniques that were applied in general processor originally also are transplanted in the checking of embedded microprocessor nuclear.Yet some characteristics of embedded microprocessor nuclear can propose new challenge to the general processor verification technique.Different with general processor, for the ease of software development and debugging, need provide the intersection debugger during design of embedded microprocessor nuclear.The debugger that intersects is made up of functional processing module, controlling application program module two parts: functional processing module operates on the host, and the controlling application program module operates on the target machine.The debugger major function of intersecting is the executable code of commissioning test on target machine, executive routine generally should be able to be provided, add basic debug functioies such as deleting breakpoint, single step execution, modification code, check and revise variate-value.
Debugging (On Chip Debugging) is the common method that realizes the intersection debugger on the sheet.In the extra control module of the inner embedding of processor, when having satisfied certain trigger condition, enter certain special state.Under this state, debugged program is out of service, and the debugger of main frame can be visited various resources (register, storer etc.) and execution command by the outside ad hoc communication interface of processor.EJTAG be on the embedded type CPU by a hard-wired module, be used to realize debugging on the sheet, assist to develop the transplanting, operation development board diagnostic routine of board monitoring program and OS etc.The attainable function of EJTAG comprises that the employing various modes is provided with Hardware Breakpoint, single step execution etc., implementation: processor (comprises single-step debug in certain debugging exception, Hardware Breakpoint or the like) enters under the debugging mode after the generation, withdraw from debugging mode later until the DRET instruction is carried out.During this period, processor is carried out the debugging exception handler, in exception handler, can carry out various EJTAG operations.Common EJTAG debugging exception is referring to table 1.System withdraws from debugging mode and allows application program or system code to continue to carry out later on.
| The exception title | Describe |
| Single-step debug (Debug Single Step) | The single-step debug exception of EJTAG |
| (Debug Interrupt) interrupted in debugging | The debugging of EJTAG is interrupted, and EJ_DINT causes by the external signal input, perhaps by the initiation that is provided with of the EjtagBrk position in the ECR register |
| Debug command breakpoint exception (Debug Instruction Break) | EJTAG debug hardware instruction breakpoint exception EJTAG debug hardware instruction break matched. |
| Debugging software breakpoint (Debug Software Breakpoint) | Because the EJTAG breakpoint that causes is carried out in the SDBBP instruction |
| Debugging storage/access data breakpoint (Debug Data Break Load/Store) | The data address breakpoint that EJTAG produces when Load, the data address that when Store, produces and value breakpoint |
Table 1
For the embedded type CPU checking that comprises intersection debugger on the EJTAG sheet, traditional instruction grade stochastic measuring technology, only consider the simulating, verifying of continual command, do not cover test and the checking of EJTAG, and, obviously be absolutely necessary at the checking of EJTAG as an ingredient of embedded type CPU.At present, test EJTAG mainly realizes with the method for hand-written test vector, by enumerating the various states of EJTAG, the employing expert manually writes the test vector at each test point, and the shortcoming of this method maximum is to expend a large amount of hand labors, inefficiency, simultaneously, because the various combinations of states of EJTAG are very complicated, be difficult to exhaustively, hand-written test vector is difficult to evenly cover all test points.
In sum, because the deficiencies in the prior art, people are desirable to provide a kind of method of improved instruction grade stochastic test embedded type CPU, when keeping traditional instruction level random test advantage, effectively support to comprise the test and the checking of the microprocessor core of intersection debugger on the EJTAG sheet.
Summary of the invention
The objective of the invention is to overcome the deficiency that existing instruction grade stochastic measuring technology can't realize intersection debugger test on the sheet, thereby provide a kind of method of in the instruction grade stochastic test, supporting the EJTAG test, this method can effectively support to comprise the test and the checking of the microprocessor core of intersection debugger on the EJTAG sheet, does not influence instruction grade stochastic simultaneously and tests original performance advantage.
In order to achieve the above object, the present invention is achieved by the following technical solutions:
A kind of implementation method of supporting to strengthen the JTAG test in the instruction grade stochastic test comprises the steps:
Step 1), read and resolve command template;
Step 2), the decision instruction sequence length whether with described command template in constrained parameters be complementary; If then execution in step 15), finish whole verification process, if not, execution in step 3);
Step 3), from instruction database, choose instruction according to the various constraints that define in the described command template;
Step 4), stochastic instruction produce the requirement generation valid instruction of engine according to processor architecture, and the additional signal relevant with this instruction, comprise instruction breakpoint and data breakpoint in described additional signal;
Step 5), according to produce the instruction type, following processing is carried out in instruction:
Step 5-1), judge whether the instruction produced is the branch transition instruction, if, then carry out next step, otherwise, execution in step 5-3);
Step 5-2), by the identifying operation code labeling and write down the instruction of all branch transition, carry out next step then;
Step 5-3), judge whether the instruction produced is the load/store access instruction, if, then carry out next step, otherwise, direct execution in step 5-5);
Step 5-4), according to described load/store access instruction and access address thereof, after record and access data write down, carry out next step;
Step 5-5), finish randomly drawing and record of program counter value;
Instruction-level simulator and simulated environment are sent in step 6), the instruction that will classify after handling respectively, distinguish execution in step 7 then) and step 8);
Step 7), in described instruction-level simulator, judge whether to be breakpoint, if, then revise control corresponding register and debugging control register, the exception cue is set simultaneously according to concrete debugging breakpoint type, if not, then revise general-purpose register, flating point register and internal memory; Last execution in step 9);
Step 8), in described simulated environment, the instruction of sending into is loaded in the microprocessor to be measured moves, described operation result is kept in register and the internal memory, then the result who is preserved is outputed in the described simulated environment by signal wire;
Step 9), the execution result of the resulting instruction-level simulator of step 7) is sent into simulated environment, be used for comparing with the resulting instruction execution result of step 8);
Step 10), in simulated environment, judge whether to have taken place debugging breakpoint exception; If carry out next step; If not, execution in step 12);
Step 11), relatively whether debugging exception operation result consistent with described instruction-level simulator simulation result, if, execution in step next step; If not, execution in step 13);
Whether step 12), standard of comparison instruction operation result be consistent with described instruction-level simulator simulation result, if then execution in step 2), if not, execution in step 14);
Step 13), send the warning that makes mistakes of debugging exception, abnormal end proof procedure;
Step 14), send the stereotyped command warning that makes mistakes, abnormal end proof procedure;
Step 15), simulated program fair termination.
In the technique scheme, in described step 3), the various constraints that define in the described command template comprise the constraint relevant with debug command, the described constraint relevant with debug command comprises: one is that each bar SDBBP instruction must have a DRET instruction to be complementary with it, and another is new parameter to be set be used to adjust the ratio that the debugging exception takes place.
In the technique scheme, in described step 4), programmable counter, branch transition command prompt signal, debugging exception count signal that stochastic instruction produces programmable counter useful signal that engine produces random extraction, load/store command prompt signal, the address of randomly drawing that is complementary with the load/store instruction, the data of randomly drawing that are complementary with the load/store instruction, is complementary with the load/store instruction.
Compared with prior art, the invention has the beneficial effects as follows:
Traditional instruction grade stochastic measuring technology is carried out effective transformation, has made it when keeping traditional instruction level random test advantage, effectively to support to comprise the test and the checking of the microprocessor core of intersection debugger on the EJTAG sheet, specifically comprised two aspects:
1) test more comprehensively: traditional hand-written test vector is difficult to accomplish the even covering to all test spaces, and relies on random test to produce, and can make test vector to the covering of the test space more comprehensively, evenly.
2) testing efficiency height: hand-written test vector needs a large amount of test experts' hand labor, and efficient is low, and random test produces the automatic generation that can realize test vector substantially, saves a large amount of human resources, the efficient height.
Description of drawings
Fig. 1 is an instruction-level random test system architecture synoptic diagram in the prior art;
Fig. 2 is the implementation method process flow diagram that the present invention is applied to the instruction grade stochastic test macro;
Fig. 3 is the specific embodiment synoptic diagram that the present invention is applied to the instruction grade stochastic test macro;
Fig. 4 is the implementation process flow diagram that the present invention is applied to the instruction grade stochastic test macro.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail:
As shown in Figure 2, a kind of method of supporting the EJTAG test in the instruction grade stochastic test may further comprise the steps:
Step 2 adds the relevant constraint of debug command in command template;
Step 3 is improved instruction grade stochastic test generation engine, and the adding access instruction is judged, programmable counter is randomly drawed, write down the access address, access data writes down, the jump instruction record, adds corresponding output signal simultaneously;
Step 4, the execution mechanism of adding debug command SDBBP/DRET adds debugging control register (DCR) simultaneously in instruction-level simulator, and entering in system provides correct result when the EJTAG debugging is interrupted;
Step 5 adds signal input, output and Compare Logic in simulated environment;
Step 6, the debugging exception handler prestores in the storer that simulated environment provides;
Describe each step of method shown in the corresponding diagram 2 in detail below in conjunction with Fig. 3:
In step 1, comprise aspect two in instruction database 31, adding the EJTAG debug command:
The order code form of DRET is:
In step 2, comprise two kinds in command template 32, adding the relevant constraint of debug command:
In step 3, test the improvement that produces engine 33 for instruction grade stochastic and comprise following aspect:
Step 330 is added the access instruction decision logic;
Step 331 is by the identifying operation code labeling and write down all load/store access instructions;
Step 332 is further preserved the access address record and the access data record of all load/store instructions;
Step 333 is added the branch transition instruction and is judged;
Step 334 is by the identifying operation code labeling and write down branch transition instruction;
Step 335 is randomly drawed program counter value and record in addition from program counter stack;
In step 4, be divided into following process:
Step 340 is for the execution mechanism that adds debug command SDBBP/DRET in instruction-level simulator 34; Add debugging control register (DCR) simultaneously, entering in system provides correct result when the EJTAG debugging is interrupted; When adding the execution mechanism of debug command SDBBP/DRET, at first add the debug command inlet, can indicate inlet by standard operation sign indicating number or inner custom coding;
In step 5, for add signal input, output and Compare Logic in simulated environment 35, detailed process is as follows:
Step 352 is added output signal in the simulated environment, have four kinds, and the one, debug command error signal, the 2nd, PC debugging exception error signal, the 3rd, address debugging exception error signal, the 4th, debug data exception error signal.
In step 6, for the debugging exception handler that prestores in the storer that provides in simulated environment, the storer that provides in simulated environment can be ROM (read-only memory) (Read-only Memory is called for short ROM), it also can be random access memory (Random Access Memory is called for short RAM); Present embodiment adopts ROM; The debugging exception handler that prestores can adopt hand-written or produce at random, but the return address need be according to the branch transition command prompt signal of input in the step 5 and the Different Results combination processing respectively of Compare Logic, referring to table 2.
Table 2
Utilize method provided by the invention to carry out the process of embedded type CPU checking below in conjunction with Fig. 4 and Fig. 2 explanation:
Step 41 at first reads and resolves command template;
The step 42 decision instruction length whether constrained parameters in the and instruction masterplate is complementary; If then finish whole verification process, execution in step 48; If not, execution in step 43;
Step 441 is by the identifying operation code labeling and write down the instruction of all branch transition, execution in step 442;
Step 444 is finished the PC value and is randomly drawed and record; Carry out two operation independent processes then, respectively execution in step 46 and step 47;
Step 46, the instruction that produces the engine generation is admitted to instruction-level simulator;
Step 460 judges whether the break-poing instruction into EJTAG; If, execution in step 461; Execution in step 462 if not;
Step 461 is revised corresponding C R, DCR according to concrete debugging breakpoint type, and the exception cue is set simultaneously, and execution in step 472 then;
Step 462 is directly revised GR, FR, other CR and internal memory, and execution in step 472 then;
Step 472 waits for that synchronously the simulator result sends into simulated environment, is used for the compare operation of subsequent step;
Step 473 judges whether to have taken place debugging breakpoint exception in simulated environment; If, execution in step 474; If not, execution in step 475;
Whether step 475, standard of comparison instruction operation result and instruction level simulator simulation result unanimity? if then link order is chosen process, execution in step 42; If not, execution in step 477;
Step 476 is sent and is debugged the warning that makes mistakes that makes an exception, execution in step 49;
Step 477 is sent the stereotyped command warning that makes mistakes; Execution in step 49;
From the above, advantage of the present invention is by add EJTAG debug command and related constraint in instruction database and command template, produce a small amount of Compare Logic of interpolation and recording operation in engine and the simulated environment in the instruction grade stochastic test, overcome existing instruction grade stochastic measuring technology and on sheet, intersected the deficiency of debugger field tests, effectively supported the EJTAG test.
Need to prove that the step that relates to if not otherwise specified, just is meant according to sequential write and carries out herein downwards.
It should be noted that at last: above embodiment is the unrestricted technical scheme of the present invention in order to explanation only, although the present invention is had been described in detail with reference to the foregoing description, those of ordinary skill in the art is to be understood that: still can make amendment or be equal to replacement the present invention, and not breaking away from any modification or partial replacement of the spirit and scope of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (3)
1. an implementation method of supporting to strengthen the JTAG test in the instruction grade stochastic test comprises the steps:
Step 1), read and resolve command template;
Step 2), decision instruction length whether with described command template in constrained parameters be complementary; If then execution in step 15), finish whole verification process, if not, execution in step 3);
Step 3), from instruction database, choose instruction according to the various constraints that define in the described command template;
Step 4), stochastic instruction produce engine and produce instruction;
Step 5), according to produce the instruction type, following processing is carried out in instruction:
Step 5-1), judge whether the instruction produced is the branch transition instruction, if, then carry out next step, otherwise, execution in step 5-3);
Step 5-2), by the identifying operation code labeling and write down the instruction of all branch transition, carry out next step then;
Step 5-3), judge whether the instruction produced is the load/store access instruction, if, then carry out next step, otherwise, direct execution in step 5-5);
Step 5-4), according to described load/store access instruction and access address thereof, after record and access data write down, carry out next step;
Step 5-5), finish randomly drawing and record of program counter value;
Instruction-level simulator and simulated environment are sent in step 6), the instruction that will classify after handling respectively, distinguish execution in step 7 then) and step 8);
Step 7), in described instruction-level simulator, judge whether to be breakpoint, if, then revise control corresponding register and debugging control register, the exception cue is set simultaneously according to concrete debugging breakpoint type, if not, then revise general-purpose register, flating point register and internal memory; Last execution in step 9);
Step 8), in described simulated environment, the instruction of sending into is loaded in the microprocessor to be measured moves, described operation result is kept in register and the internal memory, then the result who is preserved is outputed in the described simulated environment by signal wire;
Step 9), the execution result of the resulting instruction-level simulator of step 7) is sent into simulated environment, be used for comparing with the resulting instruction execution result of step 8);
Step 10), in simulated environment, judge whether to have taken place debugging breakpoint exception; If carry out next step; If not, execution in step 12);
Step 11), relatively whether debugging exception operation result consistent with described instruction-level simulator simulation result, if, execution in step next step; If not, execution in step 13);
Whether step 12), standard of comparison instruction operation result be consistent with described instruction-level simulator simulation result, if then execution in step 2), if not, execution in step 14);
Step 13), send the warning that makes mistakes of debugging exception, abnormal end proof procedure;
Step 14), send the stereotyped command warning that makes mistakes, abnormal end proof procedure;
Step 15), simulated program fair termination.
2. the implementation method of in the instruction grade stochastic test, supporting to strengthen the JTAG test according to claim 1, it is characterized in that, in described step 3), the various constraints that define in the described command template comprise the constraint relevant with debug command, the described constraint relevant with debug command comprises: one is that each bar SDBBP instruction must have a DRET instruction to be complementary with it, and another is new parameter to be set be used to adjust the ratio that the debugging exception takes place.
3. the implementation method of in the instruction grade stochastic test, supporting to strengthen the JTAG test according to claim 1, it is characterized in that, in described step 4), programmable counter, branch transition command prompt signal, debugging exception count signal that stochastic instruction produces programmable counter useful signal that engine produces random extraction, load/store command prompt signal, the address of randomly drawing that is complementary with the load/store instruction, the data of randomly drawing that are complementary with the load/store instruction, is complementary with the load/store instruction.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8312331B2 (en) * | 2009-04-16 | 2012-11-13 | Freescale Semiconductor, Inc. | Memory testing with snoop capabilities in a data processing system |
| CN101551749B (en) * | 2009-05-11 | 2012-08-22 | 中国科学院计算技术研究所 | Method and system of random test program generation and design verification method |
| CN101840368B (en) * | 2010-03-26 | 2013-01-16 | 中国科学院计算技术研究所 | JTAG (Joint Test Action Group) real-time on-chip debug method and system of multicore processor |
| US9880818B2 (en) * | 2014-11-05 | 2018-01-30 | Ab Initio Technology Llc | Application testing |
| US10936289B2 (en) | 2016-06-03 | 2021-03-02 | Ab Initio Technology Llc | Format-specific data processing operations |
| CN107665169B (en) * | 2016-07-29 | 2020-07-28 | 龙芯中科技术有限公司 | Method and device for testing processor program |
| CN106776186B (en) * | 2016-12-29 | 2020-04-07 | 湖南国科微电子股份有限公司 | Method and system for debugging CPU running state under multi-CPU architecture |
| US10572259B2 (en) * | 2018-01-22 | 2020-02-25 | Arm Limited | Hints in a data processing apparatus |
| CN108829399B (en) * | 2018-04-13 | 2022-05-20 | 杭州朗和科技有限公司 | Application testing method, testing device, medium and computing equipment |
| CN112069015B (en) * | 2020-11-10 | 2021-02-23 | 鹏城实验室 | Instruction execution method and device for instruction simulator, terminal equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6347368B1 (en) * | 1997-12-30 | 2002-02-12 | Jerry David Harthcock | Microcomputing device for exchanging data while executing an application |
| US6484273B1 (en) * | 2000-11-29 | 2002-11-19 | Lsi Logic Corporation | Integrated EJTAG external bus interface |
| CN1546136A (en) * | 2003-12-09 | 2004-11-17 | 北京正大绿洲医药科技有限公司 | Baras camphor, chuanxiong rhizome headache treating medicine and its oral preparation and its preparing process |
| CN1204499C (en) * | 2000-07-26 | 2005-06-01 | 国际商业机器公司 | Processor for executing hard ware testing during normal executing instruction |
-
2005
- 2005-09-20 CN CNB2005100864457A patent/CN100405323C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6347368B1 (en) * | 1997-12-30 | 2002-02-12 | Jerry David Harthcock | Microcomputing device for exchanging data while executing an application |
| CN1204499C (en) * | 2000-07-26 | 2005-06-01 | 国际商业机器公司 | Processor for executing hard ware testing during normal executing instruction |
| US6484273B1 (en) * | 2000-11-29 | 2002-11-19 | Lsi Logic Corporation | Integrated EJTAG external bus interface |
| CN1546136A (en) * | 2003-12-09 | 2004-11-17 | 北京正大绿洲医药科技有限公司 | Baras camphor, chuanxiong rhizome headache treating medicine and its oral preparation and its preparing process |
Non-Patent Citations (1)
| Title |
|---|
| JTAG技术的发展和应用综述. 胡学良，张春，王志华.微电子学，第35卷第6期. 2005 * |
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Application publication date: 20070328 Assignee: Longxin Zhongke Technology Co., Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract record no.: 2015990000066 Denomination of invention: Method for realizing supporting of EJTAG detection in instruction grade random detection Granted publication date: 20080723 License type: Common License Record date: 20150211 |
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Effective date of registration: 20200824 Address after: 100095, Beijing, Zhongguancun Haidian District environmental science and technology demonstration park, Liuzhou Industrial Park, No. 2 building Patentee after: LOONGSON TECHNOLOGY Corp.,Ltd. Address before: 100080 Haidian District, Zhongguancun Academy of Sciences, South Road, No. 6, No. Patentee before: Institute of Computing Technology, Chinese Academy of Sciences |
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Assignee: LOONGSON TECHNOLOGY Corp.,Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract record no.: 2015990000066 Date of cancellation: 20200928 |
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Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |