CN109375606A - A kind of algorithm library test method - Google Patents
A kind of algorithm library test method Download PDFInfo
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- CN109375606A CN109375606A CN201811108870.5A CN201811108870A CN109375606A CN 109375606 A CN109375606 A CN 109375606A CN 201811108870 A CN201811108870 A CN 201811108870A CN 109375606 A CN109375606 A CN 109375606A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
- G05B23/0221—Preprocessing measurements, e.g. data collection rate adjustment; Standardization of measurements; Time series or signal analysis, e.g. frequency analysis or wavelets; Trustworthiness of measurements; Indexes therefor; Measurements using easily measured parameters to estimate parameters difficult to measure; Virtual sensor creation; De-noising; Sensor fusion; Unconventional preprocessing inherently present in specific fault detection methods like PCA-based methods
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Abstract
The present invention relates to a kind of algorithm library test method, method includes choosing according to engineering project application and applying logic；According to the logical algorithm using logic display, the polyalgorithm block in algorithms library is synchronized and is tested；Whether the application logic operation result of the output signal and input signal that judge system under test (SUT) is consistent, unanimously then determines that the logical algorithm operation of the algorithms library is correct.The present invention is directed to practical engineering project application, algorithms library is used using the synchronous test for carrying out polyalgorithm block of logic function, overcoming existing test method cannot be guaranteed to run correct functional defect when polyalgorithm block uses in series and parallel, while improve the accuracy and reliability of test.
Description
Technical field
The present invention relates to I&C system testing field more particularly to a kind of algorithm library test methods.
Background technique
It is the data handling requirements for realizing each process procedure in instrument control design in I&C system, can develops and meet design requirement
Logical algorithm block, realize and the acquisition conversion of data, operation and data exported, algorithms library is the production for including all algorithmic blocks
Product.To guarantee the logical correctness and accuracy of algorithms library, and meet the practical engineering application of I&C system, is surveyed delivering factory
Before trying (FT), need to carry out detailed plateform system test to the basic function of algorithmic blocks all in product algorithms library.
Algorithmic block has function various in usual I&C system platform, and logic is complicated, the feature that quantity is about 300.At present
It is mostly in the industry Black-box Testing for the test of platform algorithmic block function, such as the test of algorithmic block function traversal and algorithmic block emulation are surveyed
Examination, all tests for single algorithmic block, which can guarantee the correctness of single algorithmic block, but exist it cannot be guaranteed that more
A algorithmic block runs correct functional defect when using in series and parallel.
Summary of the invention
In view of above-mentioned analysis, the present invention is intended to provide a kind of algorithm library test method, solves current test method not
It can guarantee and run correct functional defect when polyalgorithm block uses in series and parallel, improve the accuracy and reliability of test.
The purpose of the present invention is mainly achieved through the following technical solutions:
The embodiment of the invention provides a kind of algorithm library test methods, method includes the following steps: according to engineering project
Using logic is applied in selection；According to the logical algorithm using logic display, to the same stepping of polyalgorithm block in algorithms library
Row test；Whether the application logic operation result of the output signal and input signal that judge system under test (SUT) is consistent, unanimously then determines
The logical algorithm operation of the algorithms library is correct.
In another embodiment based on the above method, the system under test (SUT) includes the algorithms library, and respectively with institute
State the input module and output module of algorithms library connection.The input module acquires the signal generated by test instrumentation, by testing
The signal of the output of output module described in instrument to collect；Wherein, the test instrumentation includes logical by input with the input module
The signal of road connection injects instrument, and the signal acquisition instrument connecting with the output module by output channel.The algorithm
Library includes string and/or the polyalgorithm block that mode in parallel connects.The logical algorithm using logic display is described tested
The typical case logical algorithm of an algorithmic block in system.The typical case logical algorithm is chosen according to the test case of execution
The signal quantity of the input module acquisition.The signal quantity of the acquisition is the corresponding amount of the test case using logic
Journey value range.During the system under test (SUT) implementation of test cases, the corresponding algorithmic block of the application logic is verified, is verified simultaneously
Relevant polyalgorithm block.Described in verifying completion of the algorithms library by the corresponding typical case logical algorithm of polyalgorithm block
The test of algorithms library.Further, terminal is connect with each algorithmic block in the algorithms library, monitors the logical algorithm fortune of each algorithmic block
Calculate the result of result and algorithms library output.
Above-mentioned technical proposal has the beneficial effect that: the embodiment of the invention discloses a kind of algorithm library test method, according to
Engineering project application is chosen and applies logic, according to the logical algorithm using logic display, to the polyalgorithm in algorithms library
Block, which synchronizes, to be tested, and whether the application logic operation result of the output signal and input signal that judge system under test (SUT) is consistent, and one
Cause the logical algorithm operation for then determining the algorithms library correct.The embodiment of the present invention is directed to practical engineering project application, to algorithm
Library is used using the synchronous test for carrying out polyalgorithm block of logic function, and overcoming existing test method cannot be guaranteed polyalgorithm
Correct functional defect is run when block uses in series and parallel, not only increases the accuracy and reliability of test, is also supervised by algorithm
Output depending on terminal and measuring instrumentss carries out intuitive monitoring and checks, so that test process apparentization and result identification are high.
Other features and advantages of the present invention will illustrate in the following description, also, partial become from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by written explanation
Specifically noted structure is achieved and obtained in book, claims and attached drawing.
Detailed description of the invention
Attached drawing is only used for showing the purpose of specific embodiment, and is not to be construed as limiting the invention, in entire attached drawing
In, identical reference symbol indicates identical component.
Fig. 1 is a kind of flow chart of algorithm library test method provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram that a kind of algorithm library test method provided in an embodiment of the present invention is implemented；
Fig. 3 is a kind of typical case logical algorithm schematic diagram of algorithmic block provided in an embodiment of the present invention；
Fig. 4 is a kind of typical case local logic functional diagram of algorithmic block provided in an embodiment of the present invention.
Specific embodiment
Specifically describing the preferred embodiment of the present invention with reference to the accompanying drawing, wherein attached drawing constitutes the application a part, and
Together with embodiments of the present invention for illustrating the principle of the present invention, it is not intended to limit the scope of the present invention.
The test of I&C system platform algorithmic block function is mostly Black-box Testing in the industry at present, and is all single algorithmic block
Test, the test method can guarantee the correctness of single algorithmic block, but various for algorithmic block function in I&C system platform,
Logic is complicated, a fairly large number of feature, exists and runs correct functional defect when it cannot be guaranteed that polyalgorithm block using in series and parallel.
For this defect problem, the invention proposes a kind of algorithm library test methods.
Embodiment of the invention discloses a kind of algorithm library test methods to choose according to engineering project application and apply logic,
According to the logical algorithm using logic display, the polyalgorithm block in algorithms library is synchronized and is tested, judges tested system
Whether the output signal of system and the application logic operation result of input signal are consistent, unanimously then determine that the logic of the algorithms library is calculated
Method operation is correct.Thus directed towards practical engineering project application, algorithms library is used and carries out polyalgorithm using logic function is synchronous
The test of block, overcoming current test method cannot be guaranteed to run correct functional defect when polyalgorithm block uses in series and parallel,
The accuracy and reliability of test are improved simultaneously
Fig. 1 is a kind of flow chart of algorithm library test method of the embodiment of the present invention, as shown in Figure 1, the calculation of the present embodiment
Method library test method includes the following steps:
S101 chooses according to engineering project application and applies logic；
S102 synchronizes the polyalgorithm block in algorithms library and surveys according to the logical algorithm using logic display
Examination；
Whether the application snoop logic result of S103, the output signal and input signal that judge system under test (SUT) are consistent, unanimously
Then determine that the logical algorithm operation of the algorithms library is correct.
The algorithm library test method of the embodiment of the present invention is chosen according to engineering project application and applies logic, answered according to described
With the logical algorithm of logic display, the polyalgorithm block in algorithms library is synchronized and is tested, judges the output letter of system under test (SUT)
It is number whether consistent with the application logic operation result of input signal, unanimously then determining the logical algorithm operation of the algorithms library just
Really.Compared with existing test method, such as the test of algorithmic block function traversal and algorithmic block emulation testing, it overcomes it cannot be guaranteed that more
The functional defect that a algorithmic block uses in series and parallel.
Here make as described below to the existing test method of citing: the traversal test of algorithmic block function is in algorithms library
Whole algorithmic blocks successively carry out simple function test, and operation includes the configuration work of logic function in plateform system test environment
Journey calls the operation of respective logic algorithm according to input variable using excitation is manually entered, to obtain the operation values of output variable,
And the method being compared with desired value is tested.Algorithm simulating test is that model buildings are carried out in simulated environment, by true
Each cycle algorithm output valve is recognized compared with the result progress in real time that reference model exports, the correctness of decision algorithm operation.
Fig. 2 is the structural schematic diagram that a kind of algorithm library test method of the embodiment of the present invention is implemented.
One embodiment of the present of invention participates in Fig. 2, and the system under test (SUT) 200 includes the algorithms library 201, and respectively
The input module 202 and output module 203 being connect with the algorithms library 201.The system under test (SUT) 200 is to carry out product algorithms library
Test method implements the core of structure, and when building test environment, 200 hardware environment of system under test (SUT) needs and engineering
The almost the same test environment of site of deployment, or meet the test environment of basic demand, that is to say, that testing environment needs includes
Cabinet, rack, board and module etc., wherein module includes input module 202, output module 203 and algorithms library 201.
One embodiment of the present of invention, as shown in Fig. 2, the input module 202 acquires the signal generated by test instrumentation,
The signal that the output module 203 exports is acquired by test instrumentation；Wherein, the test instrumentation includes and the input module
202 inject instrument by the signal that input channel connects, and are adopted with the output module 203 by the signal that output channel is connect
Integrates instrument.
It should be noted that the signal that test instrumentation is divided into system under test (SUT) input terminal injects instrument 204 and system under test (SUT) is defeated
The signal acquisition instrument 205 of outlet, it is usually tester that signal, which injects instrument 204, and signal acquisition instrument 205 is usually to verify
Instrument or oscillograph.The demand that system under test (SUT) input module acquires signal is met by the use of test instrumentation, and to output
The requirement of module output signal monitoring, thus to determine whether the test result of system under test (SUT) correctly provides foundation.
One embodiment of the present of invention, the algorithms library include string and/or the polyalgorithm block that mode in parallel connects.This
The test method of embodiment is the test when polyalgorithm block uses in series and parallel to the synchronous progress polyalgorithm block of algorithms library, because
This algorithms library includes polyalgorithm block, and all algorithmic blocks are connected in a manner of various strings and/or parallel connection.
Fig. 3 is a kind of typical case logical algorithm schematic diagram of algorithmic block provided in an embodiment of the present invention.
One embodiment of the present of invention, the logical algorithm using logic display are an algorithm in the system under test (SUT)
The typical case logical algorithm of block.
The test method process of the typical case logical algorithm of one specific algorithmic block, is illustrated in conjunction with Fig. 3.According to
Engineering project application is chosen and typically applies logic.Referring to Fig. 3, the selection of typical case logic, such as algorithmic block PT100 exist
Typical case in nuclear power I&C system is overtemperature degree computing function, therefore can be answered using its relevant logical algorithm as typical case
With carrying out test verifying to PT100 algorithmic block.The collectable thermal resistance value range of PT100 is injected in the input terminal of system under test (SUT),
It is observed during logical operation by algorithm monitoring computer and being exported by the operation of each algorithmic block, it is each during observation logical operation
Whether the output of algorithmic block and the output result of algorithms library are correct, shown in Figure 2 to be used for what the system under test (SUT) 200 was connect
The terminal 206 of algorithm monitoring.The input terminal and output end of system under test (SUT) are connected to using test instrumentation simultaneously, sends input signal
With display output signal, reference frame is provided for the judgement of test result, that is, by checking that the output signal of system under test (SUT) is
It is no consistent with the application logic operation result of input signal, to judge whether test result is correct.
One embodiment of the present of invention, the typical case logical algorithm choose the input according to the test case of execution
The signal quantity of module acquisition.That is, typical case logical algorithm realizes logic by the execution of specific test case
The operation of algorithm, and the input magnitude of logical algorithm is chosen to obtain by the signal for acquiring the input module.
Another embodiment of the invention, the signal quantity of the acquisition are described corresponding using the test case of logic
Range ability value.That is, the selection range of the signal quantity of input module acquisition, the i.e. choosing of the input magnitude of logical algorithm
Range is taken, for the corresponding range ability value of test case specifically executed.
The concrete use case in plateform system test is illustrated below, i.e., LLAG first-order lead hysteresis algorithm block becomes
Work is verified in rear system testing, as shown in figure 4, a kind of typical case local logic functional diagram of algorithmic block.According to the algorithm
The typical case situation of block selects △ T PROTECTION LOOP3 function to verify algorithms library, △ T PROTECTION
The local logic functional diagram of LOOP3 function is as shown in Figure 4.According to functional diagram, △ T PROTECTION LOOP3 test can be covered
The practical situations of LLAG algorithmic block, implementation of test cases, the input of LLAG algorithmic block be HZRCP060MT2 and
HZRCP057MT2, input range include input channel can it is collected effectively and invalid range ability, test case input and pre-
The notional result of phase see the table below.
What needs to be explained here is that cold junction temperature and hot-side temperature test scope include in effective range ability and effective quantity
The outer situation of journey range tests all possible input condition by permutation and combination, to ensure that test scope is comprehensive and result has
Effect.The input path of signal and outgoing route require to be consistent with scene actual use situation, and signal is by conditioning board, i.e.,
It is conveyed to analog signals analog input card (A/D conversion) after signal is distributed and is isolated, is completed by signal processing unit related
After logical operation, eventually by digital output card (D/A conversion), the signal of operation result is exported...
By test instrumentation, i.e. process checking gauge, in the defeated of signal HZRCP060MT2 and HZRCP057MT2 corresponding channel
Enter the thermal resistance signal of end injection use-case requirement, the monitoring screen of the operation result of the logical algorithm configuration of each algorithmic block in terminal
In check, by the consistency checking of notional result expected from the signal and test case that are exported to system under test (SUT), to know
Whether the function of LLAG algorithmic block is realized.
Further, in a specific embodiment, it during the system under test (SUT) implementation of test cases, is answered described in verifying
With the corresponding algorithmic block of logic, while verifying relevant polyalgorithm block.In conjunction with Fig. 4, it can be seen that the part of the typical case
Relevant polyalgorithm block and LLAG algorithmic block string and/or in parallel in logi function chart, it can thus be appreciated that specific implementation of test cases
During, it is not only the verifying using the corresponding algorithmic block of logic to selection, while being also to relevant polyalgorithm block
Verifying.The present embodiment, which overcomes current test method, cannot be guaranteed to run correct function when polyalgorithm block uses in series and parallel
Defect.
In another specific embodiment, the algorithms library passes through the corresponding typical case logical algorithm of polyalgorithm block
The test of the algorithms library is completed in verifying.That is, the test process of algorithms library, by multiple typical case logical algorithms
Verifying complete, i.e., logical operation is carried out to polyalgorithm block corresponding in algorithms library, thus improve the accuracy of test with
Reliability.
One embodiment of the present of invention, terminal are connect with each algorithmic block in the algorithms library, monitor the logic of each algorithmic block
Algorithm operation result and the result of algorithms library output.Referring to fig. 2, in the terminal and the algorithms library for algorithm monitoring
Each algorithmic block connection, can check logical algorithm configuration from terminal, that is, operation result and the algorithms library output of each algorithmic block are answered
With logical algorithm as a result, so that test process apparentization and operation result identification are high.The system under test (SUT) is logical simultaneously
The signal for crossing output channel output is shown that the output signal should be with the result phase one of algorithms library output by signal acquisition instrument
It causes.
In conclusion, according to engineering project application, choosing application the invention discloses a kind of algorithm library test method and patrolling
Volume, according to the logical algorithm using logic display, the polyalgorithm block in algorithms library is synchronized and is tested, judgement is tested
Whether the output signal of system and the application logic operation result of input signal are consistent, unanimously then determine the logic of the algorithms library
Algorithm operation is correct.The embodiment of the present invention is directed to practical engineering project application, uses to algorithms library and applies the same stepping of logic function
The test of row polyalgorithm block, overcoming existing test method cannot be guaranteed to run correctly when polyalgorithm block uses in series and parallel
Functional defect.Embodiment based on the above method, the system under test (SUT) include the algorithms library, and respectively with the algorithms library
The input module and output module of connection.The input module acquires the signal generated by test instrumentation, is acquired by test instrumentation
The signal of the output module output；Wherein, the test instrumentation includes being connect with the input module by input channel
Signal injects instrument, and the signal acquisition instrument connecting with the output module by output channel.The algorithms library includes string
And/or the polyalgorithm block that mode in parallel connects.The logical algorithm using logic display is one in the system under test (SUT)
The typical case logical algorithm of a algorithmic block.The typical case logical algorithm chooses the input according to the test case of execution
The signal quantity of module acquisition.The signal quantity of the acquisition is the corresponding range ability of the test case using logic
Value.During the system under test (SUT) implementation of test cases, the corresponding algorithmic block of the application logic is verified, while verifying relevant
Polyalgorithm block.The algorithms library completes the algorithms library by the verifying of the corresponding typical case logical algorithm of polyalgorithm block
Test.Terminal is connect with each algorithmic block in the algorithms library, monitors the logical algorithm operation result of each algorithmic block and described
The result of algorithms library output.The accuracy and reliability of test are not only increased through this embodiment, are also monitored eventually by algorithm
The output of the signal of end and measuring instrumentss carries out intuitive monitoring and checks, so that test process apparentization and result identification are high.This
Invention is applied in nuclear safe level digitlization instrument control platform harmony system testing, is calculated for verifying platform in harmonious I&C system
System testing after Faku County's change.
It will be understood by those skilled in the art that realizing all or part of the process of method in above-described embodiment, can pass through
Computer program is completed to instruct relevant hardware, and the program can be stored in computer readable storage medium.Wherein,
The computer readable storage medium is disk, CD, read-only memory or random access memory etc..
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.
Claims (10)
1. a kind of algorithm library test method, which comprises the following steps:
According to engineering project application, chooses and apply logic；
According to the logical algorithm using logic display, the polyalgorithm block in algorithms library is synchronized and is tested；
Whether the application logic operation result of the output signal and input signal that judge system under test (SUT) consistent, unanimously then determine described in
The logical algorithm operation of algorithms library is correct.
2. the method according to claim 1, wherein the system under test (SUT) includes the algorithms library, and respectively
The input module and output module being connect with the algorithms library.
3. according to the method described in claim 2, it is characterized in that, the input module acquires the letter generated by test instrumentation
Number, the signal of the output module output is acquired by test instrumentation；
Wherein, the test instrumentation includes that the signal connecting with the input module by input channel injects instrument, and with institute
State the signal acquisition instrument that output module is connected by output channel.
4. method according to claim 1 or 2, which is characterized in that the algorithms library includes that string and/or mode in parallel connect
The polyalgorithm block connect.
5. the method according to claim 1, wherein the logical algorithm using logic display is described tested
The typical case logical algorithm of an algorithmic block in system.
6. according to the method described in claim 5, it is characterized in that, the typical case logical algorithm is used according to the test of execution
Example chooses the signal quantity of the input module acquisition.
7. according to the method described in claim 6, it is characterized in that, the signal quantity of the acquisition is the survey using logic
The corresponding range ability value of example on probation.
8. according to the method described in claim 6, it is characterized in that, being verified during the system under test (SUT) implementation of test cases
The corresponding algorithmic block of the application logic, while verifying relevant polyalgorithm block.
9. method according to claim 1 or 5, which is characterized in that the algorithms library passes through the corresponding allusion quotation of polyalgorithm block
The test of the algorithms library is completed in the verifying of type application logical algorithm.
10. system according to claim 1, it is further characterized in that, each algorithmic block connects in terminal and the algorithms library
It connects, monitors the logical algorithm operation result of each algorithmic block and the result of algorithms library output.
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