CN103996416A

CN103996416A - Reusable FTL (Flash Translation Layer) verification method

Info

Publication number: CN103996416A
Application number: CN201410226573.6A
Authority: CN
Inventors: 杨萌; 李风志; 姚香君; 戴绍新
Original assignee: Shandong Sinochip Semiconductors Co Ltd
Current assignee: Shandong Sinochip Semiconductors Co Ltd
Priority date: 2014-05-27
Filing date: 2014-05-27
Publication date: 2014-08-20
Anticipated expiration: 2034-05-27
Also published as: CN103996416B

Abstract

The invention discloses a reusable FTL (Flash Translation Layer) verification method. The FTL verification method comprises the following steps: establishing a verification platform of a bus structure, which is used for constructing a flash memory controller model with a USB (Universal Serial Bus) model; injecting excitation into the verification platform, wherein the excitation comprises two parts, namely one part corresponding to firmware of a flash memory controller, and an FTL sequence; calling a compiler of a CPU (Central Processing Unit) to compile the firmware to generate a target program, and injecting into an internal memory; and injecting the FTL sequence by the USB model and simulating USB equipment by the FTL sequence selected randomly to carry out verification, wherein the random selection of the FTL sequence is based on the random selection of SV (System Verilog). According to the method, the debugging efficiency of FTL verification can be improved.

Description

A kind of reusable FTL verification method

Technical field

The present invention relates to a kind of method for FTL (Flash Translation Layer, flash translation layer (FTL)) checking.

Background technology

Flash memory (Flash Memory, full name is flash memory) read-write unit for page, and the size of page is generally 4KB or 8KB, but it is by HDD(Hard Disk Drive that operating system reads and writes data, hard disk drive) sector size (as the 512Byte(byte) of carrying out), more trouble is that flash memory is wiped with piece office, and just do not wipe and cannot write, this file system that causes operating system to use now cannot be managed SSD(Solid State Disk at all, solid state hard disc), need to change more advanced, complicated file system goes to address this problem, but will increase the weight of like this burden of operating system.

And in order not increase the weight of the burden of operating system, SSD adopts the mode of software the operation of flash memory to be invented to the independent sector operation of disk, Here it is FTL.Because FTL is present between file system and physical medium (flash memory), operating system only need operate LBA(Logical Block Address as before, logical block addresses, be called for short logical address), and LBA is to PBA(Physics Block Address, physical blocks address, is called for short physical address) all conversion work, just entirely transfer to FTL to be responsible for.

Known according to aforesaid content, FTL is between NAND(Sheffer stroke gate) conversion layer between flash chip (being the movement chip of solid state hard disc) and basic document system (as FAT32), it makes operating system can as access hard disk, access nand flash memory equipment with file system.

FTL Algorithm constitution firmware and being configured in as on flash controller is the algorithm that the FTL sequence of FTL layer output is processed.Good FTL algorithm, in ensureing read or write speed, by writing and erasing times of the monitoring page, allows writing of each page keep in balance with erasing times, can significantly increase the life-span of nand flash memory chip.Thereby FTL, except arriving the mapping of PBA for LBA, also will take into account garbage reclamation, many-sided content such as wear leveling.

At the conventional digital SoC(System on Chip based on FTL, SOC (system on a chip)) in performance history, the debugging cycle of FTL firmware will be far above hardware, it is invisible that reason is exactly firmware debugging, cannot carry out wrong precise positioning by the waveform of similar hardware design, add FTL algorithm itself, will process as previously mentioned the work such as address mapping, garbage reclamation and wear leveling, complicacy is higher, and debugging efficiency is very low.

Summary of the invention

Therefore, the object of the present invention is to provide a kind of reusable FTL verification method, to improve the debugging efficiency of FTL checking.

The present invention is by the following technical solutions:

A kind of reusable FTL verification method, comprises

Build bus-structured verification platform, in order to build the flash controller model with USB model;

The excitation of injecting described verification platform comprises two parts, the firmware of a part of corresponding flash controller, and another part is FTL sequence;

Wherein, the compiler that calls CPU compiles firmware, produces target program, and injects internal memory;

FTL sequence is injected by USB model, verify at random by FTL sequence is carried out, and the random fashion of the random employing of FTL sequence based on SV obtains in order to simulate USB device; SV is System Verilog.

Above-mentioned reusable FTL verification method, the acquisition of FTL sequence also comprises the input by firmware personnel for the problem of finding in selected or test.

Above-mentioned reusable FTL verification method, described FTL sequence is deposited in the mode of file, and when checking, USB model read FTL sequential file obtains FTL sequence.

Above-mentioned reusable FTL verification method, described USB model is the USB model based on SV.

Above-mentioned reusable FTL verification method, the interface of USB model and RTL is realized in program (program), thereby in program, is divided into different time domains; Wherein RTL is register-transfer level, i.e. Method at Register Transfer Level.

Above-mentioned reusable FTL verification method, carries out emulation at front end to RTL, carries out firmware with it.

According to the present invention, FTL sequence random, the random fashion based on SV obtains, and can change scope, data package size and the reading and writing data direction of sequence address, thereby have better dirigibility by constraint, convenient debugging, thus improve debugging efficiency.

Brief description of the drawings

Fig. 1 is a kind of Organization Chart of verification platform.

Embodiment

With reference to figure 1, for the corresponding verification platform framework of this verification method, by CPU, RAM, USB, Flash, AHB_Arbiter, the module composition bus apparatus such as DMA, hang over bus AHB(Advanced High performance Bus), entirety forms bus structure, corresponding to flash controller, forms the model of flash controller.

The external drive of verification platform is divided into two parts, firmware (firmware) and FTL sequence.Wherein firmware is deposited with file mode, form firmware file, in order to deposit firmware, before emulation starts, configuration script reads firmware from this firmware file, the compiler that calls CPU compiles firmware, and the target program that compiling produces also injects RAM(internal memory) in the middle of, running environment is described out.FTL sequential file provides the FTL sequence of its transmission to USB model (USB model).

USB model is used for simulating USB, sends the read-write of FTL sequence and simulated data.

Before emulation starts, script calls compiler, and firmware is compiled, and changes into the file layout that CPU can carry out, i.e. the executable target program of CPU.

FTL sequence for emulation has two kinds: the first, and by firmware, personnel provide, and for running specific emulation, for the FTL sequence of pinpointing the problems, locate rapidly the position of bug; The second, obtains by random producing method, and this mode is for carrying out a large amount of random tests.

Wherein, for some empirical tested objects, can join FTL sequence, for some new problems of finding, can directly be provided by firmware personnel.

In addition, for some less objects of weight in FTL sequence, relatively little by the probability directly arriving at random when random, also can directly be provided by firmware personnel.

The random fashion of the random employing of FTL sequence based on SV (System Verilog) obtains, and can change sequence address scope by constraint, data package size, and reading and writing data direction, thereby there is better dirigibility.

In addition, for constraint, can open to tester, carry out artificial amendment or correction, to meet current test needs.

About SV, be a kind of concept combining from Verilog, VHDL, C++, also have verification platform language and assertion language, that is to say, it combines hardware description language (HDL) and modern higher level lanquage (C++).Make its checking slip-stick artist for the design verification of carrying out current high complexity there is sizable attractive force.

These all make System Verilog on a higher abstraction hierarchy, improve the ability of design setting model.It is mainly positioned in the realization and checking flow process of chip.System Verilog has chip design and the required entire infrastructure of checking slip-stick artist, the characteristics such as object based programming, dynamic thread and inter-thread communication that it is integrated, as a kind of industrial standard language, SV Comprehensive RTL design, test platform, assert and coverage rate, for system-level design and checking provide powerful supporting function.

SystemVerilog is for RTL(Method at Register Transfer Level), full blast the exploitation of abstract model and advanced verification platform, because it has possessed the architecture of carrying out this respect required by task, for example restricted arbitrary excitation generation, functional coverage or assert.

About RTL, in RTL level, IC is made up of the logical operation between one group of register and register.Why like this, because most circuit can be seen as by register to carry out stores binary data, completed the processing of data by the logical operation between register, the flow process of data processing is controlled by sequential state machine, and these processing and control can be described with hardware description language.

The simple difference of RTL level and gate leve is, RTL describes you with hardware description language (Verilog or VHDL) to want the function reaching, gate leve is to realize your function by concrete logical block (relying on the storehouse of producer), gate leve finally can be processed into actual hardware at semiconductor factory, in short, RTL and gate leve are the different phases on design realizes, and RTL, after logic synthesis, just obtains gate leve.

It is to be expressed as a finite state machine that RTL describes, or a more generally sequential state machine that can carry out register transfer on a predetermined clock period border, and tri-kinds of language of VHDL/verilog/SV are described conventionally.

RTL circuit structure is simple, and element is few.

FTL sequence obtains by reading FTL sequential file; Data obtain by random.

USB model uses SV to write and forms, class-based characteristic makes it have very high reusability, realize in program (program) with the interface of RTL, program, by dividing different time domains (timing region), can effectively avoid disorderly (race) problem.And this USB model has cast aside the state machine flow process of USB inside, there is the feature of simple high speed compared with traditional model.

For dividing the region of time domain, in this region, emulator can be distinguished different time domains to of providing for synopsys of program, for the treatment of the sequential of RTL and TB, avoids race problem

Emulation adopts nc-sim to carry out, and emulation starts rear wave file can open by instruments such as verdi under emulation catalogue, and the emulation of FTL algorithm is debugged.

In sum, the method for inventing herein, can carry out FTL algorithm simulating for specific FTL sequence or random FTL sequence, and debugging waveform is provided.Compare traditional FTL adjustment method, there is location of mistake accurate, debug efficient feature.In firmware debug process, use this method, can greatly improve the debugging efficiency of FTL algorithm, reduce the needed each side resource consumption of debugging.

Claims

1. a reusable FTL verification method, is characterized in that, comprises

2. reusable FTL verification method according to claim 1, is characterized in that, the acquisition of FTL sequence also comprises the input by firmware personnel for the problem of finding in selected or test.

3. reusable FTL verification method according to claim 1 and 2, is characterized in that, described FTL sequence is deposited in the mode of file, and when checking, USB model read FTL sequential file obtains FTL sequence.

4. reusable FTL verification method according to claim 1 and 2, is characterized in that, described USB model is the USB model based on SV.

5. reusable FTL verification method according to claim 4, is characterized in that, the interface of USB model and RTL is realized in program, thereby in program, is divided into different time domains; Wherein RTL is register-transfer level, i.e. Method at Register Transfer Level.

6. reusable FTL verification method according to claim 5, is characterized in that, at front end, RTL is carried out to emulation, carries out firmware with it.