CN109783954B - IES (information engineering System) combined FPGA (field programmable Gate array) hardware simulation acceleration system - Google Patents

IES (information engineering System) combined FPGA (field programmable Gate array) hardware simulation acceleration system Download PDF

Info

Publication number
CN109783954B
CN109783954B CN201910060694.0A CN201910060694A CN109783954B CN 109783954 B CN109783954 B CN 109783954B CN 201910060694 A CN201910060694 A CN 201910060694A CN 109783954 B CN109783954 B CN 109783954B
Authority
CN
China
Prior art keywords
fpga
clock
simulation
hardware
tested
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910060694.0A
Other languages
Chinese (zh)
Other versions
CN109783954A (en
Inventor
孙宇明
江云松
高猛
于志杰
田甜
童宗挺
朱倩
赵欢
赵鹏
李铀
尤静
姚春月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Sunwise Information Technology Ltd
Original Assignee
Beijing Sunwise Information Technology Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Sunwise Information Technology Ltd filed Critical Beijing Sunwise Information Technology Ltd
Priority to CN201910060694.0A priority Critical patent/CN109783954B/en
Publication of CN109783954A publication Critical patent/CN109783954A/en
Application granted granted Critical
Publication of CN109783954B publication Critical patent/CN109783954B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

The invention provides an IES (electronic engineering System) combined FPGA (field programmable gate array) hardware simulation acceleration system which comprises an IES simulation module, a software and hardware communication module and an FPGA hardware acceleration module. The IES simulation module circularly extracts parallel excitation data designed by the tested FPGA in a preset time period according to a preset simulation clock frequency and sends the parallel excitation data to the FPGA hardware acceleration module; circularly extracting test data of the tested FPGA design from the FPGA hardware acceleration module, converting the test data into a tested FPGA design simulation result according to a corresponding time sequence, and displaying the simulation result; the FPGA hardware acceleration module receives the parallel excitation data and stores the parallel excitation data into the input buffer; generating a test excitation clock and working clocks of each clock domain of the tested FPGA design, and driving an input buffer zone to output parallel excitation data to the tested FPGA design; under the action of the parallel excitation data, the tested FPGA designs and outputs test data to an output buffer zone. The invention reduces the operation burden of the simulation environment and improves the speed of FPGA simulation.

Description

IES (information engineering System) combined FPGA (field programmable Gate array) hardware simulation acceleration system
Technical Field
The invention relates to an FPGA simulation acceleration system, in particular to a method for completing simulation acceleration of FPGA design by combining programmable logic simulation software and FPGA hardware, belonging to the technical field of FPGA simulation test.
Background
Simulation verification is a necessary step of design test of FPGA software, and is one of effective means for guaranteeing the quality of the FPGA software. The scale and design complexity of the use of programmable gate array (FPGA) devices has increased. Conventional FPGA simulation software such as IES, modelsim and the like has long debugging and running time of a simulation environment, and cannot completely meet increasingly tense model development tasks. Therefore, it is necessary to study the simulation verification acceleration technique for FPGA code to meet the application requirements.
At present, the realization of simulation hardware acceleration has two approaches, namely an acceleration method based on an FPGA and a method based on a special acceleration calculation structure. The method based on the special acceleration computing structure needs to design a special computing structure, has high research, development and experiment costs, has corresponding products applied to professional integrated circuit verification, but has high price and weak expandability, and is often applied to the research and development of very large scale integrated circuits with sufficient fund amount. The acceleration method based on the FPGA is characterized by flexible and reconfigurable FPGA design, low research and development and experiment cost and strong expandability, and is suitable for the research and development of small-scale professional integrated circuits or the verification of FPGA design.
International business machines corporation patent CN201380017736.3 discloses a cycle accurate and cycle reproducible memory for FPGA-based hardware accelerators, including methods of operating with FPGAs to simulate devices under test. In one example, the invention creates a cycle accurate model of memory by separating a memory interface protocol of a design under test from a target memory storage array. However, the method has too high requirements on hardware design, requires additional memory on hardware besides the FPGA, is influenced by the size of the memory, and has poor adaptability to simulation software.
The design of a software and hardware collaborative simulation platform based on an FPGA discloses a software and hardware system method based on the FPGA, which comprises the following steps: and (3) performing communication by using a network port and opening data by using a graphical interface. However, the processing method disclosed in the comparison document is limited to a single clock domain, and the application scene only comprises verification of a single algorithm.
In summary, the prior art has the following problems:
(1) The hardware structure is complex, special requirements are met for the acceleration board card, and reusability is low;
(2) The simulation verification software and the hardware communication mechanism are not perfect in establishment, the operation of the tested design cannot be controlled in real time, and the simulation acceleration application scene is limited;
(3) The method has no clear control requirement on the hardware operation rate, is unfavorable for FPGA layout and wiring operation, and is easy to cause the situation that the time sequence cannot be converged.
Disclosure of Invention
The technical solution of the invention is as follows: the system overcomes the defects of the prior art, and the IES is combined with the FPGA hardware simulation acceleration system, uses a simple and general hardware environment, completes the simulation acceleration of the FPGA design and improves the verification efficiency of the FPGA design.
The technical scheme of the invention is as follows: an IES combined FPGA hardware simulation acceleration system comprises an IES simulation module, a software and hardware communication module and an FPGA hardware acceleration module; the software and hardware communication module is used for realizing communication interaction between the IES simulation environment and the FPGA hardware acceleration module; wherein:
the IES simulation module circularly extracts parallel excitation data designed by the tested FPGA in a preset time period according to a preset simulation clock frequency and sends the parallel excitation data to the FPGA hardware acceleration module; circularly extracting test data of the tested FPGA design from the FPGA hardware acceleration module, converting the test data into a tested FPGA design simulation result according to a corresponding time sequence, and displaying the simulation result in an IES simulation environment;
the FPGA hardware acceleration module receives the parallel excitation data and stores the parallel excitation data into the input buffer; generating a clock tree, wherein the clock tree comprises a test excitation clock and working clocks of all clock domains of the tested FPGA design, and the test excitation clock is used for driving an input buffer to output parallel excitation data to the tested FPGA design; each clock domain working clock of the tested FPGA design is connected to the tested FPGA design and used for replacing each clock domain working clock signal in the tested FPGA design; under the action of the parallel excitation data, the tested FPGA designs and outputs test data to an output buffer zone.
The IES simulation module includes a simulation environment, a simulation environment interface module, wherein:
the simulation environment is used for compiling an excitation file of the FPGA to be tested according to the simulation clock frequency to generate an excitation signal; simultaneously displaying the excitation data and the test data;
the simulation environment interface module converts the excitation signal into excitation data according to the simulation clock frequency in a preset time period, caches the excitation data, sends the excitation data to the FPGA hardware acceleration module through the software and hardware communication module, receives test data sent by the software and hardware communication module, and forwards the test data to the simulation environment according to time sequence.
The FPGA hardware acceleration module comprises an input FIFO, control logic, a clock tree generation module, an output FIFO and an output cache RAM, wherein:
the input FIFO is used for storing the excitation data and outputting the excitation data to the FPGA design to be tested under the drive of the test excitation clock; the excitation data at the same moment are stored in the same storage unit;
the control logic receives a data moving instruction sent by the hardware interface and moves a certain amount of test data in the output FIFO to the output buffer RAM; receiving a gating clock starting instruction sent by a hardware interface, and generating an effective gating clock to a clock tree generating module;
the clock tree generation module is used for generating a clock tree, outputting a test excitation clock and working clocks of each clock domain of the tested FPGA design under the enabling control of the gating clock, wherein the test excitation clock is used for driving the input buffer area to output parallel excitation data to the tested FPGA design; the working clocks of each clock domain of the tested FPGA design are connected to the tested FPGA design and used for replacing the working clock signals of each clock domain in the tested FPGA design;
the output FIFO is used for storing the test data output by the tested FPGA design and outputting the parallel test data to the tested FPGA design under the drive of the test excitation clock; test data at the same moment are stored in the same storage unit;
and the output buffer RAM is used for storing test data output by the design of the tested FPGA and is read by a hardware interface.
The output data bus of the input FIFO is connected to the ports designed by the FPGA to be tested, and bits of excitation data correspond to the ports designed by the FPGA to be tested one by one.
When the least common multiple of the design working clock of the tested FPGA and the frequency of the simulation clock are in an integer multiple relation, the clock tree generating module is used for enabling the working frequency of the design working clock to be equivalent to the frequency of the simulation clock, and the working clock of the design working clock of the tested FPGA is used as a test excitation clock to be output to the input FIFO; and the working frequency is equivalent to the least common multiple frequency of the working clocks of each clock domain designed according to the tested FPGA, and then the working clocks of each clock domain designed by the tested FPGA are respectively generated according to the corresponding frequency division proportion.
The FPGA to be tested designs the duty ratio of working clocks of each clock domain to be 1/N, wherein N is the frequency division ratio.
When the least common multiple of the design working clock of the tested FPGA and the frequency of the simulation clock are in a non-integer multiple relation, the clock tree generating module is used for enabling the working frequency of the clock tree generating module to be equivalent to the frequency of the simulation clock, and the working clock is used as a test excitation clock to be output to an input FIFO; and taking the working clock as a reference clock of the DDS, taking the simulation clock frequency as a reference clock frequency value of the DSS, calculating a corresponding frequency control word, and respectively generating working clocks of all clock domains of the tested FPGA design.
The software and hardware communication module comprises a hardware interface driving module and a hardware interface; wherein:
the hardware interface driving module is used for providing a hardware interface driving program, sending the excitation data generated by the IES simulation module to the hardware interface and acquiring test data from the hardware interface;
the hardware interface is used for sending the excitation data to the FPGA hardware acceleration module; and reading test data from the FPGA hardware acceleration module and sending the test data to the hardware interface driving module.
The hardware interface is a PCI bus interface.
The hardware module is realized by a PCI golden finger and a PCI bus interface IP core which are connected to the FPGA general IO.
The hardware interface driving module adopts C language programming, the simulation environment adopts IES verification platform, and adopts System Verilog programming; according to the corresponding bit sequence, mapping the bit sequence to an instantiation port of an excitation file of the FPGA to be tested, calling a C language function in a hardware interface driving module through a DPI interface of a System Verilog and a C language, sending excitation data to an FPGA hardware acceleration module, and reading test data acquired by the hardware interface driving module.
And the hardware interface reads the test data from the FPGA hardware acceleration module in a DMA mode.
Compared with the prior art, the invention has the beneficial effects that:
(1) According to the method, the excitation signals are converted into discrete excitation data and loaded into the FPGA to provide a test data source for the FPGA design, the test verification is completed in the FPGA hardware, and then the test data is read out and displayed, so that the advantage of the FPGA hardware is fully utilized, the operation burden of a simulation environment is reduced, and the speed of FPGA simulation is improved;
(2) The invention provides a clock tree concept, and when the least common multiple of the working clock of the design of the tested FPGA and the frequency of the simulation clock are in an integer multiple relation, the working frequency is equivalent to the least common multiple frequency of the working clock of each clock domain of the design of the tested FPGA, and then the working clocks of each clock domain of the design of the tested FPGA are respectively generated according to the corresponding frequency division ratio, so that the simulation time can be accurately controlled, and the effect of coordinated and consistent operation of the whole design is achieved.
(3) The excitation data at the same moment are stored in the same storage unit of the input FIFO, the output data bus of the input FIFO is connected to the port designed by the FPGA to be tested, and the bit positions of the excitation data are in one-to-one correspondence with the port designed by the FPGA to be tested, so that the excitation data are ensured to be injected into the FPGA design rapidly and accurately.
(4) The hardware interface of the invention adopts a DMA mode to read the test data from the FPGA hardware interface, and the reading speed is high.
Drawings
FIG. 1 is a block diagram of an IES-combined FPGA hardware simulation acceleration system according to an embodiment of the invention.
Detailed Description
The invention will be described in detail below with reference to the drawings and the specific embodiments.
The FPGA is used as a programmable logic device, and can correctly realize all logic operations. All simulations of logic designs are essentially simulations of logic operations, with natural advantages in converting to FPGAs. Meanwhile, because the writing requirements of the verification environment are relatively loose, the number of the non-synthesizable sentences is large, and the method is suitable for running in a computer. According to the invention, the FPGA design simulation acceleration task is completed by adopting a software-hardware combination mode according to the sequence processing of all digital devices.
As shown in FIG. 1, the invention provides an IES combined FPGA hardware simulation acceleration system, which comprises an IES simulation module, a software and hardware communication module and an FPGA hardware acceleration module; the software and hardware communication module is used for realizing communication interaction between the IES simulation environment and the FPGA hardware acceleration module; wherein:
the IES simulation module circularly extracts parallel excitation data designed by the tested FPGA in a preset time period according to a preset simulation clock frequency and sends the parallel excitation data to the FPGA hardware acceleration module; circularly extracting test data of the tested FPGA design from the FPGA hardware acceleration module, converting the test data into a tested FPGA design simulation result according to a corresponding time sequence, and displaying the simulation result in an IES simulation environment;
the FPGA hardware acceleration module receives the parallel excitation data and stores the parallel excitation data into the input buffer; generating a clock tree, wherein the clock tree comprises a test excitation clock and working clocks of all clock domains of the tested FPGA design, and the test excitation clock is used for driving an input buffer to output parallel excitation data to the tested FPGA design; each clock domain working clock of the tested FPGA design is connected to the tested FPGA design and used for replacing each clock domain working clock signal in the tested FPGA design; under the action of the parallel excitation data, the tested FPGA designs and outputs test data to an output buffer zone.
(1) IES simulation module
The IES simulation module includes a simulation environment, a simulation environment interface module, wherein:
the simulation environment is used for compiling an excitation file of the FPGA to be tested according to the simulation clock frequency to generate an excitation signal; simultaneously displaying the excitation data and the test data;
the simulation environment interface module converts the excitation signal into excitation data according to the simulation clock frequency in a preset time period, caches the excitation data, sends the excitation data to the FPGA hardware acceleration module through the software and hardware communication module, receives test data sent by the software and hardware communication module, and forwards the test data to the simulation environment according to time sequence.
(2) Software and hardware communication module
The software and hardware communication module comprises a hardware interface driving module and a hardware interface. Wherein:
the hardware interface driving module is used for providing a hardware interface driving program, sending the excitation data generated by the IES simulation module to the hardware interface and acquiring test data from the hardware interface; the module adopts C language programming, the simulation environment uses IES to verify the platform, adopt System Verilog programming; according to the corresponding BIT sequence, mapping the BIT sequence to an instantiation port of an excitation file of the FPGA to be tested, calling a C language function in a hardware interface driving module through a DPI interface of a System Verilog and a C language, sending excitation data to an FPGA hardware acceleration module, and reading test data acquired by the hardware interface driving module.
The hardware interface is used for sending the excitation data to the FPGA hardware acceleration module; and reading test data from the FPGA hardware acceleration module and sending the test data to the hardware interface driving module. The hardware interface may be selected as a PCI bus interface. The hardware module is realized through a PCI golden finger connected to the FPGA general IO and a PCI bus interface IP core, and the PCI bus interface IP core reads test data from the FPGA hardware acceleration module in a DMA mode.
(3) FPGA hardware acceleration module
The FPGA hardware acceleration module comprises an input FIFO, control logic, a clock tree generation module, an output FIFO and an output buffer RAM, wherein:
the input FIFO is used for storing the excitation data and outputting the excitation data to the FPGA design to be tested under the drive of the test excitation clock; the excitation data at the same moment are stored in the same storage unit; the output data bus of the input FIFO is connected to the ports designed by the FPGA to be tested, and bits of excitation data correspond to the ports designed by the FPGA to be tested one by one.
The control logic receives a data moving instruction sent by the hardware interface and moves a certain amount of test data in the output FIFO to the output buffer RAM; receiving a gating clock starting instruction sent by a hardware interface, and generating an effective gating clock to a clock tree generating module;
the clock tree generation module is used for generating a clock tree, outputting a test excitation clock and working clocks of each clock domain of the tested FPGA design under the enabling control of the gating clock, wherein the test excitation clock is used for driving the input buffer area to output parallel excitation data to the tested FPGA design; the working clocks of each clock domain of the tested FPGA design are connected to the tested FPGA design and used for replacing the working clock signals of each clock domain in the tested FPGA design.
The generation of the clock tree is divided into two cases:
when the least common multiple of the design working clock of the tested FPGA and the frequency of the simulation clock are in an integer multiple relation, the clock tree generating module is used for enabling the working frequency of the design working clock to be equivalent to the frequency of the simulation clock, and the working clock of the design working clock of the tested FPGA is used as a test excitation clock to be output to the input FIFO; and the working frequency is equivalent to the least common multiple frequency of the working clocks of each clock domain designed according to the tested FPGA, and then the working clocks of each clock domain designed by the tested FPGA are respectively generated according to the corresponding frequency division proportion. The FPGA to be tested designs the duty ratio of working clocks of each clock domain to be 1/N, wherein N is the frequency division ratio.
When the least common multiple of the design working clock of the tested FPGA and the frequency of the simulation clock are in a non-integer multiple relation, the clock tree generating module is used for enabling the working frequency of the clock tree generating module to be equivalent to the frequency of the simulation clock, and the working clock is used as a test excitation clock to be output to an input FIFO; and taking the working clock as a reference clock of the DDS, taking the simulation clock frequency as a reference clock frequency value of the DSS, calculating a corresponding frequency control word, and respectively generating working clocks of all clock domains of the tested FPGA design.
The output FIFO is used for storing the test data output by the tested FPGA design and outputting the parallel test data to the tested FPGA design under the drive of the test excitation clock; test data at the same moment are stored in the same storage unit;
and the output buffer RAM is used for storing test data output by the design of the tested FPGA and is read by a hardware interface.
Examples:
as shown in FIG. 1, a specific embodiment of the present invention is divided into three parts, namely an IES simulation module, a software and hardware communication module and an FPGA hardware acceleration module. The IES simulation module writes excitation data into the FPGA hardware acceleration module through the software and hardware communication module based on the simulation environment of SystemVerilog; the FPGA hardware acceleration module processes the FPGA design, and the simulation environment obtains a test result and completes the simulation of one frame of data. And (3) cyclically reciprocating, wherein the excitation data rate input to the tested design corresponds to the least common multiple rate of the carding clock tree, and the data rate output to the simulation environment also corresponds to the least common multiple rate. By the scheme, the simulation time can be accurately controlled, and waveform display can be realized by directly using simulation software.
The following modules are specifically described:
the first part, the FPGA hardware acceleration module is divided into three parts: control logic, read-write buffer memory and read-write interface. The read-write buffer takes the form of FIFO + dual port RAM. And the read-write interface adopts a DMA mode of PCIE 3.0. The method comprises the following steps:
the control logic is responsible for receiving data externally written to the PCIE. The upper computer determines the current communication state through the read-write M_AXI_LITE port, when the trigger logic receives externally input data and the trigger logic reads output data, the gate control clock is controlled to be started, the tested FPGA design is driven to work according to clock beats, and the tested design output result of the corresponding clock beats is output to the output interface FIFO. The premise that the design under test is able to be gated with clock control logic is that there is no clock frequency generation module inside. In order to solve the problem, a method for modifying the clock domain of the tested design is particularly proposed. The basic principle of the method is that all frequency generation in the FPGA is integer multiplication and division relative to a certain frequency, so that a frequency which is integer times of the clock frequency of a clock source is necessarily present, and clocks generated by all frequency generation modules can be generated in a frequency dividing mode. Therefore, a frequency division clock file can be independently generated to replace sum source clock signals generated by all frequency generation modules in the signals, and the operation of other clocks can be controlled as long as whether the master clock is generated or not is controlled, so that the aim that an upper computer can control the operation of a tested design is achieved. When the output buffer FIFO in the FPGA is full, the m_axi_lite port data is 32'h5555aaaa, otherwise, the m_axi_lite port data is 32' haaaaa 5555 for use as a data output handshake signal. When the write data to the M_AXI_LITE port is 32' h55 aaaa, the FPGA resets the internal move ram.
FIFO use and not limited to XILINX IP core use, wherein the output FIFO is set to a depth of 16384 and a width of 256 for outputting signals to the design under test; an input FIFO, set to a depth of 16384 and a width of 128, is used to input signals to the design under test. The dual-port RAM is used for caching data output by the tested design, and is carried from fifo to the dual-port RAM to wait for PCIE interface reading.
The PCIE interface uses and is not limited to XILINX IP core, can realize maximum rate 5GT/s, and has a communication width of 256 bits. AXI Address Width is set to 64, lane Width is X8, the maximum link rate is 5GT/s, AXI Data Width is set to 256, AXI clock frequency is set to 125MHz, and the reference clock is 100MHz. Vendor ID 16'h10EE,Device ID 16'h7028,Revision ID 16'h00,Subsystem Vendor ID 16'h10EE,Subsystem ID 16' h0007.
The second part, the software and hardware communication module is mainly used for completing the communication between the upper computer simulation software and the internal data of the FPGA, and is divided into a Linux system driving layer and a read-write data logic part.
The Linux system driving layer adopts a DMA driving mode, and a driver interface is called through a C language interface in a library function mode, so that an operating system can communicate through a PCIE3.0 bus. The PCI initializer must search all PCI buses in the Linux system to locate all PCI devices in the system, including the PCI-PCI bridge. The PCI initialization program determines, via the PCI BIOS program, whether each slot in the PCI bus currently being searched is occupied. The PCI initialization program begins scanning from PCI bus 0, which first attempts to read the vendor identifier and device identifier of the PCI device that may be present in each PCI slot. If a read to a slot is successful, indicating that the PCI slot is already occupied, the PCI device driver will create a data structure pci_dev describing the device and insert it into the linked list of all PCI devices already present. The PCI initializer creates a pci_bus structure if the device is found to be a PCI-PCI bridge, and then inserts it into the pcibus structure tree. The PCI initialization program determines whether the device is a PCI-PCI bridge by class code 0x 060400. If the PCI bridge is the PCI-PCI bridge, the system kernel sets the PCI bus downstream of the PCI-PCI bridge. If the PCI-PCI bridge is found again therein, the PCI bus downstream of the PCI-PCI bridge is continued to be set. Only knowing that the PCI-PCI bridge can deliver PCI i/O, PCI memory or PCI setup address: master bus number, slave bus number, subordinate bus number (the largest bus number of all buses downstream of the PCI-PCI bridge), PCI i/O, and PCI memory window (the window start and size of PCI i/O and PCI memory address space of the downstream address of the PCI-PCI bridge). The Linux system kernel searches each bus number using a depth search algorithm. Whenever a PCI-PCI bridge is found and its secondary bus number is assigned, a temporary subordinate number-0 xFF is assigned to the PCI-PCI bridge at the same time, and then the bus numbers of all PCI-PCI bridges downstream of the PCI-PCI bridge are searched and assigned.
The read-write data logic links PCIE data by opening the device name, and performs read-write operation on the device through read-write functions. The write function writes input stimulus data to the FPGA, the data size being 128 x 16384 bits. The read function first checks if the m_axi_LITE port data is 32' h5555aaaa, if so, performs a 256 x 16384bit read operation on the interface, and resets the data cache ram and the move logic by writing 32' h5555aaaa before writing 32' haaaabbbb after the read operation. The data flow from the simulation environment to the FPGA hardware acceleration module is to buffer and pack serial data with time sequence characteristics into data blocks, buffer data with 128 multiplied by 16384 bits, buffer the data according to time sequence, and analyze the data into input tested design excitation arranged according to time sequence in the FPGA for the tested design operation, wherein the data is sampled values with 128 bits corresponding to 16384 time points of an input port. Similarly, the data flow from the FPGA hardware acceleration module to the simulation environment is to buffer and pack serial data with time sequence characteristics into data blocks, buffer data with 256 multiplied by 16384 bits, buffer the data according to time sequence, and analyze the data in the simulation environment into input tested design excitation arranged according to time sequence for observation and analysis.
And the third part, the IES simulation module establishment module mainly completes simulation environment transformation. The simulation environment uses an IES verification platform, is built in a simulation System of the System Verilog, and calls a C language function through a DPI interface of the System Verilog and the C language, so that data interaction between the software simulation environment and the hardware FPGA is realized. The input port corresponds to the writing function, and the expected monitoring signal corresponds to the reading function, so that the purpose of monitoring the reading and writing port is achieved.
The software and hardware communication module accesses the PCIE interface through a Linux drive. And the FPGA hardware acceleration module starts the clock control signal of the tested design and the receiving and sending FIFO according to the written handshake signal. The FPGA stores the simulation excitation data into an input FIFO, and simultaneously returns and outputs an output result of the simulation excitation after the simulation excitation enters the tested design to the simulation environment.
Besides the design, the embodiment of the invention also designs auxiliary reconstruction design application software, so that the engineering improvement efficiency is improved, and the auxiliary reconstruction design application software comprises clock tree generation software and port automatic correspondence software.
The basic principle of clock tree generation software development is that all integer multiple frequency division clocks can be generated by distributing a source clock, and the difference is that the duty ratio of data cannot be guaranteed to be 1:1. the system operating rate is limited by the operating rate of the simulation software, and the clock frequency of the whole drive tested design is low, so that the frequency division clock can be generated when the duty ratio is ignored. The duty cycle may be designed to be 1/N, where N is the division factor. Thus, it is possible to set the other periods to be low by setting the first period of all counts to be high. The software is written to realize the function, and the clock tree frequency division file is automatically generated according to the frequency division parameters and the clock number to replace the original clock tree.
The basic principle of port automatic correspondence function development is that the design and the instantiation of the FPGA and the port name link can be extracted through an automatic extraction input-output list, so that the complexity of modification of the simulation environment is reduced. The port automatic correspondence software needs two data sources, namely an instantiation file and an input/output port name file for the FPGA design. The software reads the instantiation file and the port name file, and generates two files, namely a tested design instantiation file and a simulation port corresponding file. The tested design instantiation file is used for adding the design engineering file, the simulation port corresponding file is used for adding the design engineering file into the simulation environment, and automatic port correspondence is realized.
The method comprises the following specific implementation steps:
1. clock tree with clear design
For the homologous clocks, the least common multiple of the highest clock frequency required by design is obtained, the least common multiple is assumed to be used as a master clock for frequency division, and all clocks are replaced by clock modules generated by the self; for asynchronous clocks, the clocks generated by the asynchronous clocks are generated by using a direct frequency synthesis (DDS) mode according to the proportion of the homologous clocks. Wherein the generation of homologous clock applets using the highest frequency is implemented by clock tree generation software. And inputting the highest working frequency at the clock frequency, writing the frequency division number into the frequency division clock number, adding the frequency division coefficient of the corresponding number into the frequency division coefficient, and finally automatically generating codes. And adding the generated clock file into the tested design to replace the homologous clock generated by the internal DCM.
2. Adaptive modification of a design under test to an accelerated device environment
And correcting the IP cores, nucleating all the IPs into a netlist, taking a design code and the IPs core netlist as engineering inputs, and importing the design code and the IPs core netlist into a design VC709 design environment. And (3) rewriting hardware resources corresponding to ports such as all differential devices, delay devices and the like in the design into direct assignment or synthesizable codes.
3. Generating design call files
Taking ISE design engineering as an example: the ISE is used to open the design project, changing the project properties to be trending towards verilog. Clicking on the view HDL instantiation template generates a. Tfi file. Net gen-dir jiasasuka-sim engineering name ngc-ofmt verilog engineering name v is added in the command line to generate a netlist. The input/output port is copied to a new blank v file. Port auto-correspondence software reads the. Tfi and. V files, generating portcon. Sv and ini design under test. V. The portcon.sv is added into the environment, the ini tested design.v is added into the design project, the ini tested design.v is stored in the project folder, and the automatic transformation of the simulation environment and the tested design is realized.
4. After engineering modification, clicking to generate a bit file, running the program, and debugging, modifying and running the program when errors occur in the middle of running. And downloading the program after generating the Bit file.
5. And (3) loading a simulation environment:
first, the linux driver is installed in the administrator mode. And secondly, adding a data exchange module to the simulation environment to replace the original design program. And finally, directly executing the use case on the simulation environment, and noticing that the input frequency of the excitation corresponds to the least common multiple clock.
The parts of the specification not described in detail are common general knowledge to a person skilled in the art.

Claims (10)

1. The IES combined FPGA hardware simulation acceleration system is characterized by comprising an IES simulation module, a software and hardware communication module and an FPGA hardware acceleration module; the software and hardware communication module is used for realizing communication interaction between the IES simulation environment and the FPGA hardware acceleration module; wherein:
the IES simulation module circularly extracts parallel excitation data designed by the tested FPGA in a preset time period according to a preset simulation clock frequency and sends the parallel excitation data to the FPGA hardware acceleration module; circularly extracting test data of the tested FPGA design from the FPGA hardware acceleration module, converting the test data into a tested FPGA design simulation result according to a corresponding time sequence, and displaying the simulation result in an IES simulation environment;
the FPGA hardware acceleration module receives the parallel excitation data and stores the parallel excitation data into the input buffer; generating a clock tree, wherein the clock tree comprises a test excitation clock and working clocks of all clock domains of the tested FPGA design, and the test excitation clock is used for driving an input buffer to output parallel excitation data to the tested FPGA design; each clock domain working clock of the tested FPGA design is connected to the tested FPGA design and used for replacing each clock domain working clock signal in the tested FPGA design; under the action of the parallel excitation data, the tested FPGA designs and outputs test data to an output buffer zone;
the FPGA hardware acceleration module comprises an input FIFO, control logic, a clock tree generation module, an output FIFO and an output cache RAM, wherein:
the input FIFO is used for storing the excitation data and outputting the excitation data to the FPGA design to be tested under the drive of the test excitation clock; the excitation data at the same moment are stored in the same storage unit;
the control logic receives a data moving instruction sent by the hardware interface and moves a certain amount of test data in the output FIFO to the output buffer RAM; receiving a gating clock starting instruction sent by a hardware interface, and generating an effective gating clock to a clock tree generating module;
the clock tree generation module is used for generating a clock tree, outputting a test excitation clock and working clocks of each clock domain of the tested FPGA design under the enabling control of the gating clock, wherein the test excitation clock is used for driving the input buffer area to output parallel excitation data to the tested FPGA design; the working clocks of each clock domain of the tested FPGA design are connected to the tested FPGA design and used for replacing the working clock signals of each clock domain in the tested FPGA design;
the output FIFO is used for storing the test data output by the tested FPGA design and outputting the parallel test data to the tested FPGA design under the drive of the test excitation clock; test data at the same moment are stored in the same storage unit; the output data bus of the input FIFO is connected to the ports designed by the FPGA to be tested, and bits of excitation data correspond to the ports designed by the FPGA to be tested one by one;
and the output buffer RAM is used for storing test data output by the design of the tested FPGA and is read by a hardware interface.
2. The IES-associated FPGA hardware simulation acceleration system of claim 1, wherein the IES simulation module comprises a simulation environment, a simulation environment interface module, wherein:
the simulation environment is used for compiling an excitation file of the FPGA to be tested according to the simulation clock frequency to generate an excitation signal; simultaneously displaying the excitation data and the test data;
the simulation environment interface module converts the excitation signal into excitation data according to the simulation clock frequency in a preset time period, caches the excitation data, sends the excitation data to the FPGA hardware acceleration module through the software and hardware communication module, receives test data sent by the software and hardware communication module, and forwards the test data to the simulation environment according to time sequence.
3. The IES combined FPGA hardware simulation acceleration system of claim 1, wherein when the least common multiple of the design working clock of the tested FPGA is in an integer multiple relation with the simulation clock frequency, the clock tree generation module is used for generating the working frequency of the design working clock of the tested FPGA, the clock tree generation module is used for equivalent the working frequency of the design working clock of the tested FPGA to the simulation clock frequency, and the working clock of the design working clock of the tested FPGA is used as a test excitation clock to be output to the input FIFO; and the working frequency is equivalent to the least common multiple frequency of the working clocks of each clock domain designed according to the tested FPGA, and then the working clocks of each clock domain designed by the tested FPGA are respectively generated according to the corresponding frequency division proportion.
4. The IES-combined FPGA hardware simulation acceleration system of claim 3, wherein the duty cycle of the working clock of each clock domain of the FPGA design under test is 1/N, where N is the frequency division ratio.
5. The IES combined FPGA hardware simulation acceleration system of claim 1, wherein when the least common multiple of the design working clock of the tested FPGA is in a non-integer multiple relation with the simulation clock frequency, the clock tree generation module is used for equivalent the working frequency of the design working clock to the simulation clock frequency, and the working clock is used as a test excitation clock to be output to the input FIFO; and taking the working clock as a reference clock of the DDS, taking the simulation clock frequency as a reference clock frequency value of the DSS, calculating a corresponding frequency control word, and respectively generating working clocks of all clock domains of the tested FPGA design.
6. The IES combined FPGA hardware simulation acceleration system of claim 1, wherein the software and hardware communication module comprises a hardware interface driving module and a hardware interface; wherein:
the hardware interface driving module is used for providing a hardware interface driving program, sending the excitation data generated by the IES simulation module to the hardware interface and acquiring test data from the hardware interface;
the hardware interface is used for sending the excitation data to the FPGA hardware acceleration module; and reading test data from the FPGA hardware acceleration module and sending the test data to the hardware interface driving module.
7. The IES-associated FPGA hardware emulation acceleration system of claim 1, wherein the hardware interface is a PCI bus interface.
8. The IES combined FPGA hardware simulation acceleration system of claim 7, wherein the hardware interface is implemented by a PCI golden finger and a PCI bus interface IP core connected to a general purpose IO of the FPGA.
9. The IES combined FPGA hardware simulation acceleration System of claim 6, wherein the hardware interface driving module adopts C language programming, the simulation environment uses an IES verification platform and adopts System Verilog programming; according to the corresponding bit sequence, mapping the bit sequence to an instantiation port of an excitation file of the FPGA to be tested, calling a C language function in a hardware interface driving module through a DPI interface of a System Verilog and a C language, sending excitation data to an FPGA hardware acceleration module, and reading test data acquired by the hardware interface driving module.
10. The IES-associated FPGA hardware emulation acceleration system of claim 6, wherein the hardware interface reads test data from the FPGA hardware acceleration module using DMA.
CN201910060694.0A 2019-01-23 2019-01-23 IES (information engineering System) combined FPGA (field programmable Gate array) hardware simulation acceleration system Active CN109783954B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910060694.0A CN109783954B (en) 2019-01-23 2019-01-23 IES (information engineering System) combined FPGA (field programmable Gate array) hardware simulation acceleration system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910060694.0A CN109783954B (en) 2019-01-23 2019-01-23 IES (information engineering System) combined FPGA (field programmable Gate array) hardware simulation acceleration system

Publications (2)

Publication Number Publication Date
CN109783954A CN109783954A (en) 2019-05-21
CN109783954B true CN109783954B (en) 2023-08-29

Family

ID=66501189

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910060694.0A Active CN109783954B (en) 2019-01-23 2019-01-23 IES (information engineering System) combined FPGA (field programmable Gate array) hardware simulation acceleration system

Country Status (1)

Country Link
CN (1) CN109783954B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110765711A (en) * 2019-12-06 2020-02-07 国微集团(深圳)有限公司 Method and system for checking simulation signal of digital product
CN111523282A (en) * 2020-05-07 2020-08-11 深圳探科技术有限公司 Method, module, storage medium and system for data processing in integrated circuit simulation
JP2022049470A (en) * 2020-09-16 2022-03-29 キオクシア株式会社 Logic simulation verification system, logic simulation verification method and program
CN112364583B (en) * 2020-11-24 2023-11-17 北京轩宇信息技术有限公司 FPGA software and hardware collaborative simulation system and method
CN112541311A (en) * 2020-12-02 2021-03-23 深圳市金泰克半导体有限公司 Simulation test method, simulation test device, computer equipment and storage medium
CN112861468B (en) * 2021-02-08 2022-12-06 山东云海国创云计算装备产业创新中心有限公司 Software and hardware collaborative simulation verification method, device and medium
CN113051167B (en) * 2021-03-31 2023-12-22 北京经纬恒润科技股份有限公司 Model and model code testing method and device
CN114064547B (en) * 2021-11-15 2023-06-13 北京邮电大学 PCIe-based communication protocol stack hardware acceleration architecture construction method
CN117521583A (en) * 2023-11-17 2024-02-06 中科苏州智能计算技术研究院 Software and hardware joint simulation method and system driven by clock and storage medium
CN117313650B (en) * 2023-11-28 2024-03-01 苏州元脑智能科技有限公司 Chip test verification method and application device thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
基于FPGA的软硬件协同仿真平台的设计;田野;《中国优秀硕士学位论文全文数据库》;20110615;摘要，正文第2-4章 *

Also Published As

Publication number Publication date
CN109783954A (en) 2019-05-21

Similar Documents

Publication Publication Date Title
CN109783954B (en) IES (information engineering System) combined FPGA (field programmable Gate array) hardware simulation acceleration system
EP1489511B1 (en) Hierarchical, Network-Based emulation System
US7085702B1 (en) Method and system for modeling and automatically generating an embedded system from a system-level environment
US7418681B2 (en) Simulation system, simulation method and simulation program for verifying logic behavior of a semiconductor integrated circuit
US7366652B2 (en) Method of programming a co-verification system
Wakabayashi C-based synthesis experiences with a behavior synthesizer,“Cyber”
US8868974B2 (en) Memory-based trigger generation scheme in an emulation environment
US8387005B1 (en) Generation of multi-domain code from a graphical program
US10311193B2 (en) Alteration of a signal value for an FPGA at runtime
US7707019B1 (en) Command buffering for hardware co-simulation
US9929734B2 (en) Method for changing the configuration of a programmable logic module
Koczor et al. Verification approach based on emulation technology
US20050144436A1 (en) Multitasking system level platform for HW/SW co-verification
Sayinta et al. A mixed abstraction level co-simulation case study using systemc for system on chip verification
US10318687B2 (en) Implementing a constant in FPGA code
JP3212709B2 (en) Logic simulation device
Abbes et al. IP integration methodology for SoC design
US11520531B1 (en) Systems and methods for intercycle gap refresh and backpressure management
Ahmed et al. Functional Verification of Dynamic Partial Reconfiguration for Software-Defined Radio
CN115964969A (en) Digital logic simulation acceleration architecture based on fragmentation
JP5729983B2 (en) Information processing apparatus, information processing method, and program
CN112883679A (en) Automatic generation of fueling stations in multi-voltage designs
WO2024049472A2 (en) Communication link latency tolerance for hardware assisted verification systems
Jones et al. autoVHDL: a domain-specific modeling language for the auto-generation of VHDL core wrappers
Esteves et al. EDgAR: A Platform for Hardware/Software Codesign

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant