CN111858218A - FPGA AMBA bus interface debugging method and device and FPGA - Google Patents
FPGA AMBA bus interface debugging method and device and FPGA Download PDFInfo
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Abstract
The application discloses an AMBA bus interface debugging method and device of an FPGA and the FPGA, wherein the method comprises the following steps: acquiring a target debugging command script, wherein the target debugging command script is a TCL script acquired by a Vivado tool; calling JTAG to AXI IP in the Vivado tool to convert the target debugging command script into standard AXI interface data; and calling AXI interconnection IP in the Vivado tool and carrying out debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module so as to debug the target interface module, wherein the target interface module is an interface module corresponding to a target address in the target debugging command script. Therefore, the debugging efficiency can be greatly improved, and the debugging flexibility is improved.
Description
Technical Field
The application relates to the technical field of FPGA, in particular to an AMBA bus interface debugging method and device of FPGA and the FPGA.
Background
In an SOC (System on Chip) type FPGA (Field-Programmable gate array), a CPU (Central Processing Unit), a software System running on the CPU, and various bus and peripheral interface modules are generally provided. In early development, debugging verification is the key for ensuring the design correctness of the FPGA system. A complex SOC type FPGA system is composed of a plurality of modules, a plurality of modules have data interaction with a CPU, and due to the cooperation of hardware and software, debugging is time-consuming and labor-consuming. Therefore, before being co-tuned with software, a hardware engineer or a logic engineer needs to debug and verify the correctness of data transmission of the amba (advanced micro controller Bus architecture), advanced micro controller Bus architecture) Bus interface between each module and the CPU.
The method mainly comprises the steps of firstly, compiling C verification codes, generating binary files which can be identified by a CPU through compiling debugging software, programming the binary files into a flash, reading programs from the flash by the CPU, and interacting with a hardware module interface, so as to debug the AMBA bus interface. And the second scheme is to compile a comprehensive bus model and a test case generation module and simulate the interaction between a CPU and a hardware interface. However, in the first prior art, a logic engineer is required to write software codes, which often affects debugging efficiency for a logic engineer unfamiliar with software or C language. In the second prior art, a logic engineer is required to add additional auxiliary test codes outside the design, and the comprehensive test case generation module is not as flexible as the software test codes.
Disclosure of Invention
In view of this, an object of the present application is to provide an AMBA bus interface debugging method and apparatus for an FPGA, and an FPGA, which can improve the AMBA bus debugging efficiency and have higher flexibility. The specific scheme is as follows:
in a first aspect, the present application discloses an AMBA bus interface debugging method for an FPGA, applied to an SOC-type FPGA, comprising:
acquiring a target debugging command script, wherein the target debugging command script is a TCL script acquired by a Vivado tool;
calling JTAG to AXI IP in the Vivado tool to convert the target debugging command script into standard AXI interface data;
and calling AXI interconnection IP in the Vivado tool and carrying out debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module so as to debug the target interface module, wherein the target interface module is an interface module corresponding to a target address in the target debugging command script.
Optionally, the obtaining the target debug command script includes:
and acquiring the target debugging command script transmitted through the JTAG.
Optionally, the invoking an AXI Interconnect IP in the Vivado tool and performing a debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module, so as to debug the target interface module, includes:
if the target interface is the AHB Slave interface module, calling AXIInterconnect IP and AXI to AHB Lite Bridge IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AHB Slave interface module.
Optionally, the invoking an AXI Interconnect IP in the Vivado tool and performing a debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module, so as to debug the target interface module, includes:
if the target interface target is an AXI Slave interface module, calling an AXIInterconnect IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AXI Slave interface module.
Optionally, the invoking an AXI Interconnect IP in the Vivado tool and performing a debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module, so as to debug the target interface module, includes:
if the target interface target is an AXI Master interface module, calling AXIInterconnect IP, AXI BRAM Controller IP and Bock Memory Generator IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AXI Master interface module.
Optionally, the invoking an AXI Interconnect IP in the Vivado tool and performing a debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module, so as to debug the target interface module, includes:
if the target interface is the AHB Master interface module, calling AXIInterconnect IP, AXI BRAM Controller IP, Bock Memory Generator IP and AHB Liteto AXI Bridge IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AHB Master interface module.
Optionally, the invoking AXI Interconnect IP, AXI BRAMController IP, Bock Memory Generator IP, and AHB Lite to AXI Bridge IP in the Vivado tool to perform a debugging operation corresponding to the standard AXI interface data, so as to debug the AHB Master interface module, includes:
invoking the AXI BRAM Controller IP to establish communication between the AXI Interconnect IP and the BockMemory Generator IP;
calling the Bock Memory Generator IP to simulate the Memory of the FPGA so as to store target data corresponding to the standard AXI interface data;
and calling the AXI BRAM Controller IP and the AHB Lite to AXI Bridge IP to establish communication between the Bock Memory Generator IP and the AHB Master interface module, so that the AHB Master interface module reads the target data and carries out corresponding processing to debug the AHB Master interface module.
In a second aspect, the present application discloses an AMBA bus interface debugging device for an FPGA, which is applied to an SOC-type FPGA, and includes:
the data acquisition module is used for acquiring a target debugging command script, wherein the target debugging command script is a TCL script acquired by a Vivado tool;
the first IP calling module is used for calling JTAG to AXI IP in the Vivado tool to convert the target debugging command script into standard AXI interface data;
and the second IP calling module is used for calling an AXI Interconnect IP in the Vivado tool and carrying out debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module so as to debug the target interface module, wherein the target interface module is an interface module corresponding to a target address in the target debugging command script.
Optionally, the second IP invoking module is configured to:
and when the target interface is an AHB Master interface module, calling AXIInterconnect IP, AXI BRAM Controller IP, Bock Memory Generator IP and AHB Liteto AXI Bridge IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AHB Master interface module.
In a third aspect, the present application discloses an SOC-type FPGA, comprising:
a memory and a processor;
wherein the memory is used for storing a computer program;
the processor is used for executing the computer program to realize the AMBA bus interface debugging method of the FPGA.
Therefore, the method includes the steps of firstly obtaining a target debugging command script, wherein the target debugging command script is a TCL script obtained through a Vivado tool, then calling JTAG to AXI IP in the Vivado tool to convert the target debugging command script into standard AXI interface data, calling AXI INTERCONNECT IP in the Vivado tool and carrying out debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module so as to debug the target interface module, and the target interface module is an interface module corresponding to a target address in the target debugging command script. Therefore, the AMBA bus interface can be debugged by using the TCL command script by using the JTAG to AXI IP in the Vivado tool and matching the AXIInterconnect IP and the IP corresponding to the module to be debugged, so that the conventional mature IP is used, and the test case can be parametrized and generated by using the TCL command script, thereby greatly improving the debugging efficiency and the debugging flexibility.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of an AMBA bus interface debugging method of an FPGA according to the present disclosure;
fig. 2 is a flowchart of a specific method for debugging an AMBA bus interface of an FPGA according to the present disclosure;
FIG. 3 is a block diagram illustrating an AMBA bus interface debugging of an FPGA according to the present disclosure;
fig. 4 is a schematic structural diagram of an AMBA bus interface debugging apparatus of an FPGA according to the present disclosure;
fig. 5 is a schematic structural diagram of an SOC-type FPGA disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, a method for writing a C verification code to debug in AMBA bus interface debugging on an FPGA needs a logic engineer to write a software code, which often affects debugging efficiency for the logic engineer who is not familiar with software or C language. Writing a comprehensive bus model and a test case generation module, simulating a debugging method of interaction between a CPU and a hardware interface, adding an additional auxiliary test code outside the design of a logic engineer, and making the comprehensive test case generation module less flexible than a software test code. In view of this, the present application provides an AMBA bus interface debugging method for an FPGA, which can improve the AMBA bus debugging efficiency and has high flexibility.
Referring to fig. 1, an embodiment of the present application discloses an AMBA bus interface debugging method for an FPGA, which is applied to an SOC-type FPGA, and the method includes:
step S11: and acquiring a target debugging command script, wherein the target debugging command script is a TCL script acquired through a Vivado tool.
In a specific implementation process, a target debug Command script needs to be obtained first, so as to debug a local AMBA bus interface by using the target debug Command script, where the target debug Command script is a TCL (Tool Command Language) script obtained by a Vivado Tool. The Vivado tool is a Xilinx FPGA development tool.
Step S12: and calling JTAG to AXI IP in the Vivado tool to convert the target debugging command script into standard AXI interface data.
After the target debugging command script is obtained, the JTAG toaxI IP in the Vivado tool is also required to be called to convert the target debugging command script into standard AXI interface data. JTAG (Joint Test action group) is an international standard Test protocol, AXI (advanced eXtensible interface) is an advanced eXtensible interface, JTAG to AXI Master IP is a configurable IP (namely an IP core) in a Vivado tool, JTAG transactions can be converted into AXI transactions, AXI 4 and AXI-Lite protocols are supported, the AXI transactions are connected to AXI interface IP as a Master interface, the AXI interface IP is a configurable IP, devices conforming to the AXI transactions are interconnected, the JTAG to AXI IP interface is extended, namely a plurality of lower-level AXI slave devices are connected to a JTAG to AXI Master device through the AXI interface IP.
Step S13: and calling AXI interconnection IP in the Vivado tool and carrying out debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module so as to debug the target interface module, wherein the target interface module is an interface module corresponding to a target address in the target debugging command script.
After the target debugging command script is converted into standard AXI interface data, an AXI Interconnect IP in the Vivado tool needs to be called, and a debugging operation corresponding to the standard AXI interface data is performed according to a preset IP determined by a target interface module, so as to debug the target interface module, wherein the target interface module is an interface module corresponding to a target address in the target debugging command script.
Specifically, the AMBA Bus interface on the FPGA may include an AHB (Advanced High-performance Bus) interface module, an AXI interface module, and an APB (Advanced Peripheral Bus) interface module, so that in addition to invoking the AXI Interconnect IP, a preset IP corresponding to a target interface module in the Vivado tool needs to be invoked, so as to debug the target interface module.
Therefore, the method includes the steps of firstly obtaining a target debugging command script, wherein the target debugging command script is a TCL script obtained through a Vivado tool, then calling JTAG to AXI IP in the Vivado tool to convert the target debugging command script into standard AXI interface data, calling AXI INTERCONNECT IP in the Vivado tool and carrying out debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module so as to debug the target interface module, and the target interface module is an interface module corresponding to a target address in the target debugging command script. Therefore, the AMBA bus interface can be debugged by using the TCL command script by using the JTAG to AXI IP in the Vivado tool and matching the AXIInterconnect IP and the IP corresponding to the module to be debugged, so that the conventional mature IP is used, and the test case can be parametrized and generated by using the TCL command script, thereby greatly improving the debugging efficiency and the debugging flexibility.
Referring to fig. 2, the embodiment of the present application discloses a specific method for debugging an AMBA bus interface of an FPGA, which is applied to an SOC-type FPGA, and the method includes:
step S21: and acquiring the target debugging command script transmitted through the JTAG, wherein the target debugging command script is a TCL script acquired through a Vivado tool.
In practical application, the target debug command script transmitted through JTAG may be obtained, where the target debug command script is a TCL script obtained through a Vivado tool.
Specifically, if the address of the AXI Slave interface module in the AMBA bus interface in the FPGA is 10000000, an AXI burst write transaction of 32-bit data may be created by the following TCL command script:
create_hw_axi_txnwr_txn_lite[get_hw_axis hw_axi_1]-address 10000000–data11223344-type write
run_hw_axiwr_txn_lite
delete_hw_axi_txnwr_txn_lite
step S22: and calling JTAG to AXI IP in the Vivado tool to convert the target debugging command script into standard AXI interface data.
Step S23: and calling AXI interconnection IP in the Vivado tool and carrying out debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module so as to debug the target interface module, wherein the target interface module is an interface module corresponding to a target address in the target debugging command script.
After the target debugging command script is converted into standard AXI interface data, an AXI Interconnect IP in the Vivado tool needs to be called, and a debugging operation corresponding to the standard AXI interface data is performed according to a preset IP determined by a target interface module, so as to debug the target interface module, wherein the target interface module is an interface module corresponding to a target address in the target debugging command script.
Specifically, when the target interface module is an AHB Slave interface module, an AXI Interconnect IP and an AXI to AHB Lite Bridge IP in the Vivado tool are called to perform debugging operation corresponding to the standard AXI interface data, so as to debug the AHB Slave interface module. The AXI to AHB Lite Bridge IP is a configurable IP, and converts AXI transaction into AHB-Lite transaction. The AHB Slave interface module is mainly responsible for the data interaction process between the CPU and the register.
And when the target interface target is an AXI Slave interface module, calling an AXIInterconnect IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AXI Slave interface module. The AXI Interconnect IP transmits standard AXI interface data, so that for an AXI Slave interface module, the AXI Interconnect IP can be directly called to perform debugging operation corresponding to the standard AXI interface data.
And when the target interface is an AXI Master interface module, calling AXIInterconnect IP, AXI BRAM Controller IP and Bock Memory Generator IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AXI Master interface module. The AXI Master interface module generally functions to perform Data interaction with a memory or a DDR (Double Data Rate synchronous dynamic random access memory). Therefore, a Bock Memory Generator IP is called to replace the Memory or DDR, the AXI BRAMController IP is called to establish a communication connection between the AXI Interconnect IP and the Bock Memory Generator IP, and target data can be written into the Bock Memory Generator IP through a command script. And the AXI Master interface module reads out target data from the Bock Memory Generator IP for correctness comparison or subsequent processing and the like. The AXI BRAM Controller IP is a configurable IP, conforms to an AXI Slave protocol, is connected with an AXI interconnection device or an AXIMmaster device, and can communicate with a local BRAM (Block RAM).
And when the target interface is an AHB Master interface module, calling AXIInterconnect IP, AXI BRAM Controller IP, Bock Memory Generator IP and AHB Liteto AXI Bridge IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AHB Master interface module. Specifically, calling the AXI BRAM Controller IP to establish communication between the AXI Interconnecticut IP and the Bock Memory Generator IP; calling the Bock Memory Generator IP to simulate the Memory of the FPGA so as to store target data corresponding to the standard AXI interface data; and calling the AXI BRAMController IP and the AHB Lite to AXI Bridge IP to establish communication between the Bock Memory Generator IP and the AHB Master interface module, so that the AHB Master interface module reads the target data and carries out corresponding processing to debug the AHB Master interface module. Since AXI BRAM Controller IP can only connect AXI devices, it is necessary for the AHB Master interface module to add an AHB Lite to AXI Bridge module to convert AHB transactions to AXI transactions. The AHB Lite to AXI Bridge IP is a configurable IP and converts an AHB-Lite transaction into an AXI transaction.
The generation process of the AXI read transaction, the AXI-Lite write transaction and the AXI-Lite read transaction is similar to that of the AXI write transaction, and a parameterized use case can be conveniently generated through a TCL script.
Referring to fig. 3, a block diagram of an AMBA bus interface debugging on FPGA is shown. And after the target debugging command script transmitted through the JTAG is obtained, the JTAG to AXI IP in the Vivado tool is called to convert the target debugging command script into standard AXI interface data. And then, calling AXI interconnection IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AXI Slave interface module. And calling AXI Interconnect IP and AXI to AHB Lite Bridge IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AHB Slave interface module. And calling AXI Interconnect IP, AXI BRAM Controller IP and Bock Memory Generator IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AXI Master interface module. And calling AXI interconnection IP, AXI BRAM Controller IP, Bock MemoryGenerator IP and AHB Lite to AXI Bridge IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AHB Master interface module.
Referring to fig. 4, an embodiment of the present application discloses an AMBA bus interface debugging device for an FPGA, which is applied to an SOC-type FPGA, and includes:
the data acquisition module 11 is configured to acquire a target debugging command script, where the target debugging command script is a TCL script acquired by a Vivado tool;
a first IP invoking module 12, configured to invoke JTAG to AXI IP in the Vivado tool to convert the target debug command script into standard AXI interface data;
a second IP invoking module 13, configured to invoke an AXI Interconnect IP in the Vivado tool and perform, according to a preset IP determined by a target interface module, a debugging operation corresponding to the standard AXI interface data, so as to debug the target interface module, where the target interface module is an interface module corresponding to a target address in the target debugging command script.
Therefore, the method includes the steps of firstly obtaining a target debugging command script, wherein the target debugging command script is a TCL script obtained through a Vivado tool, then calling JTAG to AXI IP in the Vivado tool to convert the target debugging command script into standard AXI interface data, calling AXI INTERCONNECT IP in the Vivado tool and carrying out debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module so as to debug the target interface module, and the target interface module is an interface module corresponding to a target address in the target debugging command script. Therefore, the AMBA bus interface can be debugged by using the TCL command script by using the JTAG to AXI IP in the Vivado tool and matching the AXIInterconnect IP and the IP corresponding to the module to be debugged, so that the conventional mature IP is used, and the test case can be parametrized and generated by using the TCL command script, thereby greatly improving the debugging efficiency and the debugging flexibility.
Specifically, the data obtaining module 11 is configured to:
and acquiring the target debugging command script transmitted through the JTAG.
Further, the second IP invoking module 13 is configured to:
and when the target interface is the AHB Slave interface module, calling AXIInterconnect IP and AXI to AHB Lite Bridge IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AHB Slave interface module.
Further, the second IP invoking module 13 is configured to:
and when the target interface target is an AXI Slave interface module, calling an AXIInterconnect IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AXI Slave interface module.
Further, the second IP invoking module 13 is configured to:
and when the target interface is an AXI Master interface module, calling AXIInterconnect IP, AXI BRAM Controller IP and Bock Memory Generator IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AXI Master interface module.
Further, the second IP invoking module 13 is configured to:
and when the target interface is an AHB Master interface module, calling AXIInterconnect IP, AXI BRAM Controller IP, Bock Memory Generator IP and AHB Liteto AXI Bridge IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AHB Master interface module.
Further, the second IP invoking module 13 is specifically configured to:
invoking the AXI BRAM Controller IP to establish communication between the AXI Interconnect IP and the BockMemory Generator IP;
calling the Bock Memory Generator IP to simulate the Memory of the FPGA so as to store target data corresponding to the standard AXI interface data;
and calling the AXI BRAM Controller IP and the AHB Lite to AXI Bridge IP to establish communication between the Bock Memory Generator IP and the AHB Master interface module, so that the AHB Master interface module reads the target data and carries out corresponding processing to debug the AHB Master interface module.
Further, referring to fig. 5, an embodiment of the present application further discloses an SOC-type FPGA, including: a processor 21 and a memory 22.
Wherein the memory 22 is used for storing a computer program; the processor 21 is configured to execute the computer program to implement the AMBA bus interface debugging method of the FPGA disclosed in the foregoing embodiment.
For a specific process of the AMBA bus interface debugging method for the FPGA, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not described here again.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of other elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The method, the device and the FPGA for debugging the AMBA bus interface of the FPGA provided by the present application are introduced in detail, a specific example is applied in the present application to explain the principle and the implementation manner of the present application, and the description of the above embodiment is only used to help understanding the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. An AMBA bus interface debugging method of FPGA is characterized in that the method is applied to SOC type FPGA and comprises the following steps:
acquiring a target debugging command script, wherein the target debugging command script is a TCL script acquired by a Vivado tool;
calling JTAG to AXI IP in the Vivado tool to convert the target debugging command script into standard AXI interface data;
and calling AXI interconnection IP in the Vivado tool and carrying out debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module so as to debug the target interface module, wherein the target interface module is an interface module corresponding to a target address in the target debugging command script.
2. The AMBA bus interface debugging method of FPGA of claim 1, wherein said obtaining a target debug command script comprises:
and acquiring the target debugging command script transmitted through the JTAG.
3. The AMBA bus interface debugging method of FPGA of claim 1, wherein the invoking AXI Interconnect IP in the Vivado tool and performing the debugging operation corresponding to the standard AXI interface data according to the preset IP determined by the target interface module so as to debug the target interface module comprises:
if the target interface is the AHB Slave interface module, calling AXIInterconnect IP and AXI to AHB Lite Bridge IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AHB Slave interface module.
4. The AMBA bus interface debugging method of FPGA of claim 1, wherein the invoking AXI Interconnect IP in the Vivado tool and performing the debugging operation corresponding to the standard AXI interface data according to the preset IP determined by the target interface module so as to debug the target interface module comprises:
if the target interface target is an AXI Slave interface module, calling an AXIInterconnect IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AXI Slave interface module.
5. The AMBA bus interface debugging method of FPGA of claim 1, wherein the invoking AXI Interconnect IP in the Vivado tool and performing the debugging operation corresponding to the standard AXI interface data according to the preset IP determined by the target interface module so as to debug the target interface module comprises:
if the target interface target is an AXI Master interface module, calling AXIInterconnect IP, AXI BRAM Controller IP and Bock Memory Generator IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AXI Master interface module.
6. The AMBA bus interface debugging method of FPGA of claim 1, wherein the invoking AXI Interconnect IP in the Vivado tool and performing the debugging operation corresponding to the standard AXI interface data according to the preset IP determined by the target interface module so as to debug the target interface module comprises:
if the target interface is the AHB Master interface module, calling AXIInterconnect IP, AXI BRAM Controller IP, Bock Memory Generator IP and AHB Liteto AXI Bridge IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AHB Master interface module.
7. The AMBA bus interface debugging method for FPGA of claim 6, wherein said invoking AXI Interconnect IP, AXI BRAMController IP, Bock Memory generatori IP and AHB Lite to AXI Bridge IP in said Vivado tool to perform debugging operation corresponding to said standard AXI interface data, so as to debug said AHB Master interface module, comprises:
invoking the AXI BRAM Controller IP to establish communication between the AXI Interconnect IP and the BockMemory Generator IP;
calling the Bock Memory Generator IP to simulate the Memory of the FPGA so as to store target data corresponding to the standard AXI interface data;
and calling the AXI BRAM Controller IP and the AHB Lite to AXI Bridge IP to establish communication between the Bock Memory Generator IP and the AHB Master interface module, so that the AHB Master interface module reads the target data and carries out corresponding processing to debug the AHB Master interface module.
8. The utility model provides a Field Programmable Gate Array (FPGA) AMBA bus interface debugging device which characterized in that is applied to SOC type FPGA, includes:
the data acquisition module is used for acquiring a target debugging command script, wherein the target debugging command script is a TCL script acquired by a Vivado tool;
the first IP calling module is used for calling JTAG to AXI IP in the Vivado tool to convert the target debugging command script into standard AXI interface data;
and the second IP calling module is used for calling an AXI Interconnect IP in the Vivado tool and carrying out debugging operation corresponding to the standard AXI interface data according to a preset IP determined by a target interface module so as to debug the target interface module, wherein the target interface module is an interface module corresponding to a target address in the target debugging command script.
9. The AMBA bus interface debugging device of FPGA of claim 8, wherein said second IP call module is configured to:
and when the target interface is an AHB Master interface module, calling AXIInterconnect IP, AXI BRAM Controller IP, Bock Memory Generator IP and AHB Liteto AXI Bridge IP in the Vivado tool to carry out debugging operation corresponding to the standard AXI interface data so as to debug the AHB Master interface module.
10. An FPGA of SOC type, comprising:
a memory and a processor;
wherein the memory is used for storing a computer program;
the processor is used for executing the computer program to realize the AMBA bus interface debugging method of the FPGA of any one of claims 1 to 7.
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