CN114444420A - Verification IP integration method and system based on chip verification - Google Patents
Verification IP integration method and system based on chip verification Download PDFInfo
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Abstract
The invention provides a verification IP integration method and a verification IP integration system based on chip verification, wherein the method comprises the steps of responding to configuration information set by a user, rendering through a template engine, and creating a verification IP configuration file; instantiating a verification IP assembly supporting a protocol according to the UVM environment template file and the configuration information, and transmitting the configuration file to the verification IP assembly; compiling the verification IP source code, instantiating the corresponding verification IP interface through the compiled verification IP interface file, and transmitting the instantiated verification IP interface to the verification IP component. According to the method, on the basis of generating a set of general frames, the configuration information set by the user is obtained, the automatic integration of the verification platform related to the VIP is performed under different requirements of different projects, the time for a verification engineer to read corresponding VIP specification documents is shortened, a general and unified integration scheme is provided for the automatic integration, the unified maintenance of the verification at different levels is facilitated, and the reusability of the verification platform is enhanced.
Description
Technical Field
The invention relates to the technical field of chip function verification, in particular to a verification IP integration method and a verification IP integration system based on chip verification.
Background
With the high-speed development of integrated circuits, the functions of chips are more and more complex, the design complexity of the chips is more and more high, and the scale of devices on the chips is more and more large, so that great challenges are brought to the front-end verification of the chips. Chip verification engineers need to fully verify chip functions in terms of functional correctness and completeness. Through continuous development and industrial practice, at present, the most mainstream Verification Methodology is UVM (Universal Verification Methodology), the Verification language is SV (System Verilog, a hardware design and Verification language), and the Verification environment and platform based on SV and UVM are increasingly widely applied to chip front-end Verification.
The progress of chip projects is often tense, and chip verification tasks are heavier and heavier in the face of more and more complex functions. How to improve the verification efficiency and shorten the verification time in a tense project cycle becomes extremely important for developing chip projects. At present, a design method based on IP multiplexing is widely applied to SoC (system on chip) design, and the design of an on-chip bus and a peripheral bus is very important for the SoC. For this reason, many on-chip bus standards have emerged in the industry. Among them, the AMBA on-chip bus proposed by the ARM company is favored by vast IP (Internet Protocol) developers and SoC system integrators, and has become a mainstream industrial standard on-chip Protocol. For these standard protocol IPs, the authentication engineer needs to develop the corresponding authentication components VIP (authentication IPs) and integrate these VIPs into the authentication environment. The VIP provides a reliable and standard IP verification component for a chip verification engineer, and the time for the chip verification engineer to develop the VIP is reduced. However, integrating these VIPs into a UVM verification environment and performing pass-through self-tests and verification is also a time-consuming and labor-intensive task.
At present, in ASIC design verification, an AMBA bus protocol is a mainstream industrial standard on-chip protocol, a corresponding VIP in a test environment comes, and the AMBA bus protocol is widely applied to various large chip companies and provides a mature, reliable and high-portability verification IP solution for chip verification. The conventional verification automation generation platform only generates a set of general frames, does not integrate the corresponding VIP into the verification platform for a specific project, requires a verification engineer to read the corresponding VIP specification document to integrate the VIP into the verification platform, completes the connection between the DUT (design to be tested) and the VIP and related path tests, undoubtedly takes more time to know the use of the VIP, and greatly increases the possibility of human errors.
Disclosure of Invention
The invention provides a verification IP integration method and system based on chip verification, which are used for solving the problem that a special project test cannot be completed because the existing verification platform generates a VIP frame.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a verification IP integration method based on chip verification, which comprises the following steps:
rendering through a template engine in response to configuration information set by a user, and creating a verification IP configuration file;
instantiating a verification IP assembly supporting a protocol according to the UVM environment template file and the configuration information, and transmitting the configuration file to the verification IP assembly;
compiling the verification IP source code, instantiating the corresponding verification IP interface through the compiled verification IP interface file, and transmitting the instantiated verification IP interface to the verification IP component.
Further, the configuration information comprises a project name, a path and a file name stored in a top level file of the design to be verified, a top level module name of the design to be verified and parameters required by the integrated verification IP;
the required parameters include protocol type, master-slave mode, address bit width, data bit width and integration number.
Further, the method comprises, after generating the verification IP component, the steps of:
and establishing a connection relation between the verification IP and the DUT to be tested on the verification platform.
Further, the specific process of establishing the connection relationship between the verification IP and the DUT to be tested is as follows:
according to a DUT top-level file path defined by a user and a top-level module name, obtaining interface information of a DUT top-level module through regular matching;
defining signals of an interface module in the verification platform according to the interface information, and connecting the name of the DUT interface signal with the signals with the consistent names in the interface module of the verification platform;
determining the definition of the standard signal name of the current protocol type according to the preset protocol type in the configuration information, matching a top layer interface signal in the DUT, acquiring a verification platform interface module connected with the matched signal, deleting the connected verification platform interface module, and replacing the verification platform interface module with a verification IP interface.
Further, after establishing the connection relationship between the verification IP and the design under test DUT, the method further comprises the steps of:
a pass test of the DUT is performed against the test sequence provided by the validation IP.
Further, the path test comprises a read-write test and a slave end response test.
Further, the path test specifically includes:
acquiring a master-slave mode preset by a user;
if the master mode is adopted, a read-write test sequence corresponding to the protocol type is obtained, when a user calls the read-write sequence, address information is appointed, read data is obtained aiming at the read sequence, and write data is appointed aiming at the write sequence;
if the protocol type is the slave mode, a response test sequence corresponding to the protocol type is obtained, and when the response sequence is called, a user specifies response time and a response state.
The second invention of the present application provides a verification IP integration system based on chip verification, the system including a VIP integration module, the VIP integration module including:
the configuration file generation unit is used for responding to configuration information set by a user, rendering is carried out through a template engine, and a verification IP configuration file is created;
the protocol instantiation unit is used for instantiating a verification IP component supporting a protocol according to the UVM environment template file and the configuration information and transmitting the configuration file to the verification IP component;
and the integrated VIP unit is used for compiling the verification IP source code, instantiating the corresponding verification IP interface through the compiled verification IP interface file, and transmitting the instantiated verification IP interface to the verification IP component.
Further, the system also comprises a connection module, and the connection module establishes a connection relation between the verification IP and the DUT to be tested on the verification platform.
Further, the system also comprises a test module which conducts a path test of the DUT aiming at the test sequence provided by the verification IP.
The network service control apparatus according to the second aspect of the present invention can implement the methods according to the first aspect and the respective implementation manners of the first aspect, and achieve the same effects.
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
1. compared with the traditional verification automatic generation platform, the method has the advantages that on the basis of generating a set of universal framework, the configuration information set by the user is obtained, and the VIP related automatic integration of the verification platform under different requirements of different projects is realized, so that the time for reading corresponding VIP specification documents by the verification engineer is greatly shortened, and the verification engineer can concentrate on protocol and function verification rather than VIP use and integration. And secondly, the automatic integration provides a universal and unified integration scheme, so that the unified maintenance of verification at different levels is facilitated, and the reusability of the integrated system is enhanced.
2. The embodiment of the invention realizes the automatic connection of the DUT and the VIP and the automatic generation of the related path test. The complicated and repeated wiring operation of the verification engineer is reduced, human errors caused by carelessness and carelessness of the verification engineer during wiring work are reduced, and meanwhile, the working efficiency is improved; the automatic integration of the access test provides a basic test sequence for a verification engineer, so that the verification engineer can quickly construct a test case in the early stage and quickly detect whether the DUT meets a corresponding protocol.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of an embodiment of the method of the present invention;
fig. 2 is a schematic structural diagram of an embodiment of the system of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, specific example components and arrangements are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
As shown in fig. 1, a verification IP integration method based on chip verification provided in an embodiment of the present invention includes the following steps:
s1, responding to the configuration information set by the user, rendering through a template engine, and creating a verification IP configuration file;
s2, instantiating a verification IP component supporting a protocol according to the UVM environment template file and the configuration information, and transmitting the configuration file to the verification IP component;
s3, compiling the verification IP source code, instantiating the corresponding verification IP interface through the compiled verification IP interface file, and transmitting the instantiated verification IP interface to the verification IP component.
The configuration information of the setting in step S1 is exemplified as follows:
"wherein the projName is used to represent the folder name stored after the verification platform is generated, i.e. the project name; the DUT represents the path and file name of the top-level design file to be tested, and the DUT name represents the top-level module name of the top-level design module to be tested, and the top-level module interface of the design to be tested can be obtained by combining the DUT with the path and file name, thereby further completing the auto-wiring function of the VIP and DUT, and verifying the platform and DUT; the topName is used for indicating the prefix of the component name generated by the verification platform; backing up is a backup option for the same project name, if 'yes' is selected, backup is carried out on the verification platform of the same project name, and the backup is stored in a bak folder; svt _ VIP is the basic parameter required for VIP integration, and the verification automation platform will sequentially resolve the configuration of VIP according to the previous sequence number and integrate it in the environment. The first parameter is AMBA protocol selection of the VIP to be integrated, supports three protocols of APB, AHB and AXI, determines the type of the VIP component generated by the final verification platform, the second parameter represents Master-Slave mode selection of the VIP to be integrated, slv represents that the VIP to be integrated works in Slave mode, mst represents the VIP to be integrated and Master mode, the parameter determines the working mode selected by the VIP component generated in the final verification platform, particularly configuration selection of the VIP component in the verification platform, the third parameter represents the address bit width of the VIP to be integrated, the parameter determines the address bit width selected by the VIP component generated in the final verification platform, particularly configuration selection of the VIP component in the verification platform, the fourth parameter represents the data bit width of the VIP to be integrated, the parameter determines the data bit width selected by the VIP component generated in the final verification platform, the last parameter represents the number of VIP components to be integrated, and determines the number of VIP components generated in the final verification platform.
And step S1, creating the configuration file, rendering the configuration file through a template engine according to the user-defined configuration, completing the creation of a corresponding protocol configuration class, completing the selection of a master-slave mode, completing the selection of data bit width and address bit width, and completing the selection of the number of the VIPs to be integrated.
In step S2, the instantiation of the VIP component of the corresponding protocol is completed based on the UVM environment (UVM _ environment) template file, and the configuration file is delivered to the corresponding VIP component through UVM _ config _ db function provided by UVM. And (4) adding compilation of the VIP source code of the corresponding protocol in the Makefile template file according to the configuration information, namely compiling the VIP source code sequentially through the vcs command.
In step S3, according to the configuration information, adding corresponding VIP interface instantiation through the compiled VIP interface file in the verification platform top-level template file, and passing it to the VIP component in Environment through the UVM _ config _ db function provided by the UVM.
In one implementation of the embodiment of the method of the present invention, after generating the verification IP component, the method further includes:
s4, establishing the connection relation between the verification IP and the DUT to be tested on the verification platform.
The specific process for establishing the connection relationship between the verification IP and the design DUT to be tested is as follows:
s41, according to the DUT top-level file path and the top-level module name defined by the user, obtaining interface information of the DUT top-level module through regular matching, wherein the interface information specifically comprises the name, bit width and input/output type of the signal;
s42, defining the signal of the interface module in the verification platform according to the interface information, and connecting the name of the DUT interface signal with the same name in the interface module of the verification platform;
s43, according to the preset protocol type in the configuration information, determining the definition of the standard signal name of the current protocol type, matching the top layer interface signal in the DUT, obtaining the verification platform interface module connected with the matched signal, deleting the connected verification platform interface module, and replacing the verification platform interface module with a verification IP interface.
In one implementation manner of the embodiment of the method of the present invention, after establishing the connection relationship between the verification IP and the DUT to be tested, the method further includes the steps of:
and S5, testing the path of the DUT aiming at the test sequence provided by the verification IP.
The path test comprises a read-write test and a slave end response test.
The access test sets a test sequence under each VIP attribute in a sequence template file, selects according to different configurations of a user, and selectively provides the corresponding test sequence to the user in the sequence file, specifically:
s51, acquiring a master-slave mode preset by a user;
s52, if the master mode is adopted, a read-write test sequence corresponding to the protocol type is obtained, when a user calls the read-write sequence, address information is appointed, read data are obtained aiming at the read sequence, and write data are appointed aiming at the write sequence;
if the slave mode is the S53, a response test sequence corresponding to the protocol type is acquired, and the user specifies the response time and the response state when invoking the response sequence.
The embodiment of the invention also provides a verification IP integration system based on chip verification, which comprises a VIP integration module 1, wherein the VIP integration module 1 comprises a configuration file generation unit 11, a protocol instantiation unit 12 and an integrated VIP unit 13.
The configuration file generating unit 11 responds to configuration information set by a user, renders through a template engine, and creates a verification IP configuration file; the protocol instantiation unit 12 instantiates a verification IP component supporting a protocol according to the UVM environment template file and the configuration information, and transmits the configuration file to the verification IP component; the integrated VIP unit 13 is configured to compile the verification IP source code, instantiate the corresponding verification IP interface according to the compiled verification IP interface file, and transmit the instantiated verification IP interface to the verification IP component.
In one implementation manner of the system embodiment of the present invention, the system further includes a connection module 2, and the connection module 2 establishes a connection relationship between the verification IP and the DUT to be tested on the verification platform.
In an implementation manner of the embodiment of the system according to the present invention, the system further includes a test module, and the test module performs a path test of the DUT with respect to a test sequence provided by the verification IP.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (10)
1. A verification IP integration method based on chip verification is characterized by comprising the following steps:
rendering through a template engine in response to configuration information set by a user, and creating a verification IP configuration file;
instantiating a verification IP assembly supporting a protocol according to the UVM environment template file and the configuration information, and transmitting the configuration file to the verification IP assembly;
compiling the verification IP source code, instantiating the corresponding verification IP interface through the compiled verification IP interface file, and transmitting the instantiated verification IP interface to the verification IP component.
2. The method of claim 1, wherein the configuration information includes a project name, a path and a file name stored in a top-level file of the design to be verified, a top-level module name of the design to be verified, and parameters required for integrating the verification IP;
the required parameters include protocol type, master-slave mode, address bit width, data bit width and integration number.
3. The verification-based IP integration method of claim 1, wherein said method further comprises, after generating the verification IP component, the steps of:
and establishing a connection relation between the verification IP and the DUT to be tested on the verification platform.
4. The verification IP integration method based on chip verification as claimed in claim 3, wherein the specific process of establishing the connection relationship between the verification IP and the DUT to be designed is as follows:
according to a DUT top-level file path defined by a user and a top-level module name, obtaining interface information of a DUT top-level module through regular matching;
defining signals of an interface module in the verification platform according to the interface information, and connecting the name of the DUT interface signal with the signals with the consistent names in the interface module of the verification platform;
determining the definition of the standard signal name of the current protocol type according to the preset protocol type in the configuration information, matching a top layer interface signal in the DUT, acquiring a verification platform interface module connected with the matched signal, deleting the connected verification platform interface module, and replacing the verification platform interface module with a verification IP interface.
5. The method for verifying IP integration based on chip verification as claimed in claim 3, wherein the method further comprises the following steps after establishing the connection relationship between the verification IP and the DUT to be designed:
a pass test of the DUT is performed against the test sequence provided by the validation IP.
6. The method of claim 5, wherein the path test comprises a read-write test and a slave-end response test.
7. The verification-based IP integration method of claim 6, wherein the path test is specifically:
acquiring a master-slave mode preset by a user;
if the master mode is adopted, a read-write test sequence corresponding to the protocol type is obtained, when a user calls the read-write sequence, address information is appointed, read data is obtained aiming at the read sequence, and write data is appointed aiming at the write sequence;
if the protocol type is the slave mode, a response test sequence corresponding to the protocol type is obtained, and when a user calls the response sequence, the response time and the response state are appointed.
8. A verification IP integration system based on chip verification, the system comprising a VIP integration module, the VIP integration module comprising:
the configuration file generation unit is used for responding to configuration information set by a user, rendering is carried out through a template engine, and a verification IP configuration file is created;
the protocol instantiation unit is used for instantiating a verification IP component supporting a protocol according to the UVM environment template file and the configuration information and transmitting the configuration file to the verification IP component;
and the integrated VIP unit is used for compiling the verification IP source code, instantiating the corresponding verification IP interface through the compiled verification IP interface file and transmitting the instantiated verification IP interface to the verification IP component.
9. The integrated system of claim 8, further comprising a connection module, wherein the connection module establishes a connection relationship between the verification IP and the DUT at the verification platform.
10. The integrated system of claim 9, further comprising a test module for performing path testing of the DUT with respect to the test sequence provided by the verification IP.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115345099A (en) * | 2022-08-31 | 2022-11-15 | 沐曦科技(北京)有限公司 | Method, electronic device and medium for automatically generating chip verification platform |
| CN116167309A (en) * | 2022-12-28 | 2023-05-26 | 芯动微电子科技(武汉)有限公司 | Chip performance verification method and system |
| CN116738909A (en) * | 2023-06-25 | 2023-09-12 | 成都电科星拓科技有限公司 | Memory integration method of integrated circuit |
| CN116756049A (en) * | 2023-08-17 | 2023-09-15 | 上海燧原科技有限公司 | Universal verification method and device for chip, electronic equipment and storage medium |
| CN117057286A (en) * | 2023-10-11 | 2023-11-14 | 成都电科星拓科技有限公司 | SMBus module level verification system based on UVM and VIP |
| CN117290254A (en) * | 2023-11-24 | 2023-12-26 | 沐曦集成电路(南京)有限公司 | Chip verification method based on component automation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115345099A (en) * | 2022-08-31 | 2022-11-15 | 沐曦科技(北京)有限公司 | Method, electronic device and medium for automatically generating chip verification platform |
| CN116167309A (en) * | 2022-12-28 | 2023-05-26 | 芯动微电子科技(武汉)有限公司 | Chip performance verification method and system |
| CN116167309B (en) * | 2022-12-28 | 2023-10-31 | 芯动微电子科技(武汉)有限公司 | Chip performance verification method and system |
| CN116738909A (en) * | 2023-06-25 | 2023-09-12 | 成都电科星拓科技有限公司 | Memory integration method of integrated circuit |
| CN116738909B (en) * | 2023-06-25 | 2024-05-24 | 成都电科星拓科技有限公司 | Memory integration method of integrated circuit |
| CN116756049A (en) * | 2023-08-17 | 2023-09-15 | 上海燧原科技有限公司 | Universal verification method and device for chip, electronic equipment and storage medium |
| CN116756049B (en) * | 2023-08-17 | 2023-11-07 | 上海燧原科技有限公司 | Universal verification method and device for chip, electronic equipment and storage medium |
| CN117057286A (en) * | 2023-10-11 | 2023-11-14 | 成都电科星拓科技有限公司 | SMBus module level verification system based on UVM and VIP |
| CN117057286B (en) * | 2023-10-11 | 2024-01-30 | 成都电科星拓科技有限公司 | SMBus module level verification system based on UVM and VIP |
| CN117290254A (en) * | 2023-11-24 | 2023-12-26 | 沐曦集成电路(南京)有限公司 | Chip verification method based on component automation |
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