CN114327476A - Chip design file generation method and device and chip design method and device - Google Patents
Chip design file generation method and device and chip design method and device Download PDFInfo
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- CN114327476A CN114327476A CN202111604615.1A CN202111604615A CN114327476A CN 114327476 A CN114327476 A CN 114327476A CN 202111604615 A CN202111604615 A CN 202111604615A CN 114327476 A CN114327476 A CN 114327476A
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Abstract
The application provides a chip design file generation method and device, and a chip design method and device, wherein the chip design file generation method comprises the following steps: obtaining a pin description file of a chip; the pin description file records the description information of each pin; generating an RTL code and a verification code of the chip according to the description information; outputting a chip design file; the chip design file includes RTL code and verification code. The efficiency of chip GPIO architectural design can be improved in this application, and when the chip design needs to be revised, the designer only needs to revise corresponding information in the pin description file can automatic new generation RTL code and verification code, need not the manual work and compiles again, avoids artifical compiling to produce the mistake and leak, shortens chip research and development time.
Description
Technical Field
The embodiment of the application relates to the technical field of chip design, in particular to a method and a device for generating a chip design file and a method and a device for designing a chip.
Background
As chip technology develops, chip architectures tend to be complex. In the GPIO mechanism compatible architecture, each pad, family, and community has several attributes, respectively, so that one architecture can have hundreds of pads (pads) and be organized into tens of families (family) and communities (community), resulting in a huge amount of compiled code data. Therefore, it takes a long time for one GPIO design team to complete one GPIO architecture design.
Disclosure of Invention
The embodiment of the application provides a chip design file generation method and device, a chip design method and device, a computer device and a storage medium, and can improve the efficiency of chip GPIO architecture design.
A chip design file generation method comprises the following steps:
obtaining at least one pin description file of a chip; wherein the pin description file comprises description information for describing one or more pins of the chip;
generating an RTL code and a verification code of the chip according to the description information;
outputting a chip design file; wherein the chip design file comprises the RTL code and the verification code.
A chip design method, comprising:
obtaining a chip design file; the chip design file is obtained according to the chip design file generation method;
instantiating the chip according to the RTL code in the chip design file;
and verifying the chip according to the verification code in the chip design file.
A chip design file generation device comprises:
the file acquisition module is used for acquiring at least one pin description file of the chip; wherein the pin description file comprises description information for describing one or more pins of the chip;
the code generation module is used for generating an RTL code and a verification code of the chip according to the description information;
the design file output module is used for outputting a chip design file; wherein the chip design file comprises the RTL code and the verification code.
A chip design apparatus, comprising:
the design file acquisition module is used for acquiring a chip design file; the chip design file is generated by the chip design file generating device;
the chip instantiation module is used for instantiating the chip according to the RTL code in the chip design file;
and the verification module is used for verifying the chip according to the verification code in the chip design file.
A computer device comprising a memory and a processor, the memory having a computer program stored therein, wherein the computer program, when executed by the processor, causes the processor to perform the steps of:
obtaining at least one pin description file of a chip; wherein the pin description file comprises description information for describing one or more pins of the chip;
generating an RTL code and a verification code of the chip according to the description information;
outputting a chip design file; wherein the chip design file comprises the RTL code and the verification code.
A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of:
obtaining a pin description file of a chip; the pin description file records description information of each pin;
generating an RTL code and a verification code of the chip according to the description information;
outputting a chip design file; the chip design file includes the RTL code and the verification code.
According to the chip design file generation method, the chip design file generation device, the chip design method, the chip design device, the computer equipment and the storage medium, the description information is obtained from the pin description file by obtaining the pin description file of the chip, the RTL code and the verification code of the chip are automatically compiled and generated according to the description information and the chip design file is output, manual compilation is replaced, the efficiency of the GPIO architecture design of the chip is improved, when the chip design needs to be modified, a designer can automatically and newly generate the RTL code and the verification code only by modifying corresponding information in the pin description file, manual recompilation is not needed, mistakes and omissions caused by manual compilation are avoided, and the research and development time of the chip is shortened.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram of the architecture of a chip in one embodiment;
FIG. 2 is a flow diagram of a method for generating a chip design file in one embodiment;
FIG. 3 is a flow diagram of steps in one embodiment for generating RTL code and verification code for a chip based on description information;
FIG. 4 is a flowchart of a chip design file generation method in another embodiment;
FIG. 5 is a flowchart of a chip design file generation method in yet another embodiment;
FIG. 6 is a flow diagram of a method of chip design in one embodiment;
FIG. 7 is a block diagram showing the structure of a chip design file generating apparatus according to an embodiment;
FIG. 8 is a second block diagram illustrating the structure of an apparatus for generating a chip design file according to an embodiment;
FIG. 9 is a third block diagram illustrating a chip design file generating apparatus according to an embodiment;
FIG. 10 is a block diagram showing the structure of a chip design document generating apparatus according to an embodiment;
FIG. 11 is a block diagram showing the structure of a chip design apparatus according to an embodiment;
FIG. 12 is a block diagram of a computing device in one embodiment.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth to provide a thorough understanding of the present application, and in the accompanying drawings, preferred embodiments of the present application are set forth. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. This application is capable of embodiments in many different forms than those described herein and those skilled in the art will be able to make similar modifications without departing from the spirit of the application and it is therefore not intended to be limited to the specific embodiments disclosed below.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, as used in this specification, the term "and/or" includes any and all combinations of the associated listed items.
As shown in fig. 1, in one GPIO mechanism compatible architecture, each pad (pad), family (family), and community (community) has at least 20+, 30+, and approximately 10 attributes, respectively. Such a GPIO architecture can have at least 100 pads organized into tens of homes and communities, resulting in a very large amount of data for chip design. In addition to this large data set, designers also need to establish the correct signal connections between the community Soft IP (SIP, Soft IP) and the Hard IP (HIP, Hard IP) of the pad. And the verification team needs to verify all pins of the chip. In addition, a large number of signals need to be properly connected in the top module to achieve full chip integration. Therefore, without any automation, it takes a long time to complete the design and verification of the GPIO architecture for a new project. Moreover, due to the extremely large data volume, the manual implementation process of the GPIO is very prone to errors.
Based on the above problems, the chip design file generation method related in the embodiment of the application can be applied to chip GPIO architecture design, and can automatically generate a chip design file according to a pin description file of a chip provided by a designer. The Chip referred to in the present application may be any Digital circuit Chip, and specifically may be a processor Chip such as a DSP (Digital Signal Processing) Chip or an SOC (System on Chip) Chip.
As shown in fig. 2, in one embodiment, the chip design file generation method includes steps 201 to 203.
Step 201, at least one pin description file of the chip is obtained.
The pin description file includes description information of one or more pins of the chip, and the pin description file is provided by a designer responsible for designing each module of the chip, and includes all relevant description information of pin function implementation, such as function multiplexing of the pins, pin connection information, names, types, and the like. Specifically, the pin description file may obtain description information from a template form to each designer of the chip design, and obtain the description information of each pin from the functional module, and the description information is collected into one or more pin description files. And if the pin description files are multiple, generating the chip design file based on the multiple pin description files in a cooperative manner.
In one embodiment, the pin description file may be an Excel file, and the designer may fill the description information to be provided in the form according to the respective responsible portions.
And 202, generating an RTL code and a verification code of the chip according to the description information.
The RTL (Resistor Transistor Logic) code is an implementation code for describing an ideal function of a chip by using a hardware description language (Verilog or VHDL). The verification code is the verification code described in a hardware description language (Verilog or VHDL) for implementing chip front-end self-test.
Reading a pin description file of a chip, extracting description information in the pin description file, and converting the description information into a hardware description language, specifically, converting the description information into the hardware description language by using a preset conversion logic, and finally generating an RTL code and a verification code.
In one embodiment, a designer needs to modify the chip design, only needs to modify description information of relevant parts in the pin description file, and regenerates the RTL code and the verification code according to a new pin description file without manual recompilation, and uses computer equipment to perform automatic compilation according to preset logic, so that compilation errors can be reduced.
And step 203, outputting a chip design file.
The chip design file comprises an RTL code and a verification code. The instantiation of the chip can be realized based on the RTL code, and the front-end simulation verification of the chip can be realized by utilizing the verification code.
According to the chip design file generation method, the pin description file of the chip is obtained, the description information is obtained from the pin description file, the RTL code and the verification code of the chip are automatically compiled and generated according to the description information, the chip design file is output, manual compilation is replaced, the efficiency of GPIO (general purpose input/output) architecture design of the chip is improved, when the chip design needs to be modified, a designer can automatically and newly generate the RTL code and the verification code only by modifying corresponding information in the pin description file, manual recompilation is not needed, mistakes and omissions caused by manual compilation are avoided, and the research and development time of the chip is shortened.
In one embodiment, the at least one pin description file comprises a first description file and a second description file, the first description file is associated with the second description file at least through description of a first pin, and the first pin is one of pins of the chip; the chip design file generation method further comprises the following steps:
identifying the change content of the first description information of the first pin by the first description file;
and correspondingly modifying the second description file according to the modified content.
In order to implement the function multiplexing of the pins in the chip, the designs of different functional modules of the chip may be related to the same pin, and when the first description file of the first pin is modified, an engineer needs to modify the related description file correspondingly, which is prone to error and leakage. In this embodiment, by recognizing that the first description information of the first pin in the first description file is changed and recognizing the change content, the corresponding part in the second description file is automatically modified according to the change content, so that modification omission is avoided, and the generation efficiency of the chip design file is improved.
In one embodiment, modifying the second description file according to the modified content correspondingly includes:
modifying second description information of the second description file to the first pin according to the modified content;
and modifying the third description information of the second pin by the second description file.
The second description information is description information of the first pin in the second description file, and is the description information of the first pin together with the first description information, so that when the first description information is changed, the second description information can be automatically modified according to the change content. The third description information is description information about a second pin in the second description file, the second pin is another pin of the chip associated with the first pin, and the third description information and the second description information belong to the same description file, namely relate to the same functional module, so the third description information relating to the second pin in the second description file can be modified correspondingly according to the change content.
In one embodiment, the description information includes pin function description information, register description information, and IO connection description information.
The pin function description information is configuration parameter information for describing the chip pin function implementation, and may include multiplexing relationship of pins, used I/O type and port name of the I/O pin, whether the pin belongs to an ASIC or is only used for an FPGA, and whether the pin is of a special type such as a test mode, a clock, a reset pin, and a control signal for controlling multiplexing of the pin. The register description information records configuration parameter information of the registers, including the name, offset address, type, read-write permission, signal name of each signal field, bit segment definition, default value, comment and the like of each register. The IO connection description information is used to describe a hardware connection relationship of each IO port.
In one embodiment, the description information may only include pin function description information, the register description information and the IO connection description information may be preset, and a designer may generate an iterated or modified chip design file by providing the pin function description information according to each iterative design or function modification.
In one embodiment, the description information may only include pin function description information and register description information, the connection description information may be preset, and a designer may generate an iterated or modified chip design file by providing the pin function description information and the register description information according to each iterative design or function modification.
In one embodiment, the pin function description information includes function (function) information and DFT (design for test) information. In the original design of the chip, various hardware logic information for improving the testability (including controllability and observability) of the chip is inserted at the stage, namely DFT information, and the functional information is used for describing hardware logic information when pins realize the functions of each functional module.
Part of pins can support the function multiplexing of the functional module and also can relate to DFT test, RTL codes capable of realizing the function multiplexing and DFT can be directly generated by obtaining pin description files comprising the function information and the DFT information, and compared with the prior art that the design of the functional module is completed and then the DFT is designed and inserted, the efficiency of chip design can be improved.
In one embodiment, as shown in fig. 3, the generating the RTL code and the verification code of the chip according to the description information includes steps 301 to 303:
and 301, generating an RTL code of the soft IP according to the pin function description information and the register description information.
The Soft IP (Soft IP, SIP) is a functional block described by using a hardware description language such as Verilog/VHDL, and does not relate to a specific circuit element. The RTL code of the soft IP needs to be generated according to the pin function description information and the register description information, and when the RTL code of the soft IP is generated, the pin function description information and the register description information can be captured from a pin description file and then converted into the RTL code based on the captured information.
And step 302, generating RTL codes of the hard IP according to the IO connection description information and the register description information.
The Hard IP (Hard IP, HIP) is a functional module implemented by a circuit element, and an I/O port of the functional module needs to be defined to implement its function in a chip, so a corresponding RTL code needs to be generated, and for the RTL code of the Hard IP, IP connection description information and register description information in a pin description file need to be captured and converted to obtain the RTL code.
And step 303, generating the verification code according to the pin function description information, the register description information and the IO connection description information.
When the pin function description information, the register description information and the IO connection description information are determined, namely the working logic of the chip is also determined, the DFT information comprises test excitation, the test excitation is a value to be loaded at the input end of the chip, information which is output based on the test excitation chip can be generated based on the working logic of the chip, the output part of information is verification codes, and when the chip is subjected to front-end simulation test, self-checking is realized by comparing a simulation output result with the verification codes.
In one embodiment, the key word information in the pin description file can be identified through a script program, so that the pin function description information, the register description information and the IO connection description information corresponding to each pin are obtained through addressing.
As shown in fig. 4, in one embodiment, the chip design file generating method includes steps 401 to 405:
step 401, at least one pin description file of the chip is obtained.
The pin description file records description information of one or more pins, and the description information comprises pin function description information, register description information and IO connection description information.
Step 402, detecting whether the pin function description information has multiplexing function conflict.
The multiplexing function conflict means that conflict exists between two or more functions implemented on a certain pin, and if the multiplexing function conflict exists on the pin, the chip cannot normally implement the functions. Specifically, the pin function description information may be detected by a preset multiplexing function conflict detection model, the multiplexing function conflict detection model may be configured with common pin multiplexing function conflicts, and when detecting by using the multiplexing function conflict detection model, if a corresponding multiplexing function conflict is identified, it is determined that a multiplexing function conflict exists.
In one embodiment, the multiplexing function conflict detection model can be updated according to the pin multiplexing function conflict encountered by a designer in the chip design process, so that the reliability of automatic detection of the multiplexing function conflict is optimized. In one embodiment, the multiplex function conflict detection model may perform iterative learning according to a simulation test to update the pin multiplex function conflict type.
And step 403, if a multiplexing function conflict exists, generating a function description error report prompt.
The function description error-reporting prompt is used for prompting that the description information of multiplexing function conflict exists in the pin function description information, so that a designer can quickly determine the description information to be modified without manual investigation, and the chip design efficiency is improved.
And step 404, if no multiplexing function conflict exists, generating an RTL code and a verification code of the chip according to the description information.
Step 405, outputting a chip design file.
And if no multiplexing function conflict exists through detection, generating an RTL code and a verification code according to the description information in the pin description file, and forming a chip design file for output.
According to the embodiment, the validity of the description information in the pin description file can be detected before the chip design file is generated, the situation that the pin multiplexing function conflict is found in the simulation stage is reduced, and the chip design efficiency is improved.
As shown in fig. 5, in one embodiment, the chip design file generation method includes steps 501 to 505:
step 501, at least one pin description file of a chip is obtained.
The pin description file records description information of one or more pins of the chip, and the description information comprises pin function description information, register description information and IO connection description information.
Step 502, detecting whether the IO connection description information has a connection conflict.
The connection conflict means that there is a conflict in connection definitions of a certain IO port, for example, the same IO port defines an opposite functional connection, and if there is a connection conflict in the IO port, the chip cannot normally implement its function. Specifically, the IO connection description information may be detected through a preset IO connection conflict detection model, the IO connection conflict detection model may be configured with common IO port connection conflicts, and IO connection conflicts are determined to exist if corresponding connection conflicts are identified during detection.
In one embodiment, the IO connection conflict detection model may be updated according to an IO port connection conflict encountered by a designer in a chip design process, so as to optimize reliability of automatic detection of the connection conflict. In one embodiment, the IO connection conflict detection model may perform iterative learning according to a simulation test, and update the IO connection conflict type.
And 503, if the connection conflict exists, generating an IO connection error report prompt.
The IO connection error reporting prompt is used for prompting that description information of IO port connection conflict exists in the IO connection description information, so that a designer can quickly determine the description information to be modified without manual investigation, and the efficiency of chip design is improved.
And step 504, if no connection conflict exists, generating an RTL code and a verification code of the chip according to the description information.
And step 505, outputting the chip design file.
And if no connection conflict exists, continuously generating the RTL code and the verification code of the chip according to the description information to form chip design file output.
According to the embodiment, IO connection conflict detection is performed before the chip design file is generated, design mistakes and omissions in the chip research and development process can be effectively reduced, and the chip research and development efficiency is improved.
In one embodiment, semantic and/or syntax validity detection can be performed on the description information, so that errors and omissions in the design stage are further reduced.
In one embodiment, the RTL code and the verification code may be checked by a tool such as lin, Spyglass, and the like, specifically, the design rule check is performed on the chip circuit, including the writing style of the RTL code and the verification code, DFT, naming rule, circuit synthesis related rule, and the like.
As shown in fig. 6, an embodiment of the present application further provides a chip design method, including steps 601 to 603:
step 601, obtaining a chip design file.
The chip design file is obtained according to the chip design file generation method in the above embodiment.
Step 602, instantiating the chip according to the RTL code in the chip design file.
The instantiation of the chip can be realized by using the RTL code automatically generated in the method for generating the chip design file, namely, the chip simulation is realized based on the RTL code.
Step 603, verifying the chip according to the verification code in the chip design file.
If the RTL code logic of the chip design is correct, after the test stimulus is input, the output result of the chip should be consistent with the verification code, the front-end self-check of the chip design can be realized through the verification code, and if the RTL code logic is inconsistent with the verification code, a designer can check and modify the pin description file, regenerate a new RTL code and the verification code, and instantiate and verify the RTL code. The early design of each chip needs multiple simulation test iterations and errors are corrected, and the method and the device can reduce time consumed by manual code compiling and improve chip design efficiency.
It should be understood that although the various steps in the flow charts of fig. 2-6 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-6 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
Fig. 7 is a block diagram of a chip design file generation apparatus according to an embodiment. As shown in fig. 7, the chip design file generating apparatus 700 includes:
a file obtaining module 710, configured to obtain at least one pin description file of a chip; the pin description file comprises description information for describing one or more pins of the chip;
a code generation module 720, configured to generate an RTL code and a verification code of the chip according to the description information;
a design file output module 730 for outputting a chip design file; the chip design file includes RTL code and verification code.
As shown in FIG. 8, in one embodiment, the code generation module 720 includes:
a first RTL code generation unit 721 configured to generate an RTL code of the soft IP according to the pin function description information and the register description information;
the second RTL code generation unit 722 generates an RTL code of the hard IP according to the IO connection description information and the register description information;
the verification code generation unit 723 generates a verification code according to the pin function description information, the register description information, and the IO connection description information.
As shown in fig. 9, in one embodiment, the chip design file generating apparatus 700 further includes:
a first conflict detection module 740, configured to detect whether there is a multiplexing function conflict in the pin function description information;
the first error reporting module 750 is configured to generate a function description error reporting prompt when detecting that there is a multiplexing function conflict.
As shown in fig. 10, in one embodiment, the chip design file generating apparatus 700 further includes:
a second conflict detection module 760, configured to detect whether a connection conflict exists in the IO connection description information;
the second error reporting module 770 is configured to generate an IO connection error reporting prompt when detecting that a connection conflict exists.
As shown in fig. 11, an embodiment of the present application further provides a chip design apparatus 800, including:
a design file obtaining module 810, configured to obtain a chip design file; the chip design file is generated by the chip design file generation device of the embodiment;
a chip instantiation module 820, configured to instantiate a chip according to the RTL code in the chip design file;
and the verification module 830 is configured to verify the chip according to the verification code in the chip design file.
The division of each module in the chip design file generation apparatus and the chip design apparatus is only for illustration, and in other embodiments, the chip design file generation apparatus and the chip design apparatus may be divided into different modules as needed to complete all or part of the functions of the chip design file generation apparatus and the chip design apparatus.
For specific limitations of the chip design file generation apparatus, reference may be made to the above limitations of the chip design file generation method, and for specific limitations of the chip design apparatus, reference may be made to the above limitations of the chip design method, which are not described herein again. The chip design file generation device and each module in the chip design device may be wholly or partially implemented by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 12. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a chip design file generation method and/or a chip design method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 12 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:
obtaining at least one pin description file of a chip; the pin description file comprises description information for describing one or more pins of the chip;
generating an RTL code and a verification code of the chip according to the description information;
outputting a chip design file; the chip design file comprises an RTL code and a verification code.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
generating an RTL code of the soft IP according to the pin function description information and the register description information;
generating RTL codes of the hard IP according to the IO connection description information and the register description information;
and generating a verification code according to the pin function description information, the register description information and the IO connection description information.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
detecting whether the multiplexing function conflict exists in the pin function description information;
if the multiplexing function conflict exists, generating a function description error report prompt;
and if the multiplexing function conflict does not exist, executing the step to generate the RTL code and the verification code of the chip according to the description information.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
detecting whether connection conflict exists in the IO connection description information;
if the connection conflict exists, generating an IO connection error report prompt;
and if the connection conflict does not exist, generating the RTL code and the verification code of the chip according to the description information.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
identifying the change content of the first description information of the first pin by the first description file;
and correspondingly modifying the second description file according to the modified content.
In one embodiment, the processor, when executing the computer program, further performs the steps of:
modifying second description information of the second description file to the first pin according to the modified content;
modifying third description information of the second pin by the second description file; wherein the second pin is another pin of the chip associated with the first pin.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:
obtaining a chip design file; the chip design file is obtained according to the chip design file generation method;
instantiating the chip according to the RTL code in the chip design file;
and verifying the chip according to the verification code in the chip design file.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which when executed by a processor performs the steps of:
obtaining a pin description file of a chip; the pin description file records the description information of each pin;
generating an RTL code and a verification code of the chip according to the description information;
outputting a chip design file; the chip design file includes RTL code and verification code.
In one embodiment, the computer program when executed by the processor further performs the steps of:
generating an RTL code of the soft IP according to the pin function description information and the register description information;
generating RTL codes of the hard IP according to the IO connection description information and the register description information;
and generating a verification code according to the pin function description information, the register description information and the IO connection description information.
In one embodiment, the computer program when executed by the processor further performs the steps of:
detecting whether the multiplexing function conflict exists in the pin function description information;
if the multiplexing function conflict exists, generating a function description error report prompt;
and if the multiplexing function conflict does not exist, executing the step to generate the RTL code and the verification code of the chip according to the description information.
In one embodiment, the computer program when executed by the processor further performs the steps of:
detecting whether connection conflict exists in the IO connection description information;
if the connection conflict exists, generating an IO connection error report prompt;
and if the connection conflict does not exist, generating the RTL code and the verification code of the chip according to the description information.
In one embodiment, the computer program when executed by the processor further performs the steps of:
identifying the change content of the first description information of the first pin by the first description file;
and correspondingly modifying the second description file according to the modified content.
In one embodiment, the computer program when executed by the processor further performs the steps of:
modifying second description information of the second description file to the first pin according to the modified content;
modifying third description information of the second pin by the second description file; wherein the second pin is another pin of the chip associated with the first pin.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which when executed by a processor performs the steps of:
obtaining a chip design file; the chip design file is obtained according to the chip design file generation method;
instantiating the chip according to the RTL code in the chip design file;
and verifying the chip according to the verification code in the chip design file.
In one embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, performs the steps of:
obtaining a pin description file of a chip; the pin description file records the description information of each pin;
generating an RTL code and a verification code of the chip according to the description information;
outputting a chip design file; the chip design file includes RTL code and verification code.
In one embodiment, the computer program when executed by the processor further performs the steps of:
generating an RTL code of the soft IP according to the pin function description information and the register description information;
generating RTL codes of the hard IP according to the IO connection description information and the register description information;
and generating a verification code according to the pin function description information, the register description information and the IO connection description information.
In one embodiment, the computer program when executed by the processor further performs the steps of:
detecting whether the multiplexing function conflict exists in the pin function description information;
if the multiplexing function conflict exists, generating a function description error report prompt;
and if the multiplexing function conflict does not exist, executing the step to generate the RTL code and the verification code of the chip according to the description information.
In one embodiment, the computer program when executed by the processor further performs the steps of:
detecting whether connection conflict exists in the IO connection description information;
if the connection conflict exists, generating an IO connection error report prompt;
and if the connection conflict does not exist, generating the RTL code and the verification code of the chip according to the description information.
In one embodiment, the computer program when executed by the processor further performs the steps of:
identifying the change content of the first description information of the first pin by the first description file;
and correspondingly modifying the second description file according to the modified content.
In one embodiment, the computer program when executed by the processor further performs the steps of:
modifying second description information of the second description file to the first pin according to the modified content;
modifying third description information of the second pin by the second description file; wherein the second pin is another pin of the chip associated with the first pin.
In one embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, performs the steps of:
obtaining a chip design file; the chip design file is obtained according to the chip design file generation method;
instantiating the chip according to the RTL code in the chip design file;
and verifying the chip according to the verification code in the chip design file.
Any reference to memory, storage, database, or other medium used herein may include non-volatile and/or volatile memory. The nonvolatile Memory may include a ROM (Read-Only Memory), a PROM (Programmable Read-Only Memory), an EPROM (Erasable Programmable Read-Only Memory), an EEPROM (Electrically Erasable Programmable Read-Only Memory), or a flash Memory. Volatile Memory can include RAM (Random Access Memory), which acts as external cache Memory. By way of illustration and not limitation, RAM is available in many forms, such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), Double Data Rate DDR SDRAM (Double Data Rate Synchronous Random Access Memory), ESDRAM (Enhanced Synchronous Dynamic Random Access Memory), SLDRAM (Synchronous Link Dynamic Random Access Memory), RDRAM (Random Dynamic Random Access Memory), and DRmb DRAM (Dynamic Random Access Memory).
The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (13)
1. A method for generating a chip design file is characterized by comprising the following steps:
obtaining at least one pin description file of a chip; wherein the pin description file comprises description information for describing one or more pins of the chip;
generating an RTL code and a verification code of the chip according to the description information;
outputting a chip design file; wherein the chip design file comprises the RTL code and the verification code.
2. The method of claim 1, wherein the description information comprises pin function description information, register description information, and IO connection description information.
3. The method of claim 2, wherein the pin function description information comprises function information and DFT information.
4. The method of claim 2, wherein the generating the RTL code and the verification code of the chip according to the description information comprises:
generating an RTL code of the soft IP according to the pin function description information and the register description information;
generating RTL codes of the hard IP according to the IO connection description information and the register description information;
and generating the verification code according to the pin function description information, the register description information and the IO connection description information.
5. The method of claim 2, further comprising:
detecting whether the pin function description information has multiplexing function conflict or not;
if the multiplexing function conflict exists, generating a function description error report prompt;
and if no multiplexing function conflict exists, executing the step to generate an RTL code and a verification code of the chip according to the description information.
6. The method of claim 2, further comprising:
detecting whether the IO connection description information has connection conflict or not;
if the connection conflict exists, generating an IO connection error report prompt;
and if the connection conflict does not exist, generating an RTL code and a verification code of the chip according to the description information.
7. The method according to any one of claims 1 to 6, wherein the at least one pin description file comprises a first description file and a second description file, wherein the first description file is associated with the second description file at least by a description of a first pin, the first pin being one of the pins of the chip, the method further comprising:
identifying the change content of the first description information of the first pin by the first description file;
and correspondingly modifying the second description file according to the change content.
8. The method of claim 7, wherein modifying the second description file according to the modification content comprises:
modifying second description information of the second description file on the first pin according to the change content;
modifying third description information of the second pin by the second description file; wherein the second pin is another pin of the chip associated with the first pin.
9. A method of chip design, comprising:
obtaining a chip design file; the chip design file is obtained according to the chip design file generation method of any one of claims 1 to 8;
instantiating the chip according to the RTL code in the chip design file;
and verifying the chip according to the verification code in the chip design file.
10. A chip design file generating apparatus, comprising:
the file acquisition module is used for acquiring at least one pin description file of the chip; wherein the pin description file comprises description information for describing one or more pins of the chip;
the code generation module is used for generating an RTL code and a verification code of the chip according to the description information;
the design file output module is used for outputting a chip design file; wherein the chip design file comprises the RTL code and the verification code.
11. A chip design apparatus, comprising:
the design file acquisition module is used for acquiring a chip design file; the chip design file is generated by the chip design file generating apparatus of claim 10;
the chip instantiation module is used for instantiating the chip according to the RTL code in the chip design file;
and the verification module is used for verifying the chip according to the verification code in the chip design file.
12. A computer device comprising a memory and a processor, the memory having stored thereon a computer program, wherein the computer program, when executed by the processor, causes the processor to perform the steps of the method according to any of claims 1 to 9.
13. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 9.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114997241A (en) * | 2022-06-29 | 2022-09-02 | 苏州浪潮智能科技有限公司 | Pin inspection method, pin inspection device, computer equipment and storage medium |
| CN116225396A (en) * | 2022-12-23 | 2023-06-06 | 中山市科卓尔电器有限公司 | Design method of MCU singlechip functional port |
| CN116700688A (en) * | 2023-06-06 | 2023-09-05 | 无锡摩芯半导体有限公司 | Pinmux verification code rapid generation method based on python implementation |
| CN117056897A (en) * | 2023-10-13 | 2023-11-14 | 沐曦集成电路(上海)有限公司 | Configuration information processing method for chip verification, electronic device and medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114997241A (en) * | 2022-06-29 | 2022-09-02 | 苏州浪潮智能科技有限公司 | Pin inspection method, pin inspection device, computer equipment and storage medium |
| CN114997241B (en) * | 2022-06-29 | 2024-01-26 | 苏州浪潮智能科技有限公司 | Pin inspection method, pin inspection device, computer equipment and storage medium |
| CN116225396A (en) * | 2022-12-23 | 2023-06-06 | 中山市科卓尔电器有限公司 | Design method of MCU singlechip functional port |
| CN116225396B (en) * | 2022-12-23 | 2024-05-17 | 中山市科卓尔电器有限公司 | Design method of MCU singlechip functional port |
| CN116700688A (en) * | 2023-06-06 | 2023-09-05 | 无锡摩芯半导体有限公司 | Pinmux verification code rapid generation method based on python implementation |
| CN117056897A (en) * | 2023-10-13 | 2023-11-14 | 沐曦集成电路(上海)有限公司 | Configuration information processing method for chip verification, electronic device and medium |
| CN117056897B (en) * | 2023-10-13 | 2023-12-26 | 沐曦集成电路(上海)有限公司 | Configuration information processing method for chip verification, electronic device and medium |
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