CN117056897B - Configuration information processing method for chip verification, electronic device and medium - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
- G06F21/44—Program or device authentication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention relates to the field of chip technologies, and in particular, to a method for processing configuration information for chip verification, an electronic device, and a medium, where the method includes: step S1, in the chip initialization stage, acquiring default shared configuration information and chip initialization configuration information; s2, converting into a UVM format; s3, acquiring a test description file; s4, determining default shared configuration information as chip verification configuration information corresponding to the first test case; and modifying default shared configuration information based on personalized configuration parameters corresponding to the second test cases and/or generating personalized configuration information based on a preset normalized configuration information structure, converting the personalized configuration information into a UVM format, and modifying and conforming conflict information in the modified default shared configuration information and/or the generated personalized configuration information with chip initialization configuration information to obtain chip verification configuration information corresponding to each second test case. The invention improves the processing efficiency of the configuration information of chip verification.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a method for processing configuration information for chip verification, an electronic device, and a medium.
Background
In the chip verification process, various verifications aiming at different chip functions are involved, such as verification of chip power consumption, verification of chip initialization, verification of chip security, verification of chip core access and the like. Different verifications are usually implemented by different verification engineers, and different configuration information is set by the different verification engineers according to different verifications, when different functions need to be verified together, different configuration information is likely to be set for the same content, and a situation that configuration information conflicts occurs is likely to occur, so that joint verification of different functions cannot be implemented. In addition, the chip scale is huge, a large amount of configuration information needs to be set, and each verification engineer can set and maintain the configuration information respectively, so that the processing efficiency of the configuration information is greatly reduced. Therefore, how to realize unified management and maintenance of the chip verification configuration information and improve the processing efficiency of the chip verification configuration information is a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a configuration information processing method, electronic equipment and medium for chip verification, which can realize unified management and maintenance of the configuration information for chip verification and improve the processing efficiency of the configuration information for chip verification.
According to a first aspect of the present invention, there is provided a configuration information processing method for chip authentication, comprising:
step S1, in a chip initialization stage, acquiring default shared configuration information and chip initialization configuration information, wherein the default shared configuration information is generated based on a preset normalized configuration information structure, and the default shared configuration information and the chip initialization configuration information are generated based on a high-level language;
s2, converting the default shared configuration information and the chip initialization configuration information into a UVM format;
s3, acquiring a test description file, wherein the test description file comprises M 1 First test case and M 2 A second test case, wherein the second test case comprises corresponding personalized configuration parameters M 1 >M 2 ；
S4, determining the default shared configuration information as chip verification configuration information corresponding to each first test case; and modifying default shared configuration information based on personalized configuration parameters corresponding to each second test case and/or generating personalized configuration information based on a preset normalized configuration information structure, converting the personalized configuration information into a UVM format, and if the modified default shared configuration information and/or the generated personalized configuration information conflicts with chip initialization configuration information, modifying and conforming conflict information in the modified default shared configuration information and/or the generated personalized configuration information with the chip initialization configuration information to obtain chip verification configuration information corresponding to each second test case.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium having computer instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the configuration information processing method, the electronic equipment and the medium for chip verification can achieve quite technical progress and practicality, have wide industrial utilization value, and have at least the following beneficial effects:
the invention generates the configuration information through normalizing the configuration information structure, realizes unified management and maintenance of the chip verification configuration information, can directly apply the chip initialization configuration information to the chip verification stage, and improves the processing efficiency of the chip verification configuration information.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a configuration information processing method for chip verification according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a configuration information processing method for chip verification, as shown in fig. 1, comprising the following steps:
step S1, in the chip initialization stage, default shared configuration information and chip initialization configuration information are obtained, wherein the default shared configuration information is generated based on a preset normalized configuration information structure, and the default shared configuration information and the chip initialization configuration information are generated based on a high-level language.
It should be noted that, the operations of generating the personalized configuration information and modifying the default shared configuration information must be performed in the chip initialization stage, if the operations of generating the personalized configuration information and modifying the default shared configuration information are not performed in the chip initialization stage, and if the instructions of performing the operations of generating the personalized configuration information and modifying the default shared configuration information are not initiated in the chip initialization stage, the operations of generating the personalized configuration information and modifying the default shared configuration information are rejected, and the prompt information may be generated. In addition, when the default information does not accord with the normalized configuration information structure, the configuration information cannot be changed, and prompt information can be generated at the same time.
In addition, the chip initialization configuration information is a chip power-on initialization fuse file, in the prior art, before chip streaming, the chip power-on initialization fuse file cannot be directly used, chip initialization can be performed based on the chip power-on initialization fuse file only after chip streaming, and the fuse is a section of logic in the chip and is stored in a Static Random-Access Memory (SRAM) of the chip in a key value pair form. In the prior art, some simulation initialization information needs to be additionally set to verify chip initialization, and the accuracy and the reliability are low. The chip initialization configuration information can be directly applied to the chip verification configuration information, and the accuracy and the reliability of chip initialization verification are improved.
And S2, converting the default shared configuration information and the chip initialization configuration information into a general verification methodology (Universal Verification Methodology, simply referred to as UVM) format.
It should be noted that, the scalability of UVM is poor, and there is no hierarchical concept, so it is convenient to directly generate the shared configuration information and the chip initialization configuration information based on UVM, and the use of the configuration information in the chip verification stage needs to be in UVM format, so the default shared configuration information and the chip initialization configuration information are generated based on a high-level language, and then further converted into UVM format for chip verification. The existing mode of converting the high-level language into the UVM format falls within the protection scope of the present invention, and is not described herein.
S3, acquiring a test description file, wherein the test description file comprises M 1 First test case and M 2 A second test case, wherein the second test case comprises corresponding personalized configuration parameters M 1 >M 2 。
The test description file may be a json file. It should be noted that, in general, most test cases can realize chip verification directly based on default shared configuration information, and only a small number of test cases need individualized configuration information, for example, 100 test cases in a test description file are included, and the default shared configuration information is set, so that the default shared configuration information can be directly used for 80 first test cases, and corresponding individualized configuration parameters are independently generated for 20 second test cases, thereby improving the processing efficiency of the configuration information.
S4, determining the default shared configuration information as chip verification configuration information corresponding to each first test case; and modifying default shared configuration information based on personalized configuration parameters corresponding to each second test case and/or generating personalized configuration information based on a preset normalized configuration information structure, converting the personalized configuration information into a UVM format, and if the modified default shared configuration information and/or the generated personalized configuration information conflicts with chip initialization configuration information, modifying and conforming conflict information in the modified default shared configuration information and/or the generated personalized configuration information with the chip initialization configuration information to obtain chip verification configuration information corresponding to each second test case.
After the step S4, a step S5 may be further included of storing the chip verification configuration information corresponding to all the second test cases into a shared database, and the corresponding chip verification configuration information may be directly obtained from the shared database by other subsequent second test cases, so as to further improve the processing efficiency of the chip verification configuration information.
As an example, the preset normalized configuration information structure includes a key (key) data segment and a value (value) data segment, and the key data segment includes a first data segment, a second data segment, a third data segment, a fourth data segment, and a fifth data segment. The first data segment is used for setting configuration identifiers, and the configuration identifiers are used for identifying the information as configuration information. The second data segment is used for setting a chip identifier or a system identifier, and when the second data segment is the chip identifier, the piece of configuration information is the configuration information corresponding to the chip identifier. When the second data segment is a system identifier, the configuration information is configuration information corresponding to the system, for example, a chip identifier is GPU (Graphics Processing Unit) chip identifier, and a corresponding system identifier is CPU (Central Processing Unit) identifier. The third data segment is used for setting a physical identifier or a virtual identifier, when the third data segment is the physical identifier, the piece of configuration information is the configuration information under the physical function, and when the third data segment is the virtual identifier, the piece of configuration information is the configuration information under the virtual function. The fourth data segment is used to set a memory (memory), register (register) or bell type (doorbell) identification. The fifth data segment is used for setting a base address or a size identifier. When the second data segment is the system identification, the key data segment does not have a corresponding third data segment.
For example, the configuration information "mx.conig.g.0.phy.memory.bottom 0x4000,0000" where mx.conig.g.0.phy.memory.bottom is a key data segment and 0x4000,0000 is a value data segment. The mx.config is a configuration identification set for the first data segment. G.0 is the chip identifier set for the second data segment, phy is the physical identifier set for the third data segment, memory is the memory set for the fourth data segment, and bottom is the base address set for the fifth data segment. 0x4000,0000 is the value of the base address of the memory of gpu.o under physical function. And further, the configuration information of "mx.config.global.memory.bottom 0xc000,0000" is shown, where mx.config.global.memory.bottom is a key data segment and 0xc000,0000 is a value data segment. Mx.config is the configuration identifier set for the first data segment, global is the second data segment for setting the global system identifier, memory is the memory set for the fourth data segment, and bottom is the base address set for the fifth data segment.
As an example, the chip identity includes { G } 0 ,G 1 ,G 2 ,…,G n ,…G N },G 0 G is the default chip identification n For the N-th switchable chip identifier, the value range of N is 1 to N, N is the number of the switchable chips, it can be understood that only G is turned on by default 0 When there is a multi-chip operation requirement, from { G 1 ,G 2 ,…,G n ,…G N At least one of the two is selected to be started, so that the multi-chip operation is realized. The chip identifiers of the second data segment in the default shared configuration information are G 0 The third data segments are all set as physical identifiers; the chip identification of the second data segment in the personalized configuration information is { G } 1 ,…,G n ,…G N One of the }.
As an example, the step S1 includes, before:
step S10, obtaining G 0 Memory attribute information, register attribute information and doorbell attribute information in corresponding physical function modes, and acquiring system memory attribute information, wherein the attribute information comprises a base address and a size.
Step S20, based on G 0 Memory attribute information, register attribute information and doorbell attribute information under corresponding physical function modes are generated according to a preset normalized configuration information structure to generate G 0 Corresponding physical configuration information; and generating configuration information corresponding to the system memory according to a preset normalized configuration information structure based on the attribute information of the system memory.
Step S30, G 0 And determining the corresponding physical configuration information and the configuration information corresponding to the system memory as the default shared configuration information, and storing the default shared configuration information in a preset first shared folder.
It can be understood that all test cases requiring the default shared configuration information can be directly obtained from the preset first shared folder.
As an example, the personalized configuration parameters include: virtual function enable instructions and/or multi-chip enable instructions and/or default shared configuration information modification instructions; the multi-chip enable instruction includes at least one G n Identification; the default shared configuration information modification instruction includes a target key and a target value.
As an example, if the personalized configuration parameter includes a default shared configuration information modification instruction, the step S4 includes:
step S41, judging whether a target key exists in the chip initialization configuration information, if not, directly executing step S42, if so, judging whether the target value is equal to an initial value corresponding to the target key in the chip initialization configuration information, if so, executing step S42, and if not, enabling the target value to be equal to the initial value corresponding to the target key, and executing step S42.
And S42, modifying the default value corresponding to the target key in the default sharing configuration information into a target value.
It should be noted that, the chip initialization configuration information is set to be finer-grained information, for example, the value of each domain segment of a certain register, and the chip initialization configuration information has the highest priority and is standard information, so when information conflict occurs, the chip initialization configuration information is used as the standard, and the smooth progress of the chip verification process is ensured.
As an example, if the personalized configuration parameter includes a virtual function enabling instruction, the step S4 includes:
step S401, acquiring G 0 Memory attribute information, register attribute information and doorbell attribute information in a corresponding virtual function mode, wherein the attribute information comprises a base address and a size.
Step S402, based on G 0 The corresponding memory attribute information, register attribute information and doorbell attribute information under the virtual function mode are generated according to a preset normalized configuration information structure to generate G 0 Corresponding virtual configuration information.
Step S403, G 0 The corresponding virtual configuration information is stored in a preset second shared folder.
As an example, if the personalized configuration parameter includes a multichip enabled instruction, the step S4 includes:
step S411, obtaining a target G corresponding to the multi-chip enabling instruction n If the personalized configuration parameters also include a virtual function enabling instruction, step S412 is executed, otherwise step S413 is executed.
Step S412, based on target G n Memory attribute information, register attribute information and doorbell attribute information under corresponding virtual function modes are generated according to a preset normalized configuration information structure to generate a target G n Corresponding virtual configuration information, target G n The corresponding virtual configuration information is stored in a preset second shared folder and/or a preset third shared folder.
Step S413, based on target G n Memory attribute information and register attributes in corresponding physical function modeGenerating a target G according to the property information and doorbell attribute information and a preset normalized configuration information structure n Corresponding physical configuration information, target G n The corresponding physical configuration information is stored in a preset third shared folder.
It should be noted that, the second shared folder is used for storing the configuration information corresponding to the virtual function, and the third shared folder is used for storing the configuration information in the multi-chip scene, and the target G n The corresponding virtual configuration information belongs to the configuration information corresponding to the virtual function and the configuration information under the multi-chip scene, so that one of the second shared folder and the third shared folder can be selected for storage, and the second shared folder and the third shared folder can be selected for storage at the same time. Therefore, the configuration information classified and classified scene of the chip verification can be stored through the first shared folder, the second shared folder and the third shared folder, and the subsequent use of the configuration information is facilitated.
The embodiment of the invention generates the configuration information by normalizing the configuration information structure, realizes unified management and maintenance of the chip verification configuration information, can directly apply the chip initialization configuration information to the chip verification stage, and improves the processing efficiency of the chip verification configuration information.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, and the computer instructions are used for executing the method of the embodiment of the invention.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (10)
1. A configuration information processing method for chip authentication, comprising:
step S1, in a chip initialization stage, acquiring default shared configuration information and chip initialization configuration information, wherein the default shared configuration information is generated based on a preset normalized configuration information structure, and the default shared configuration information and the chip initialization configuration information are generated based on a high-level language;
s2, converting the default shared configuration information and the chip initialization configuration information into a UVM format;
s3, acquiring a test description file, wherein the test description file comprises M 1 First test case and M 2 A second test case, wherein the second test case comprises corresponding personalized configuration parameters M 1 >M 2 ；
S4, determining the default shared configuration information as chip verification configuration information corresponding to each first test case; and modifying default shared configuration information based on personalized configuration parameters corresponding to each second test case and/or generating personalized configuration information based on a preset normalized configuration information structure, converting the personalized configuration information into a UVM format, and if the modified default shared configuration information and/or the generated personalized configuration information conflicts with chip initialization configuration information, modifying and conforming conflict information in the modified default shared configuration information and/or the generated personalized configuration information with the chip initialization configuration information to obtain chip verification configuration information corresponding to each second test case.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the preset normalized configuration information structure comprises a key data segment and a value data segment, wherein the key data segment comprises a first data segment, a second data segment, a third data segment, a fourth data segment and a fifth data segment, the first data segment is used for setting a configuration identifier, the second data segment is used for setting a chip identifier or a system identifier, the third data segment is used for setting a physical identifier or a virtual identifier, the fourth data segment is used for setting a memory, a register or a bell type identifier, the fifth data segment is used for setting a base address or a size identifier, and when the second data segment is a system identifier, the key data segment does not have the corresponding third data segment.
3. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the chip identification includes { G } 0 ,G 1 ,G 2 ,…,G n ,…G N },G 0 G is the default chip identification n The value range of N is 1 to N, and N is the number of the switchable chips; the chip identifiers of the second data segment in the default shared configuration information are G 0 The third data segments are all set as physical identifiers; the chip identification of the second data segment in the personalized configuration information is { G } 1 ,…,G n ,…G N One of the }.
4. The method of claim 3, wherein the step of,
the step S1 is preceded by:
step S10, obtaining G 0 Memory attribute messages in corresponding physical function modesInformation, register attribute information, doorbell attribute information, and system memory attribute information, wherein the attribute information comprises a base address and a size;
step S20, based on G 0 Memory attribute information, register attribute information and doorbell attribute information under corresponding physical function modes are generated according to a preset normalized configuration information structure to generate G 0 Corresponding physical configuration information; generating configuration information corresponding to the system memory according to a preset normalized configuration information structure based on the attribute information of the system memory;
step S30, G 0 And determining the corresponding physical configuration information and the configuration information corresponding to the system memory as the default shared configuration information, and storing the default shared configuration information in a preset first shared folder.
5. The method of claim 3, wherein the step of,
the personalized configuration parameters include: virtual function enable instructions and/or multi-chip enable instructions and/or default shared configuration information modification instructions; the multi-chip enable instruction includes at least one G n Identification; the default shared configuration information modification instruction includes a target key and a target value.
6. The method of claim 5, wherein the step of determining the position of the probe is performed,
if the personalized configuration parameter includes a default shared configuration information modification instruction, the step S4 includes:
step S41, judging whether a target key exists in the chip initialization configuration information, if not, directly executing step S42, if so, judging whether the target value is equal to an initial value corresponding to the target key in the chip initialization configuration information, if so, executing step S42, and if not, enabling the target value to be equal to the initial value corresponding to the target key, and executing step S42;
and S42, modifying the default value corresponding to the target key in the default sharing configuration information into a target value.
7. The method of claim 5, wherein the step of determining the position of the probe is performed,
if the personalized configuration parameters include virtual function enabling instructions, the step S4 includes:
step S401, acquiring G 0 Memory attribute information, register attribute information and doorbell attribute information under a corresponding virtual function mode, wherein the attribute information comprises a base address and a size;
step S402, based on G 0 The corresponding memory attribute information, register attribute information and doorbell attribute information under the virtual function mode are generated according to a preset normalized configuration information structure to generate G 0 Corresponding virtual configuration information;
step S403, G 0 The corresponding virtual configuration information is stored in a preset second shared folder.
8. The method of claim 7, wherein the step of determining the position of the probe is performed,
if the personalized configuration parameter includes a multi-chip enabling instruction, the step S4 includes:
step S411, obtaining a target G corresponding to the multi-chip enabling instruction n If the personalized configuration parameters simultaneously include a virtual function enabling instruction, executing step S412, otherwise, executing step S413;
step S412, based on target G n Memory attribute information, register attribute information and doorbell attribute information under corresponding virtual function modes are generated according to a preset normalized configuration information structure to generate a target G n Corresponding virtual configuration information, target G n The corresponding virtual configuration information is stored in a preset second shared folder and/or a preset third shared folder;
step S413, based on target G n Memory attribute information, register attribute information and doorbell attribute information under corresponding physical function modes are generated according to a preset normalized configuration information structure to generate a target G n Corresponding physical configuration information, target G n The corresponding physical configuration information is stored in the preset firstThree shared folders.
9. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-8.
10. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-8.
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Citations (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5684742A (en) * | 1995-09-20 | 1997-11-04 | International Business Machines Corporation | Device and method for the simplified generation of tools for the initialization and personalization of and communication with a chip card |
| US7137087B1 (en) * | 2003-08-20 | 2006-11-14 | Adaptec, Inc. | Integrated circuit verification scheme |
| US7917873B1 (en) * | 2007-02-12 | 2011-03-29 | Zocalo Tech, Inc. | System and method for verification of integrated circuit design |
| WO2011157119A1 (en) * | 2010-06-13 | 2011-12-22 | 华为技术有限公司 | Auto-configuration method and device for registers of chip |
| CN103178996A (en) * | 2013-03-15 | 2013-06-26 | 烽火通信科技股份有限公司 | Distributed packet-switching chip model verification system and method |
| WO2016197768A1 (en) * | 2016-01-04 | 2016-12-15 | 中兴通讯股份有限公司 | Chip verification method, device, and system |
| WO2021093654A1 (en) * | 2019-11-15 | 2021-05-20 | 中兴通讯股份有限公司 | Daughter card initialization method, electronic apparatus, and storage medium |
| CN113032195A (en) * | 2021-03-24 | 2021-06-25 | 上海西井信息科技有限公司 | Chip simulation verification method, system, equipment and storage medium |
| CN113485882A (en) * | 2021-07-21 | 2021-10-08 | 鹏城实验室 | Chip verification method and device and computer readable storage medium |
| WO2021238006A1 (en) * | 2020-05-29 | 2021-12-02 | 上海商汤智能科技有限公司 | Artificial intelligence chip verification |
| CN113835945A (en) * | 2021-09-29 | 2021-12-24 | 深圳大普微电子科技有限公司 | Chip testing method, device, equipment and system |
| CN114327476A (en) * | 2021-12-24 | 2022-04-12 | Oppo广东移动通信有限公司 | Chip design file generation method and device and chip design method and device |
| CN114429103A (en) * | 2022-01-14 | 2022-05-03 | 山东云海国创云计算装备产业创新中心有限公司 | Chip verification method and device, electronic equipment and storage medium |
| CN114900367A (en) * | 2022-05-25 | 2022-08-12 | 东南大学 | Sharing strategy verification and conflict detection method based on priority dynamic adjustment |
| CN115203067A (en) * | 2022-07-13 | 2022-10-18 | 联宝(合肥)电子科技有限公司 | Memory initialization method and device, electronic equipment and computer readable storage medium |
| CN115470062A (en) * | 2022-10-18 | 2022-12-13 | 山东云海国创云计算装备产业创新中心有限公司 | Method, system, storage medium and equipment for checking configuration of BMC display chip |
| CN115904517A (en) * | 2022-12-19 | 2023-04-04 | 西安易朴通讯技术有限公司 | Processing method and device for configuration file of expander chip and disk array system |
| CN115983173A (en) * | 2023-03-21 | 2023-04-18 | 湖北芯擎科技有限公司 | Register model generation method and device, computer equipment and storage medium |
| CN116203400A (en) * | 2023-04-27 | 2023-06-02 | 湖南大学 | Test method and system based on chip initialization |
| CN116483644A (en) * | 2023-06-25 | 2023-07-25 | 北京云枢创新软件技术有限公司 | Log search method for chip verification test regression, electronic equipment and medium |
| CN116562225A (en) * | 2023-05-08 | 2023-08-08 | 北京晟芯网络科技有限公司 | Chip verification platform, method and device |
| CN116578352A (en) * | 2023-07-11 | 2023-08-11 | 沐曦集成电路(上海)有限公司 | Chip initializing system |
| CN116719581A (en) * | 2023-07-11 | 2023-09-08 | 沐曦集成电路(上海)有限公司 | Chip multi-instance module initializing system |
| CN116719729A (en) * | 2023-06-12 | 2023-09-08 | 南京金阵微电子技术有限公司 | Universal verification platform, universal verification method, medium and electronic equipment |
| CN116738901A (en) * | 2023-06-09 | 2023-09-12 | 新华三半导体技术有限公司 | Chip verification method and device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7146302B2 (en) * | 2003-04-28 | 2006-12-05 | International Business Machines Corporation | Method, system and program product that utilize a configuration database to configure a hardware digital system having an arbitrary system size and component set |
| US7757073B2 (en) * | 2006-10-25 | 2010-07-13 | Nvidia Corporation | System configuration data sharing between multiple integrated circuits |
| US8954721B2 (en) * | 2011-12-08 | 2015-02-10 | International Business Machines Corporation | Multi-chip initialization using a parallel firmware boot process |
| EP2720167A1 (en) * | 2012-10-11 | 2014-04-16 | Nagravision S.A. | Method and system for smart card chip personalization |
| CN114624575A (en) * | 2022-03-01 | 2022-06-14 | 长鑫存储技术有限公司 | Chip testing method, device, equipment and storage medium |
-
2023
- 2023-10-13 CN CN202311325625.0A patent/CN117056897B/en active Active
Patent Citations (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5684742A (en) * | 1995-09-20 | 1997-11-04 | International Business Machines Corporation | Device and method for the simplified generation of tools for the initialization and personalization of and communication with a chip card |
| US7137087B1 (en) * | 2003-08-20 | 2006-11-14 | Adaptec, Inc. | Integrated circuit verification scheme |
| US7917873B1 (en) * | 2007-02-12 | 2011-03-29 | Zocalo Tech, Inc. | System and method for verification of integrated circuit design |
| WO2011157119A1 (en) * | 2010-06-13 | 2011-12-22 | 华为技术有限公司 | Auto-configuration method and device for registers of chip |
| CN103178996A (en) * | 2013-03-15 | 2013-06-26 | 烽火通信科技股份有限公司 | Distributed packet-switching chip model verification system and method |
| WO2016197768A1 (en) * | 2016-01-04 | 2016-12-15 | 中兴通讯股份有限公司 | Chip verification method, device, and system |
| WO2021093654A1 (en) * | 2019-11-15 | 2021-05-20 | 中兴通讯股份有限公司 | Daughter card initialization method, electronic apparatus, and storage medium |
| WO2021238006A1 (en) * | 2020-05-29 | 2021-12-02 | 上海商汤智能科技有限公司 | Artificial intelligence chip verification |
| CN113032195A (en) * | 2021-03-24 | 2021-06-25 | 上海西井信息科技有限公司 | Chip simulation verification method, system, equipment and storage medium |
| CN113485882A (en) * | 2021-07-21 | 2021-10-08 | 鹏城实验室 | Chip verification method and device and computer readable storage medium |
| CN113835945A (en) * | 2021-09-29 | 2021-12-24 | 深圳大普微电子科技有限公司 | Chip testing method, device, equipment and system |
| CN114327476A (en) * | 2021-12-24 | 2022-04-12 | Oppo广东移动通信有限公司 | Chip design file generation method and device and chip design method and device |
| CN114429103A (en) * | 2022-01-14 | 2022-05-03 | 山东云海国创云计算装备产业创新中心有限公司 | Chip verification method and device, electronic equipment and storage medium |
| CN114900367A (en) * | 2022-05-25 | 2022-08-12 | 东南大学 | Sharing strategy verification and conflict detection method based on priority dynamic adjustment |
| CN115203067A (en) * | 2022-07-13 | 2022-10-18 | 联宝(合肥)电子科技有限公司 | Memory initialization method and device, electronic equipment and computer readable storage medium |
| CN115470062A (en) * | 2022-10-18 | 2022-12-13 | 山东云海国创云计算装备产业创新中心有限公司 | Method, system, storage medium and equipment for checking configuration of BMC display chip |
| CN115904517A (en) * | 2022-12-19 | 2023-04-04 | 西安易朴通讯技术有限公司 | Processing method and device for configuration file of expander chip and disk array system |
| CN115983173A (en) * | 2023-03-21 | 2023-04-18 | 湖北芯擎科技有限公司 | Register model generation method and device, computer equipment and storage medium |
| CN116203400A (en) * | 2023-04-27 | 2023-06-02 | 湖南大学 | Test method and system based on chip initialization |
| CN116562225A (en) * | 2023-05-08 | 2023-08-08 | 北京晟芯网络科技有限公司 | Chip verification platform, method and device |
| CN116738901A (en) * | 2023-06-09 | 2023-09-12 | 新华三半导体技术有限公司 | Chip verification method and device |
| CN116719729A (en) * | 2023-06-12 | 2023-09-08 | 南京金阵微电子技术有限公司 | Universal verification platform, universal verification method, medium and electronic equipment |
| CN116483644A (en) * | 2023-06-25 | 2023-07-25 | 北京云枢创新软件技术有限公司 | Log search method for chip verification test regression, electronic equipment and medium |
| CN116578352A (en) * | 2023-07-11 | 2023-08-11 | 沐曦集成电路(上海)有限公司 | Chip initializing system |
| CN116719581A (en) * | 2023-07-11 | 2023-09-08 | 沐曦集成电路(上海)有限公司 | Chip multi-instance module initializing system |
Non-Patent Citations (2)
| Title |
|---|
| 基于Leon2的安全应用配置方案及验证;郑欢;;计算机仿真(05);全文 * |
| 基于PowerPC芯片与天脉系统的地址空间分配开发研究;吴云;薛一哲;陈宁;徐宁;;航空计算技术(01);全文 * |
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