CN103178996A - Distributed packet-switching chip model verification system and method - Google Patents
Distributed packet-switching chip model verification system and method Download PDFInfo
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Abstract
The invention discloses distributed packet-switching chip model verification system and method and relates to the field of designing packet processing chips. The system comprises a core control module, a command line interface module, an SDK (software development kit) proxy interface module, a virtual network test meter module, a virtual chip configuration module and a C model package module. The core control module is a server program module. The command line interface module, the SDK proxy interface module, the virtual network test meter instrument, the virtual chip configuration module and the C model package module are client program modules. The system is a C/S/C (client/server/client) structured distributed system supporting three application scenarios, namely, system function model verification, software-hardware cooperated simulation verification and prototype verification. Modules required for different application scenarios are different. Verification closure time of the functions of the system at different levels can be shortened greatly, development efficiency is increased, and debugging cost is lowered.
Description
Technical field
The present invention relates to the packet processing chip design field, particularly relate to a kind of distributed packet switching chip modelling verification system and verification method.
Background technology
Along with the IP(Internet Protocol of global communication technology, Internet protocol) the change process deepens continuously, and the application demand of packet switching chip is increasing, and the agreement that packet switch is relevant also increases thereupon, thereby makes the exploitation of this type of chip increasingly sophisticated.
In actual chip development process, common chip checking flow process is as follows:
(1) system functional model Qualify Phase: system adopts high-level language (for example C language) to carry out the modeling of systemic-function, namely utilize the method for Procedure modeling first the bag processing capacity of chip to be simulated out, carry out other realization of hardware description language level as benchmark again after test is completed, this process can be referred to as the C model measurement;
(2) circuit simulation Qualify Phase: adopt hardware description language for the C model function of passing through after tested, complete RTL(Register Transport Level Method at Register Transfer Level) modular design, and build simulation test platform and carry out emulation testing;
(3) soft or hard collaborative simulation verification (Co-simulation) stage: will be the code of RTL code by emulation testing and chip drives software combine and carry out emulation testing;
(4) the prototype verification stage: above-mentioned RTL by checking is comprehensively become actual real circuits, adopt specific FPGA(Field-Programmable Gate Array, field programmable gate array) obtain physics realization, and test in prototype verification plate and network test instrument formation prototype verification environment, usually chip development in this stage just with SDK(System Development Kit, system development tool bag) and hardware system together carry out the test of system level.
The method that adopts due to above-mentioned 4 stages is different, generally need to design a cover hardware or software for each stage is independent and realize respectively, and test case can't be multiplexing, causes whole process exception complicated.Each packet switching chip need to be supported thousands of disparate networks agreements, therefore need to do respectively a large amount of tests on different stage could finally complete checking, whole convergence process can occur repeatedly a large amount of, the functional verification of chip to be measured is tediously long at the checking convergence time of different stage, causes development progress to lag behind.
Summary of the invention
The invention provides a kind of distributed packet switching chip modelling verification system and verification method, adopt distributed system architecture to carry out normalized to the proof procedure of different abstraction level, can significantly shorten chip to be measured at the checking convergence time of different stage, improve development efficiency, reduce debugging cost.
distributed packet switching chip modelling verification provided by the invention system, comprise kernel control module, the command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model encapsulation module, wherein, kernel control module belongs to the serve end program module, the command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model encapsulation module belong to client program module, this verification system belongs to the distributed system of client-service end-client C/S/C structure, support simultaneously 3 kinds of application scenarioss: the system functional model checking, the soft or hard collaborative simulation verification, prototype verification, under different application scenarioss, required module is different,
Kernel control module, be used for: the message of transmitting between the command line interface module that management is attached thereto, SDK proxy interface module, virtual network test instrumentation module, complete proprietary message between global configuration file and program module forwarding, copy, broadcast, classify, preserve, add up, the simultaneously connection of maintain message passage;
The command line interface module, be used for: read the global configuration file by customization, start the required program module of current application scene according to the application scenarios configuration parameter that reads, after the connection initialization of C/S/C, personnel provide command line interface for chip development, complete customization and the editor of test case;
SDK proxy interface module is used for: receive the packet switching chip configuration to be measured that kernel control module is sent, call SDK software according to packet switching chip configuration to be measured, the model/prototype that drives packet switching chip to be measured is normally moved;
Virtual network test instrumentation module is used for: network test instrument that is virtually reality like reality, and the packet switching chip test and excitation configuration messages to be measured and the response that forward according to kernel control module check configuration messages, complete transmission, reception, verification and the statistics of packet;
The virtual chip configuration module only is used under system functional model checking application scenarios, is used for preserving, upgrade, inquiring about register configuration and the bag processing protocol list item of packet switching chip to be measured;
C model encapsulation module, be used for: the packet switching chip configuration to be measured of reading the virtual chip configuration module, receive the test and excitation that test module is sent, packet switching chip to be measured configuration and test and excitation are given be encapsulated in its inner packet switching chip model and process, the result after this packet switching chip model processing is sent to test module; C model encapsulation module is only enabled under system functional model checking application scenarios, and the packet switching chip model is connected in this distributed system.
On the basis of technique scheme, described global configuration file comprises application scenarios, types of models, service end process configuration information and some client process configuration informations, application scenarios is set to a kind of in system functional model checking, soft or hard collaborative simulation verification, prototype verification, is used for controlling enabling and operational mode of the different required program modules of application scenarios; Types of models is configured to different identification according to the model of the disparate modules of chip to be measured, only is used under system functional model checking application scenarios the file destination of the C model that C model encapsulation module is corresponding according to the model identification dynamic link; Service end process configuration information comprises IP address, port numbers, process type and device number, the client process configuration information comprises process type and device number, the web socket that IP address and port numbers are used for creating between server module and client program module connects, the message channel of construction procedures intermodule; Process type is configured to different process identification (PID)s, is used for distinguishing different module types; In non-networking test, kernel control module will carry out corresponding operation according to process type; Device number is used for distinguishing the chip to be measured of program module test, and in the networking test, there is unique device number in each chip to be measured, in the networking test, kernel control module will carry out corresponding operation according to device number, process type, and in non-networking test, device number is ignored by system.
On the basis of technique scheme, between described program module, proprietary message comprises 6 message fields: device number, source process type, target process type, coomand mode, message number, message content, wherein, device number is used for distinguishing the chip to be measured of program module test, in the networking test, there is unique device number in each chip to be measured, in the networking test, kernel control module will carry out corresponding operation according to device number, process type, in non-networking test, device number is ignored by system; Source process type and target process type are used for source and the target of a message of expression, and being convenient to kernel control module will forward according to process type, are used for simultaneously and message number together calculates global message number; Coomand mode is used for the basic return state of a message of expression; Message number be used for to be distinguished different message in the same class program module, and kernel control module number operates according to global message; Message content is concrete message content corresponding to each message number.
On the basis of technique scheme, described coomand mode comprises correctly returns to, orders mistake and command timeout three state.
On the basis of technique scheme, described concrete message content comprises sub-message, character string information and protocol massages.
On the basis of technique scheme, the message number of each class method inside modules is independent numbering, for whole distributed system, and the overall start message numbering+message number of global message number=target process type.
On the basis of technique scheme, the order of described test case support comprises the stimulation arrangement order of chip configuration order to be measured, virtual network test instrumentation, the debug command that the response expectation checks regular configuration order and this distributed system.
On the basis of technique scheme, described kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model encapsulation module distribution are on same machines or different machines.
On the basis of technique scheme, described kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model encapsulation module distribution are in same operation system or different operating system.
Based on above-mentioned distributed packet switching chip modelling verification system, the embodiment of the present invention also provides a kind of distributed packet switching chip modelling verification method, comprises the following steps:
S1, under system functional model checking scene:
The bag of step 107, C model encapsulation module is processed: the data structure that the various excitation bag data transaction that C model encapsulation device will be received become chip model to be measured to identify, call the function of chip model to be measured, the data structure that meets with a response and wrap, convert the respond packet message format that virtual network test instrumentation module needs to, send to virtual network test instrumentation module;
S2, under soft or hard collaborative simulation verification scene:
The simulation test platform of step 207, RTL emulation: RTL obtains excitation bag data from its DPI interface, is driven on the input interface signal of RTL module, after the RTL resume module is completed, from the output interface signal of RTL module, obtains actual respond packet data;
S3, under the prototype verification scene:
Compared with prior art, advantage of the present invention is as follows:
(1) the present invention is applicable to the whole process of packet switching chip checking, especially front end checking, the effect highly significant, all testing cases can be completed during initial stage system model checking, follow-up soft or hard collaborative simulation stage and prototype verification stage still can be continued to use test case before, in the situation that do not revise original test case, only need to revise a small amount of global configuration parameter, just can realize seamless switching, full automaticly complete all tests, can significantly shorten chip to be measured at the checking convergence time of different stage, improve development efficiency.
(2) the present invention can utilize a plurality of program module parallel runnings that are distributed on different machines, makes whole operational efficiency be improved.
(3) the present invention is in chip development directly is embedded in distributed system with SDK in early days, verify in advance, like this, usually need to wait until that the initial stage that is operated in chip development that can carry out after the prototype verification plate is completed just completes together with other work, and reuse SDK in the prototype verification in later stage, the SDK of this moment has passed through checking, thereby can improve the efficient of system testing in prototype verification, reduces debugging cost.
Often have the networking test of multi-chip in the chip testing of (4) packet switch class, traditional verification system and method are difficult to support usually, and distributed system architecture of the present invention can be supported the networking test of a plurality of chips to be measured easily.
(5) distributed system architecture of the present invention has defined proprietary communication information mechanism, by adding the message conversion program, the message content of native system is converted into the operation that other various software/hardwares systems can the accept (simulator of hardware description language for example, network test instrument command interface), message conversion program and kernel control module can carry out message communicating, thereby complete interconnected.Because there is the socket of oneself in common the 3rd side's system, because this distributed system definition unified message format for communications, so only can complete interconnectedly with completing instruction interface that message to the 3 method, systems can identify, the mode of the processing messages of inside is still constant.If not distributed system architecture, there is no this message mechanism, and interconnected being difficult to of other system complete, the software library that can only provide with other system and native system are compiled in together just can be completed.
Description of drawings
Fig. 1 is the structural representation of distributed packet switching chip modelling verification system in the embodiment of the present invention.
Fig. 2 is the structural representation of system's global configuration in the embodiment of the present invention.
Fig. 3 is the structural representation of inter-process messages in the embodiment of the present invention.
Fig. 4 is the flow chart of system functional model checking in the embodiment of the present invention.
Fig. 5 is the flow chart of soft or hard collaborative simulation verification in the embodiment of the present invention.
Fig. 6 is the flow chart of embodiment of the present invention mesarcs checking.
Embodiment
The present invention is described in further detail below in conjunction with drawings and the specific embodiments.
Shown in Figure 1, the embodiment of the present invention provides a kind of distributed packet switching chip modelling verification system, comprise kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model encapsulation module, wherein, kernel control module belongs to the serve end program module, and command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model encapsulation module belong to client program module.This verification system belongs to C/S/C(Client-Server-Client client-service end-client) distributed system of structure, support simultaneously 3 kinds of application scenarioss: system functional model checking, soft or hard collaborative simulation verification, prototype verification, program module required under different application scenarioss is different.
Kernel control module, the serve end program that belongs to whole distributed system, be used for: the message of transmitting between the command line interface module that management is attached thereto, SDK proxy interface module, virtual network test instrumentation module, complete the proprietary message format (hereinafter will further illustrate) of the embodiment of the present invention forwarding, copy, broadcast, classify, preserve, add up, the simultaneously connection of maintain message passage.
The command line interface module, be used for: read by the proprietary global configuration file of the embodiment of the present invention of customization (hereinafter will further illustrate), start the required program module of current application scene according to the application scenarios configuration parameter that reads, after the connection initialization of C/S/C, personnel provide command line interface for chip development, complete customization and the editor of test case.The order of test case support comprises chip configuration order to be measured, and the stimulation arrangement order of virtual network test instrumentation, response expectation check regular configuration order, and the debug command of this distributed system etc.Test case, the mode that can key on order line is sent into command line interface, can be also that a script file of finishing writing in advance (text that comprises many orders) is sent into command interface, this module sends to kernel control module with the proprietary message format that all orders transform into the embodiment of the present invention, and receiving order operation result message from kernel control module, in extraction message, operation result is presented on order line.In addition, all command interaction records of this module all will be recorded in journal file, convenient debugging and analytical test result.
SDK proxy interface module is used for: receive the packet switching chip configuration to be measured that kernel control module is sent, call SDK software according to packet switching chip configuration to be measured, the model/prototype that drives packet switching chip to be measured is normally moved; Its operational mode can change according to the difference of application scenarios configuration parameter in global configuration.(hereinafter can further illustrate).
Virtual network test instrumentation module is used for: network test instrument that is virtually reality like reality, and the packet switching chip test and excitation configuration messages to be measured and the response that forward according to kernel control module check configuration messages, complete transmission, reception, verification and the statistics of packet; Its operational mode can change according to the difference of application scenarios configuration parameter in global configuration.
The virtual chip configuration module is used for: register configuration and the bag processing protocol list item of preserving, upgrade, inquire about packet switching chip to be measured.The virtual chip configuration module is only enabled under system functional model checking application scenarios, and for soft or hard collaborative simulation verification and these 2 kinds of application scenarioss of prototype verification, the side circuit that the function of this module reaches in FPGA in the RTL module is respectively completed.
C model encapsulation module, be used for: the packet switching chip configuration to be measured of reading the virtual chip configuration module, receive the test and excitation that test module is sent, packet switching chip to be measured configuration and test and excitation are given be encapsulated in its inner packet switching chip model and process, the result after this packet switching chip model processing is sent to test module.In packet switching chip model processing procedure, may revise the packet switching chip configuration to be measured in the virtual chip configuration module.C model encapsulation module is only enabled under system functional model checking application scenarios, make the packet switching chip model can be connected in this distributed system, for soft or hard collaborative simulation verification and these 2 kinds of application scenarioss of prototype verification, the way of realization of packet switching chip to be measured is respectively the side circuit in RTL code and FPGA.
Above-mentioned 6 program modules can run on different machines as process independently, above different operating system, finally consist of whole distributed validation system.
Control for the interconnected and intercommunication of completing whole distributed validation system, the embodiment of the present invention has been formulated proprietary message format between proprietary global configuration file form and program module.
Shown in Figure 2, global configuration file comprises application scenarios, types of models, service end process configuration information and some client process configuration informations, application scenarios is set to a kind of in system functional model checking, soft or hard collaborative simulation verification, prototype verification, is used for controlling enabling and operational mode of required program module in above-mentioned 6 program modules of different application scenarioss; Proof procedure is completing step by step, may be that one by one module to be measured is verified in native system at the beginning, and then module spliced to be measured is connected into is complete chip to be measured, each module/chip correspondence in the system functional model checking becomes a C model, and which model therefore needs to select is.Types of models is configured to different identification according to the model of the disparate modules of chip to be measured, only is used under system functional model checking application scenarios the file destination of the C model that C model encapsulation module is corresponding according to the model identification dynamic link; Service end process configuration information comprises IP address, port numbers, process type and device number, the client process configuration information comprises process type and device number, the web socket (Socket) that IP address and port numbers are used for creating between server module and client program module connects, the message channel of construction procedures intermodule; Process type is configured to different process identification (PID)s, be used for distinguishing above-mentioned 6 kinds of different program module types, here arranging is that each program module that need to start is arranged sign, and which program module could differentiate message be to core controller like this, need to be forwarded to which program module.In non-networking test, kernel control module will carry out corresponding operation according to process type; Device number is used for distinguishing the chip to be measured of program module test, in the networking test, there is unique device number in each chip to be measured, in the networking test, kernel control module will carry out corresponding operation according to device number, process type, in non-networking test, this device number will be ignored by system.
Under different application scenarioss, the program module type that the global configuration item starts is as required inserted above-mentioned configuration one by one, and the relevant configuration of its module type of program module that does not need to start should not inserted (hereinafter further specified).
Shown in Figure 3, between program module, proprietary message comprises 6 message fields: device number, source process type, target process type, coomand mode, message number, message content, wherein, device number is used for distinguishing the chip to be measured of program module test, and in the networking test, there is unique device number in each chip to be measured, in the networking test, kernel control module will carry out corresponding operation according to device number, process type, and in non-networking test, this device number will be ignored by system; Source process type and target process type are used for source and the target of a message of expression, and being convenient to kernel control module will forward according to process type, are used for simultaneously and message number together calculates global message number; Coomand mode is used for the basic return state of a message of expression, comprises correctly and returns to, orders mistake and command timeout three state; Message number is used for distinguishing different message in the same class program module, the message number of each class method inside modules is independent numbering, for whole distributed system, the overall start message numbering+message number of global message number=target process type, kernel control module number operates according to global message; Message content is concrete message content corresponding to each message number, can deposit the data of any byte in theory, concrete message content comprises sub-message (comprising a plurality of parameters such as order), character string information and protocol massages (as all kinds of bag data) etc., according to the function needs of each module and the multiple different messages of processing, the concrete function of concrete message content and chip to be measured is relevant, between the program module in the embodiment of the present invention, proprietary message format as a kind of general message format, goes for various packet switch type chip to be measured.
Based on above-mentioned distributed packet switching chip modelling verification system (comprising global configuration and program module message mechanism), the embodiment of the present invention provides a kind of distributed packet switching chip modelling verification method, can support simultaneously 3 kinds of application scenarioss: system functional model checking, soft or hard collaborative simulation verification, prototype verification, the below is elaborated.
The distributed packet switching chip modelling verification method that the embodiment of the present invention provides comprises the following steps:
S1, shown in Figure 4, under system functional model checking scene:
The bag of step 107, C model encapsulation module is processed: the data structure that the various excitation bag data transaction that C model encapsulation device will be received become chip model to be measured to identify, call the function of chip model to be measured, the data structure that meets with a response and wrap, convert the respond packet message format that virtual network test instrumentation module needs to, send to virtual network test instrumentation module;
S2, shown in Figure 5, under soft or hard collaborative simulation verification scene:
Global configuration contrast under global configuration under soft or hard collaborative simulation verification scene and system functional model checking scene, difference is application scenarios is changed to the soft or hard collaborative simulation verification, remove process identification (PID) and the device number of virtual chip configuration module and C model encapsulation module, all the other initialization operations are verified under scene consistent with system functional model;
The simulation test platform of step 207, RTL emulation: RTL has obtained excitation bag data from its DPI interface, be driven on the input interface signal of RTL module, after the RTL resume module is completed, from the output interface signal of RTL module, obtain actual respond packet data;
S3, shown in Figure 6, under the prototype verification scene:
Global configuration under global configuration under the prototype verification scene and soft or hard collaborative simulation verification scene is basically identical, difference is that with the application scenarios configuration change be prototype verification, simultaneously SDK proxy interface module must be configured in the embedded system of prototype verification plate and start, and the enable position of all the other modules is not done restriction;
Those skilled in the art can carry out various modifications and variations to the embodiment of the present invention, if these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, these modifications and modification are also within protection scope of the present invention.
The prior art that the content of not describing in detail in specification is known to the skilled person.
Claims (10)
1. distributed packet switching chip modelling verification system, it is characterized in that: comprise kernel control module, the command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model encapsulation module, wherein, kernel control module belongs to the serve end program module, the command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model encapsulation module belong to client program module, this verification system belongs to the distributed system of client-service end-client C/S/C structure, support simultaneously 3 kinds of application scenarioss: the system functional model checking, the soft or hard collaborative simulation verification, prototype verification, under different application scenarioss, required module is different,
Kernel control module, be used for: the message of transmitting between the command line interface module that management is attached thereto, SDK proxy interface module, virtual network test instrumentation module, complete proprietary message between global configuration file and program module forwarding, copy, broadcast, classify, preserve, add up, the simultaneously connection of maintain message passage;
The command line interface module, be used for: read the global configuration file by customization, start the required program module of current application scene according to the application scenarios configuration parameter that reads, after the connection initialization of C/S/C, personnel provide command line interface for chip development, complete customization and the editor of test case;
SDK proxy interface module is used for: receive the packet switching chip configuration to be measured that kernel control module is sent, call SDK software according to packet switching chip configuration to be measured, the model/prototype that drives packet switching chip to be measured is normally moved;
Virtual network test instrumentation module is used for: network test instrument that is virtually reality like reality, and the packet switching chip test and excitation configuration messages to be measured and the response that forward according to kernel control module check configuration messages, complete transmission, reception, verification and the statistics of packet;
The virtual chip configuration module only is used under system functional model checking application scenarios, is used for preserving, upgrade, inquiring about register configuration and the bag processing protocol list item of packet switching chip to be measured;
C model encapsulation module, be used for: the packet switching chip configuration to be measured of reading the virtual chip configuration module, receive the test and excitation that test module is sent, packet switching chip to be measured configuration and test and excitation are given be encapsulated in its inner packet switching chip model and process, the result after this packet switching chip model processing is sent to test module; C model encapsulation module is only enabled under system functional model checking application scenarios, and the packet switching chip model is connected in this distributed system.
2. distributed packet switching chip modelling verification as claimed in claim 1 system, it is characterized in that: described global configuration file comprises application scenarios, types of models, service end process configuration information and some client process configuration informations, application scenarios is set to a kind of in system functional model checking, soft or hard collaborative simulation verification, prototype verification, is used for controlling enabling and operational mode of the different required program modules of application scenarios; Types of models is configured to different identification according to the model of the disparate modules of chip to be measured, only is used under system functional model checking application scenarios the file destination of the C model that C model encapsulation module is corresponding according to the model identification dynamic link; Service end process configuration information comprises IP address, port numbers, process type and device number, the client process configuration information comprises process type and device number, the web socket that IP address and port numbers are used for creating between server module and client program module connects, the message channel of construction procedures intermodule; Process type is configured to different process identification (PID)s, is used for distinguishing different module types; In non-networking test, kernel control module will carry out corresponding operation according to process type; Device number is used for distinguishing the chip to be measured of program module test, and in the networking test, there is unique device number in each chip to be measured, in the networking test, kernel control module will carry out corresponding operation according to device number, process type, and in non-networking test, device number is ignored by system.
3. distributed packet switching chip modelling verification as claimed in claim 1 system, it is characterized in that: between described program module, proprietary message comprises 6 message fields: device number, the source process type, the target process type, coomand mode, message number, message content, wherein, device number is used for distinguishing the chip to be measured of program module test, in the networking test, there is unique device number in each chip to be measured, in the networking test, kernel control module will be according to device number, process type is carried out corresponding operation, in non-networking test, device number is ignored by system, source process type and target process type are used for source and the target of a message of expression, and being convenient to kernel control module will forward according to process type, are used for simultaneously and message number together calculates global message number, coomand mode is used for the basic return state of a message of expression, message number be used for to be distinguished different message in the same class program module, and kernel control module number operates according to global message, message content is concrete message content corresponding to each message number.
4. distributed packet switching chip modelling verification as claimed in claim 3 system, it is characterized in that: described coomand mode comprises correctly returns to, orders mistake and command timeout three state.
5. distributed packet switching chip modelling verification as claimed in claim 3 system, it is characterized in that: described concrete message content comprises sub-message, character string information and protocol massages.
6. distributed packet switching chip modelling verification as claimed in claim 3 system, it is characterized in that: the message number of each class method inside modules is independent numbering, for whole distributed system, the overall start message numbering+message number of global message number=target process type.
7. as described in any one in claim 1 to 6 distributed packet switching chip modelling verification system, it is characterized in that: the order of described test case support comprises the stimulation arrangement order of chip configuration order to be measured, virtual network test instrumentation, the debug command that the response expectation checks regular configuration order and this distributed system.
8. as described in any one in claim 1 to 6 distributed packet switching chip modelling verification system, it is characterized in that: described kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model encapsulation module distribution are on same machines or different machines.
9. as described in any one in claim 1 to 6 distributed packet switching chip modelling verification system, it is characterized in that: described kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model encapsulation module distribution are in same operation system or different operating system.
10. distributed packet switching chip modelling verification method based on the described distributed packet switching chip modelling verification of any one in claim 1 to 9 system comprises the following steps:
S1, under system functional model checking scene:
step 101, system initialization: the application scenarios that global configuration is set is the system functional model checking, configure types of models and the device number of chip to be measured, the configuration kernel control module, the command line interface module, SDK proxy interface module, virtual network test instrumentation module, process identification (PID) and the device number of virtual chip configuration module and C model encapsulation module, first start kernel control module, then start client program module, client program module is according to the IP address in global configuration, message channel between the automatic establishment of port numbers and kernel control module, each module distribution is on one or more machine,
Step 102, test command or script typing: various command, script that user's typing command line interface module can be identified, the command line interface module will be ordered, script file is converted into command messages and sends to kernel control module, and command messages comprises that chip configuration order to be measured, stimulation arrangement order, response expectation check regular configuration order;
Step 103, test command forward: kernel control module is according to purpose process type and device number in the command messages of receiving, chip configuration order to be measured is forwarded to SDK proxy interface module, stimulation arrangement order, response expectation are checked that regular configuration order is forwarded to virtual network test instrumentation module;
Step 104, chip configuration command process to be measured: the chip configuration order to be measured that SDK proxy interface module will be received converts concrete chip configuration to, writes/read register and list item data in the virtual chip configuration module, reads for C model encapsulation module;
Step 105, stimulation arrangement command process: virtual network test instrumentation module is according to the stimulation arrangement order of receiving, produce corresponding variety of protocol bag data, and send to C model encapsulation module, and record simultaneously the excitation bag data of these generations, for generating, follow-up expectation bag data prepare;
Step 106, response expectation check regular configuration order processing: virtual network test instrumentation module checks the excitation bag data of record in regular configuration order and step 105 according to the response expectation of receiving, calculate the respond packet data that expectation obtains, and record, automatically relatively prepare between the respond packet for follow-up real response bag and expectation;
The bag of step 107, C model encapsulation module is processed: the data structure that the various excitation bag data transaction that C model encapsulation device will be received become chip model to be measured to identify, call the function of chip model to be measured, the data structure that meets with a response and wrap, convert the respond packet message format that virtual network test instrumentation module needs to, send to virtual network test instrumentation module;
Step 108, comparison real response bag and Expected Response bag: before virtual network test instrumentation module is wrapped in the real response of receiving, the Expected Response bag of record compares, obtain final result, and the mode of result with file preserved, consult for the tester;
S2, under soft or hard collaborative simulation verification scene:
Step 201, system initialization: the application scenarios that global configuration is set is the soft or hard collaborative simulation verification, configure types of models and the device number of chip to be measured, process identification (PID) and the device number of configuration kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, first start kernel control module, then start client program module, client program module automatically create according to the IP address in global configuration, port numbers and kernel control module between message channel, each module distribution is on one or more machine;
Step 202, test command or script typing, identical with step 102: various command, script that user's typing command line interface module can be identified, the command line interface module will be ordered, script file is converted into command messages and sends to kernel control module, and command messages comprises that chip configuration order to be measured, stimulation arrangement order, response expectation check regular configuration order;
Step 203, test command forward, identical with step 103: kernel control module is according to purpose process type and device number in the command messages of receiving, chip configuration order to be measured is forwarded to SDK proxy interface module, stimulation arrangement order, response expectation are checked that regular configuration order is forwarded to virtual network test instrumentation module;
Step 204, chip configuration command process to be measured: the chip configuration order to be measured that SDK proxy interface module will be received converts concrete chip configuration to, the Direct Programming interface DPI that provides by the RTL simulator calls register and the list item configuration feature of simulation test platform, completes the register in RTL and list item configuration are carried out read-write operation; If former RTL simulation test platform is not developed corresponding register and list item configuration DPI, add register and list item configuration DPI and come adaptive native system;
Step 205, stimulation arrangement command process: virtual network test instrumentation module is according to the stimulation arrangement order of receiving, produce corresponding variety of protocol bag data, the pumping signal of calling simulation test platform by DPI drives function, excitation bag data are driven on the interface signal of RTL module to be measured, record simultaneously the excitation bag data of these generations, prepare for follow-up expectation bag data generate; If former RTL simulation test platform is not developed corresponding pumping signal and driven DPI, add pumping signal and drive the next adaptive native system of DPI;
Step 206, the regular configuration order of response expectation inspection are processed: virtual network test instrumentation module checks the excitation bag data of record in regular configuration order and previous step processing according to the response expectation of receiving, calculate the respond packet data that expectation obtains, by DPI, the respond packet of expectation is deposited in the simulation test platform of RTL, automatically relatively prepare between the respond packet for follow-up real response bag and expectation; If former RTL simulation test platform is not developed corresponding Expected Response bag storage DPI, add Expected Response bag storage DPI and come adaptive native system;
The simulation test platform of step 207, RTL emulation: RTL obtains excitation bag data from its DPI interface, is driven on the input interface signal of RTL module, after the RTL resume module is completed, from the output interface signal of RTL module, obtains actual respond packet data;
Step 208, the inner relatively real response bag of simulation test platform that compares real response bag and Expected Response bag: RTL and the data of Expected Response bag obtain final result, and the mode of result with file are preserved, and consult for the tester;
S3, under the prototype verification scene:
step 301, system initialization: the application scenarios that global configuration is set is prototype verification, configure types of models and the device number of chip to be measured, the configuration kernel control module, the command line interface module, SDK proxy interface module, process identification (PID) and the device number of virtual network test instrumentation module, first start kernel control module, then start client program module, client program module is according to the IP address in global configuration, message channel between the automatic establishment of port numbers and kernel control module, SDK proxy interface block configuration starts in the embedded system of prototype verification plate, all the other modules are distributed on one or more machine,
Step 302, test command or script typing, identical with step 202: various command, script that user's typing command line interface module can be identified, the command line interface module will be ordered, script file is converted into command messages and sends to kernel control module, and command messages comprises that chip configuration order to be measured, stimulation arrangement order, response expectation check regular configuration order;
Step 303, test command forward, identical with step 203: kernel control module is according to purpose process type and device number in the command messages of receiving, chip configuration order to be measured is forwarded to SDK proxy interface module, stimulation arrangement order, response expectation are checked that regular configuration order is forwarded to virtual network test instrumentation module;
Step 304, chip configuration command process to be measured: the chip configuration order to be measured that SDK proxy interface module will be received converts concrete chip configuration to, call register and the list item configuration feature of SDK, complete the register in FPGA to be measured and list item are carried out read-write operation;
Step 305, stimulation arrangement command process: virtual network test instrumentation module is according to the stimulation arrangement order of receiving, produce corresponding variety of protocol bag data, by calling the Packet Generation function of live network test instrumentation, bag is directly delivered to above the network interface of prototype verification plate to be measured, record simultaneously the excitation bag data of these generations, prepare for follow-up expectation bag data generate;
Step 306, the regular configuration order of response expectation inspection are processed: virtual network test instrumentation module checks the excitation bag data of record in regular configuration order and previous step processing according to the response expectation of receiving, calculate the respond packet data that expectation obtains, and record, open simultaneously the bag crawl function of live network test instrumentation, automatically relatively prepare between the respond packet for follow-up real response bag and expectation;
Step 307, FPGA complete bag and process: the physics realization FPGA of chip to be measured obtains excitation bag data by the network interface of prototype verification plate, finish dealing with the rear respond packet data of reality that send to the network interface of prototype verification plate, instrument receives respond packet simultaneously, deposits the bag of receiving in its inner buffer memory;
Step 308, comparison real response bag and Expected Response bag, after virtual network test instrumentation module distributes all excitation bags, call the bag crawl buffer memory read functions of live network test instrumentation, obtain actual respond packet data, compare with the Expected Response bag that records before, obtain final result, and the mode of result with file preserved, consult for the tester.
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|---|---|---|---|---|
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304383A (en) * | 2008-07-07 | 2008-11-12 | 杭州华三通信技术有限公司 | Method for switching message of switching network, switching system, routing line card and Ether line card |
| CN101547154A (en) * | 2009-05-06 | 2009-09-30 | 烽火通信科技股份有限公司 | A TRUNK dispensing method |
| CN101572673A (en) * | 2009-06-19 | 2009-11-04 | 杭州华三通信技术有限公司 | Distributed packet switching system and distributed packet switching method of expanded switching bandwidth |
| US20110185241A1 (en) * | 2010-01-22 | 2011-07-28 | Robert Erickson | Method and System for Packet Switch Based Logic Replication |
-
2013
- 2013-03-15 CN CN201310083802.9A patent/CN103178996B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304383A (en) * | 2008-07-07 | 2008-11-12 | 杭州华三通信技术有限公司 | Method for switching message of switching network, switching system, routing line card and Ether line card |
| CN101547154A (en) * | 2009-05-06 | 2009-09-30 | 烽火通信科技股份有限公司 | A TRUNK dispensing method |
| CN101572673A (en) * | 2009-06-19 | 2009-11-04 | 杭州华三通信技术有限公司 | Distributed packet switching system and distributed packet switching method of expanded switching bandwidth |
| US20110185241A1 (en) * | 2010-01-22 | 2011-07-28 | Robert Erickson | Method and System for Packet Switch Based Logic Replication |
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