CN116938393B - Chip detection method, system and storage medium - Google Patents
Chip detection method, system and storage medium Download PDFInfo
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- CN116938393B CN116938393B CN202311189630.3A CN202311189630A CN116938393B CN 116938393 B CN116938393 B CN 116938393B CN 202311189630 A CN202311189630 A CN 202311189630A CN 116938393 B CN116938393 B CN 116938393B
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- 238000001514 detection method Methods 0.000 title claims abstract description 107
- 238000012360 testing method Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000005540 biological transmission Effects 0.000 claims description 16
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 238000004590 computer program Methods 0.000 claims description 4
- 230000002159 abnormal effect Effects 0.000 claims description 2
- 230000006870 function Effects 0.000 description 15
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/1607—Details of the supervisory signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
- H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica
- H04L1/243—Testing correct operation by comparing a transmitted test signal with a locally generated replica at the transmitter, using a loop-back
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L2001/0092—Error control systems characterised by the topology of the transmission link
- H04L2001/0095—Ring
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a chip detection method, a system and a storage medium, wherein the method comprises the following steps: the chip detection method is applied to an integrated chip to be detected, the integrated chip to be detected simultaneously supports a receiving function and a sending function, the integrated chip to be detected comprises an application processor module and a loop path, the loop path comprises a sending data control module, a sending module, a loop module, a receiving module and a receiving data control module which are sequentially connected in sequence, and the method comprises the following steps: the application processor module sends detection data to the sending data control module; the application processor module receives detection data returned by the connection sequence of the loop path; the application processor compares whether the transmitted detection data and the received detection data are the same, and a corresponding test result is obtained according to the comparison result. The application realizes the self-checking function of the chip, improves the reliability of the system and meets the requirement of functional safety. Meanwhile, the complexity of chip testing can be simplified, the occupied area of testing is reduced, and the testing time and labor cost are reduced.
Description
Technical Field
The present application relates to the field of data security technologies, and in particular, to a method, a system, and a storage medium for detecting a chip.
Background
MIPI is an abbreviation for Mobile Industry Processor Interface, mobile industry processor interface. The D-PHY is one of MIPI protocols, provides definition of DSI (serial display interface) and CSI (serial camera interface) on a physical layer, manages, errors and communicates data between a host and a peripheral through physical interconnection, and is a standardized protocol of cameras and display screens in a mobile phone. The D-PHY adopts 1 pair of source synchronous differential clocks and 1-4 pairs of differential data lines to carry out data transmission, and the data transmission adopts a DDR mode.
The use of D-PHY is often divided into two independent chip uses, master and slave. For example, the CPU sends an instruction, the instruction is transmitted to a D-PHY main control (TX) chip through the PPI bus by the LCD control module, the main control module sends data to a controlled (RX) chip of the LCD device through dp and dn differential lines, and the data is further modulated and displayed on a display screen.
At present, the main control chip and the controlled chip only complete the internal loop of the D-PHY or the loop between the D-PHY and the D-PHY layer in the test process, and the main control chip and the controlled chip need to be separately tested by means of certain peripheral equipment and circuits, and although the separate test mode is flexible, whether the channels in the integrated chip are normal or not cannot be confirmed, so that the data accuracy is ensured. Meanwhile, the area consumption is also brought, and the cost of test time and labor cost is increased.
Disclosure of Invention
The embodiment of the application aims to provide a chip detection method, a system and a storage medium, which integrate two independently used sending modules and receiving modules to realize integrated test, realize a chip self-checking function, improve the reliability of the system and meet the requirement of functional safety. Meanwhile, the complexity of chip testing can be simplified, the occupied area of testing is reduced, and the testing time and labor cost are reduced.
In a first aspect, to achieve the above object, an embodiment of the present application provides a chip detection method applied to an integrated chip to be detected, where the integrated chip to be detected supports a receiving function and a transmitting function at the same time, the integrated chip to be detected includes an application processor module and a loop path, and the loop path includes a transmitting data control module, a transmitting module, a loop module, a receiving module and a receiving data control module that are sequentially connected in sequence, the method includes:
the application processor module sends detection data to the sending data control module;
the application processor module receives detection data returned through the connection sequence of the loop path;
the application processor compares whether the sent detection data and the received detection data are the same or not, and a corresponding test result is obtained according to the comparison result.
In a second aspect, in order to solve the same technical problem, an embodiment of the present application provides a chip detection system, which is applied to an integrated chip to be detected, where the integrated chip to be detected supports a receiving function and a transmitting function at the same time, the integrated chip to be detected includes an application processor module and a loop path, and the loop path includes a transmitting data control module, a transmitting module, a loop module, a receiving module and a receiving data control module that are sequentially connected in sequence, and includes:
the application processor module is used for sending detection data to the sending data control module;
the application processor module is used for receiving detection data returned through the connection sequence of the loop path;
the application processor is used for comparing whether the sent detection data and the received detection data are the same or not, and obtaining a corresponding test result according to the comparison result.
In a third aspect, to solve the same technical problem, an embodiment of the present application provides a computer readable storage medium, where a computer program is stored, where an apparatus where the computer readable storage medium is controlled to execute the steps in the chip detection method described in any one of the above when the computer program runs.
The embodiment of the application provides a chip detection method, a system and a storage medium, wherein an integrated chip to be detected simultaneously supports a receiving function and a sending function, the integrated chip to be detected comprises an application processor module and a loop path, the loop path comprises a sending data control module, a sending module, a loop module, a receiving module and a receiving data control module which are sequentially connected in sequence, detection data are sent to the sending data control module through the application processor module, the application processor module receives the detection data which are sequentially returned through the connection of the loop path, then the application processor compares whether the sent detection data are identical with the received detection data, and a corresponding test result is obtained according to a comparison result. The application integrates and sets two independently used transmitting modules and receiving modules to realize integrated test, realizes the self-checking function of the chip, improves the reliability of the system and meets the requirement of functional safety. Meanwhile, the complexity of chip verification can be simplified, the occupied area of the test is reduced, and the test time and the labor cost are reduced.
Drawings
FIG. 1 is a schematic flow chart of a chip detection method according to an embodiment of the application;
FIG. 2 is a schematic diagram of a chip detection system according to an embodiment of the present application;
fig. 3 is a schematic diagram of another structure of a chip detection system according to an embodiment of the application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
Referring to fig. 1 to 3, fig. 1 is a flow chart of a chip detection method according to an embodiment of the present application, fig. 2 is a schematic structural diagram of an application processor 1 according to an embodiment of the present application, and fig. 3 is a schematic structural diagram of a loop module according to an embodiment of the present application. The chip detection method provided by the embodiment of the application is applied to an integrated chip to be detected, the integrated chip to be detected supports a receiving function and a transmitting function at the same time, the integrated chip to be detected comprises an application processor module 20 and a loop path, the loop path comprises a transmitting data control module 30, a transmitting module 60, a loop module 50, a receiving module 40 and a receiving data control module 10 which are sequentially connected in sequence, as shown in fig. 1, the chip detection method comprises the following steps:
s100, the application processor module 20 sends detection data to the sending data control module 30;
s200, the application processor module 20 receives detection data returned through the connection sequence of the loop path;
s300, the application processor 1 compares whether the sent detection data and the received detection data are the same, and a corresponding test result is obtained according to the comparison result.
Specifically, MIPI (Mobile Industry Processor Interface) is to standardize interfaces inside terminal devices such as a camera, a display screen interface, a radio frequency/baseband interface, and the like, so as to reduce the complexity of the design of the terminal device and increase the design flexibility.
The CSI (Camera Serial Interface) is a serial interface applied to camera technology, is a specification defined by MIPI, and is used for connecting a camera with a CPU and transmitting video signals of the camera. The data transmission process based on the CSI-2 camera uses data differential signals to transmit pixel values in video, meanwhile, the CSI-2 transmission interface can be very flexible to simplify or expand, for application scenes with fewer interfaces, the CSI-2 interface can complete the data serial transmission process of the camera by only using one group of differential data signal lines and one group of differential clock lines, so that the load is reduced, a certain transmission rate can be met, and for a large-array CCD camera, the CSI-2 interface can expand differential data lines of the CCD camera, and therefore the high-speed requirement of parallel transmission of multiple groups of data lines is met.
Wherein DSI (Display Serial Interface) is a serial interface applied to display technology, is compatible with DPI (display pixel interface ), DBI (display bus interface, display Bus Interface) and DCS (display command set ), transmits pixel information or instructions to peripheral devices in a serial manner, reads status information or pixel information from the peripheral devices, and enjoys independent communication protocols including data packet formats and error correction and detection mechanisms during transmission. MIPI-DSI has two working modes of high-speed mode and low-speed mode, all data paths can be used for unidirectional high-speed transmission, but only the first data path can be used for low-speed bidirectional transmission, and the formats of state information, pixels and the like of the slave end are returned through the data paths. The clock path is dedicated to transmitting the synchronous clock signal during high speed data transmission. Furthermore, one host side may allow simultaneous communication with multiple slaves.
The application can realize the self-checking function of the MIPI D-PHY Receiving (RX) and Transmitting (TX) module, improve the system reliability and meet the requirement of functional safety. The application is only applicable to integrated chips of modules supporting both MIPI D-PHY Receive (RX) and Transmit (TX). The application does not require complex external equipment, utilizes loop connection inside the chip, automatically receives the comparison data content, and simultaneously completes the detection of the receiving and transmitting module 60. Meanwhile, the whole link can cover a plurality of modules such as input of the receiving module 40, output of the application processor 1, output of the sending module 60 and the like, and system level testing is achieved. The integrated chip of the module supporting MIPI D-PHY Receiving (RX) and Transmitting (TX) often corresponds to independent CSI and DSI protocols, so that test data needs to cooperate with the loop module 50 to complete conversion between DSI and CSI protocols. The application can realize the self-checking function of the chip, improve the reliability of the system and meet the requirement of functional safety. Meanwhile, the factory test of the chip can be simplified, and the test time and the labor cost are saved.
In some embodiments, the receiving module 40 and the transmitting module 60 each support a serial display interface protocol and a serial camera interface protocol;
the receiving module 40 and the transmitting module 60 each include a data signal path and a clock signal path;
the receiving module 40 establishes a connection with the loop module 50 through the data signal path and the clock signal path;
the transmitting module 60 establishes a connection with the loop module 50 through the data signal path and the clock signal path.
In some embodiments, before the application processor module 20 sends the detection data to the sending data control module 30, it includes:
setting an operation mode of the loop module 50; the working modes comprise a non-transparent mode and a transparent mode;
the non-transparent mode is to perform protocol conversion so that the protocol type of the detected data returned to the application processor module 20 is the same as the protocol type of the detected data sent by the application processor module 20, and the transparent mode is to directly and transparently transmit the detected data to the receiving module 40 without performing protocol type conversion.
In some embodiments, the loop module 50 includes a non-transparent mode path and a transparent mode path; the application processor module 20 receiving the detection data returned through the connection sequence of the loop path includes:
the transmission data control module 30 transmits the detection data to the transmission module 60;
the loop module 50 receives the detection data sent by the sending module 60, judges whether the transparent mode access is opened, and sends the detection data to the receiving module 40 through a corresponding access according to the judgment result;
the receiving module 40 sends the detection data to the receiving data control module 10, and the receiving data control module 10 sends the detection data to the application processor module 20.
In some embodiments, the non-transparent mode path includes a packet processing unit and a clock processing unit, comprising:
if the determination result is that the transparent mode path is opened, the loop module 50 directly sends the detection data to the receiving module 40 through the transparent mode path;
if the transparent mode is not opened, the loop module 50 performs protocol conversion on the detection data through the packet processing unit and the clock processing unit, and sends the converted detection data with the same protocol type as that supported by the receiving module 40 to the receiving module 40.
In some embodiments, the loop module 50 further includes a control submodule 51, the control submodule 51 including a control register, the control submodule 51 being connected to the non-transparent mode path 52 and the transparent mode path 53, respectively, further including:
when the transparent mode path 53 receives a first preset configuration signal sent by the control register, closing the non-transparent mode path and opening the transparent mode path;
when the non-transparent mode path 52 receives a second preset configuration signal sent by the control register, the transparent mode path is closed and the non-transparent mode path is opened.
In some embodiments, the control registers are connected to an integrated System on a Chip (SOC) or the control registers are connected to peripheral hardware via a serial peripheral bus.
In some embodiments, the application processor 1 compares whether the transmitted detection data and the received detection data are the same, and obtaining the corresponding test result according to the comparison result includes:
if the comparison result is that the transmitted detection data is the same as the received detection data, determining that the passage of the integrated chip to be detected is normal;
and if the comparison result is that the transmitted detection data and the received detection data are different, sending out prompt information to inform that the channel of the integrated chip to be tested is abnormal.
Specifically, the present application includes an application processing module, a CSI/DSI control module, a transmitting module 60 (D-PHY TX), a loop module 50, a receiving module 40 (D-PHY RX) and a loop control module that are packaged inside the same integrated chip. Due to the different applications, the use of D-PHY is often divided into two separate modules, receive (RX) and Transmit (TX), and corresponds to two different protocols DSI (display serial interface) and CSI (camera serial interface). Both protocols may employ a D-PHY physical layer. For example, LCDs supporting MIPI D-PHY often have only a Receive (RX) module, corresponding to DSI protocol modulation.
Typically, the application processor module 20 sends the data to the controlled (RX) chip of the LCD device via the dp, dn differential lines via the DSI control module and transmit module 60 (TX), and further modulates the data for display on the display screen. And the camera only has a Transmitting (TX) module, corresponding to the CSI protocol modulation.
The entire detection data link of the present application is sent out of the application processor module 20, input to the transmit control module via the system bus, then to the physical layer transmit module 60 (TX) via the PPI interface, and into the loop module 50 from the clock and data path of the D-PHY.
Finally, the receiving module 40 (RX) transmits the data to the receiving control module through the PPI interface, and returns to the application processor 1 through the system bus, so that the detection is completed by comparing the input and output data. After the test is completed, the loop module 50 needs to be set to be in a closed mode, so that normal function use is not affected.
The loop module 50 provides packet and clock handling when supporting different protocol transceiver modules so that the receiving end module can properly parse.
The loop module 50 of the present application provides a register configuration to control the on-off of the loop, supporting transparent and non-transparent modes when on. Meanwhile, the loop module 50 of the present application also supports external devices to operate the control module registers through SPI/I2C configuration. Transparent mode is the transmission of data directly to the receiving module 40 (RX) through a transparent mode path. The non-transparent mode modulates the DSI/CSI packets into a protocol matching the receiving module 40 through a non-transparent mode path, and transmits the DSI/CSI packets to the receiving module 40 (RX).
The application relates to the field of integrated chip functional security and testing. The application utilizes the internal loop of the integrated chip to complete self-checking on the integrated chip of the module which simultaneously supports MIPI D-PHY Receiving (RX) and Transmitting (TX), improves the reliability of the system and meets the requirement of functional safety. According to the application, external equipment such as a package dispenser and a package receiver is not needed, so that the factory test of the chip is simplified, and the test time and the labor cost are saved. The application can realize the system level of the MIPI D-PHY in the chip and comprises the output of the sending module 60, the input of the detection of the whole link to the application processor module 20 and the final input of the receiving module 40.
In addition, referring to fig. 2, fig. 2 is a schematic structural diagram of a chip detection system provided by an embodiment of the present application, where the chip detection system provided by the embodiment of the present application is applied to an integrated chip to be detected, and the integrated chip to be detected supports a receiving function and a transmitting function at the same time, and as shown in fig. 2, the integrated chip to be detected includes an application processor module 20 and a loop path, and the loop path includes a transmitting data control module 30, a transmitting module 60, a loop module 50, a receiving module 40 and a receiving data control module 10 sequentially connected in sequence, and includes:
the application processor module 20 is configured to send detection data to the sending data control module 30;
the application processor module 20 is configured to receive detection data returned through a connection sequence of the loop path;
the application processor 1 is configured to compare whether the transmitted detection data and the received detection data are the same, and obtain a corresponding test result according to the comparison result.
The chip detection system can realize the steps in any embodiment of the chip detection method provided by the embodiment of the application, so that the beneficial effects of any chip detection method provided by the embodiment of the application can be realized, and detailed descriptions of the previous embodiments are omitted.
In the implementation, each module may be implemented as an independent entity, or may be combined arbitrarily, and implemented as the same entity or several entities, and the implementation of each module may be referred to the foregoing method embodiment, which is not described herein again.
Those of ordinary skill in the art will appreciate that all or a portion of the steps of the various methods of the above embodiments may be performed by instructions, or by instructions controlling associated hardware, which may be stored in a computer-readable storage medium and loaded and executed by a processor. To this end, an embodiment of the present application provides a computer readable storage medium having stored therein a plurality of instructions capable of being loaded by a processor to perform the steps of any one of the embodiments of the chip detection method provided by the embodiment of the present application.
Wherein the computer-readable storage medium may comprise: read Only Memory (ROM), random access Memory (RAM, random Access Memory), magnetic or optical disk, and the like.
The steps in any embodiment of the chip detection method provided by the embodiment of the present application can be executed by the instructions stored in the computer readable storage medium, so that the beneficial effects of any chip detection method provided by the embodiment of the present application can be achieved, which are detailed in the previous embodiments and are not described herein.
The above describes in detail a method, a system and a storage medium for detecting chips provided by the embodiments of the present application, and specific examples are applied to describe the principles and implementations of the present application, where the description of the above embodiments is only for helping to understand the method and core ideas of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application. Moreover, it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the principles of the present application, and such modifications and variations are also considered to be within the scope of the application.
Claims (9)
1. The chip detection method is characterized by being applied to an integrated chip to be detected, the integrated chip to be detected simultaneously supports a receiving function and a sending function, the integrated chip to be detected comprises an application processor module and a loop path, the loop path comprises a sending data control module, a sending module, a loop module, a receiving module and a receiving data control module which are sequentially connected in sequence, and the method comprises the following steps:
the application processor module sends detection data to the sending data control module;
the application processor module receives detection data returned through the connection sequence of the loop path;
the application processor compares whether the sent detection data and the received detection data are the same or not, and a corresponding test result is obtained according to the comparison result;
before the application processor module sends the detection data to the data sending control module, the method comprises the following steps: setting a working mode of the loop module; the working modes comprise a non-transparent mode and a transparent mode;
the non-transparent mode is to perform protocol conversion so that the protocol type of the detection data returned to the application processor module is the same as the protocol type of the detection data sent by the application processor module, and the transparent mode is to directly and transparently transmit the detection data to the receiving module without performing protocol type conversion.
2. The chip detection method according to claim 1, wherein the receiving module and the transmitting module both support a serial display interface protocol and a serial camera interface protocol;
the receiving module and the sending module comprise a data signal path and a clock signal path;
the receiving module and the loop module are connected through the data signal path and the clock signal path;
the transmitting module establishes connection with the loop module through the data signal path and the clock signal path.
3. The chip detection method according to claim 1, wherein the loop module includes a non-transparent mode path and a transparent mode path; the application processor module receiving detection data returned through the connection sequence of the loop path comprises:
the sending data control module sends the detection data to the sending module;
the loop module receives the detection data sent by the sending module, judges whether the transparent mode passage is opened or not, and sends the detection data to the receiving module through a corresponding passage according to a judging result;
the receiving module sends the detection data to the receiving data control module, and the receiving data control module sends the detection data to the application processor module.
4. The chip detection method according to claim 3, wherein the non-transparent mode path includes a packet processing unit and a clock processing unit, comprising:
if the judging result is that the transparent mode passage is opened, the loop module directly sends the detection data to the receiving module through the transparent mode passage;
and if the judging result is that the transparent mode access is not opened, the loop module carries out protocol conversion on the detection data through the data packet processing unit and the clock processing unit, and sends the converted detection data with the same protocol type as that supported by the receiving module to the receiving module.
5. The chip detection method according to claim 4, wherein the loop module further comprises a control submodule including a control register, the control submodule being connected to the non-transparent mode path and the transparent mode path, respectively, further comprising:
when the transparent mode access receives a first preset configuration signal sent by the control register, closing the non-transparent mode access and opening the transparent mode access;
and when the non-transparent mode access receives a second preset configuration signal sent by the control register, closing the transparent mode access and opening the non-transparent mode access.
6. The method of claim 5, wherein the control register is coupled to an integrated system-on-chip or the control register is coupled to peripheral hardware via a serial peripheral bus.
7. The chip detection method according to any one of claims 1 to 6, wherein the application processor comparing whether the transmitted detection data and the received detection data are identical, and obtaining a corresponding test result according to the comparison result comprises:
if the comparison result is that the transmitted detection data is the same as the received detection data, determining that the passage of the integrated chip to be detected is normal;
and if the comparison result is that the transmitted detection data and the received detection data are different, sending out prompt information to inform that the channel of the integrated chip to be tested is abnormal.
8. The utility model provides a chip detection system which characterized in that is applied to the integrated chip that awaits measuring, the integrated chip that awaits measuring supports receive function and transmit function simultaneously, the integrated chip that awaits measuring includes application processor module and loop path, the loop path includes transmission data control module, transmission module, return circuit module, receiving module and the received data control module that connects gradually in proper order, includes:
the application processor module is used for sending detection data to the sending data control module;
the application processor module is used for receiving detection data returned through the connection sequence of the loop path;
the application processor is used for comparing whether the sent detection data and the received detection data are the same or not, and obtaining a corresponding test result according to the comparison result;
before the application processor module sends the detection data to the data sending control module, the method comprises the following steps: setting a working mode of the loop module; the working modes comprise a non-transparent mode and a transparent mode;
the non-transparent mode is to perform protocol conversion so that the protocol type of the detection data returned to the application processor module is the same as the protocol type of the detection data sent by the application processor module, and the transparent mode is to directly and transparently transmit the detection data to the receiving module without performing protocol type conversion.
9. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program, wherein the computer program when run controls a device in which the computer readable storage medium is located to perform the steps in the chip detection method according to any one of claims 1 to 7.
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