CN115242681A - System, method and equipment for testing communication module in chip and storage medium - Google Patents
System, method and equipment for testing communication module in chip and storage medium Download PDFInfo
- Publication number
- CN115242681A CN115242681A CN202211143334.5A CN202211143334A CN115242681A CN 115242681 A CN115242681 A CN 115242681A CN 202211143334 A CN202211143334 A CN 202211143334A CN 115242681 A CN115242681 A CN 115242681A
- Authority
- CN
- China
- Prior art keywords
- test
- module
- data
- test data
- self
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 464
- 238000004891 communication Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims description 22
- 238000001514 detection method Methods 0.000 claims abstract description 40
- 230000006870 function Effects 0.000 claims description 74
- 230000004044 response Effects 0.000 claims description 24
- 238000004590 computer program Methods 0.000 claims description 6
- 230000002159 abnormal effect Effects 0.000 claims description 5
- 238000013480 data collection Methods 0.000 claims description 5
- 238000012795 verification Methods 0.000 claims description 4
- 238000013461 design Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0823—Errors, e.g. transmission errors
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention relates to the field of computer chip design, in particular to a test system of an on-chip communication module, which comprises a self-detection module and a test data connection module, wherein: the self-detection module is configured to send first test data to the test data connection module and receive second test data sent by the test data connection module, and verify the function of the test module based on comparison between the first test data and the second test data; the test data connection module is configured to receive first test data of the self-test module, forward the first test data to the test module, and send second test data sent by the test module to the self-test module. And the check comparison module is used for comparing whether the received and transmitted data are consistent or not so as to judge the basic state of the test module by the driver, thereby greatly improving the debugging speed of the network function.
Description
Technical Field
The invention belongs to the field of computers, and particularly relates to a system, a method and equipment for testing an on-chip communication module and a readable storage medium.
Background
The baseboard management control chip is a common chip on the server and is used for monitoring and managing the running state of the server. The network function is a necessary function in the baseboard management control chip, and the general baseboard management control chip at least comprises two network modules (EMAC 1 and EMAC 2), wherein the EMAC1 is a special network card of the baseboard management control chip and can normally communicate with an external network. EMAC2 is used to manage and configure a network card of a server (host side). In an advanced baseboard management control chip, more network modules are included, such as 4.
The network module (EMAC, ethernet Media Access Controller) has powerful functions, occupies a large chip resource and area, and has numerous registers, so that the driving of the debugging of the network module is complex after the chip stream comes back, the debugging period is long, the chip debugging mainly comprises the debugging of a driver/software personnel, while the development of the EMAC is that a chip designer designs the chip, and the driver does not understand the internal architecture and the register function inside the EMAC as much as the chip designer, thereby virtually prolonging the debugging period of the network function.
Especially, placing a plurality of network modules into a baseboard management control chip brings great risks to the comprehensive constraint, layout and wiring of the chip and the package manufacturing, so that the network function in the chip after tape-out may be disabled and the network function is not available, and at this time, a driver cannot determine whether the chip itself is a functional error or a PHY (Physical, port Physical layer, an ethernet PHY is a chip and can send and receive data frames (frames) of the ethernet) of the chip itself or a PCB board card has a problem, which greatly prolongs the debugging period of the network function.
Therefore, an effective means is needed to solve the problem of debugging efficiency in the conventional BMC chip design.
Disclosure of Invention
In order to solve the above problems, the present invention provides a test system for an on-chip communication module, which includes a self-test module and a test data connection module, wherein:
the self-detection module is configured to send first test data to the test data connection module and receive second test data sent by the test data connection module, and verify the function of the test module based on comparison between the first test data and the second test data;
the test data connection module is configured to receive first test data of the self-test module, forward the first test data to the test module, and send second test data sent by the test module to the self-test module.
In some embodiments of the invention, the self-detection module comprises:
a test enable register configured to receive a control signal of a CPU and enable or disable a function of the self-test module.
In some embodiments of the invention, the self-detection module further comprises:
a test status register configured to store the comparison verification result based on the first test data and the second test data.
In some embodiments of the invention, the self-detection module further comprises:
a first storage module configured to store the first test data and to provide the first test data to the test module in response to a start of a test;
a second storage module configured to receive and store the second test data.
In some embodiments of the invention, the self-detection module further comprises:
and the comparison module is configured to read the first test data and the second test data from the first storage module and the second storage module, compare the first test data with the second test data, and update the comparison result to a test status register.
In some embodiments of the invention, the system further comprises:
a configuration data connection module configured to obtain configuration data from the self-test module and configure a function of the test module based on the configuration data.
In some embodiments of the invention, the self-detection module further comprises:
a test configuration module configured to initialize a function of the test module through the configuration data connection module.
In some embodiments of the invention, the system further comprises:
and the test data loop-back module is configured to connect an external output interface of the test module with an input interface, acquire output data of the test module, and send the output data serving as second test data to the self-detection module through the test data connection module.
In some embodiments of the invention, the system further comprises:
and the test module control register is configured to switch the function and the data connection mode of the test module.
Another aspect of the present invention further provides a method for testing an on-chip communication module, including:
sending first test data to a test module, and collecting second test data sent by the test module;
comparing the first test data with the second test data, and judging whether comparison results are the same;
judging that the function of the test module is normal in response to the comparison result being the same;
and judging that the function of the test module is abnormal in response to the different comparison results.
In some embodiments of the invention, the method further comprises:
the first test data is pre-stored in a first storage module, and the first test data is read from the first storage module and sent to the test module in response to the start of the test;
and storing the second test data in a second storage module, and reading the corresponding first test data and the second test data from the first storage module and the second storage module respectively for comparison in response to the completion of second test data collection.
In some embodiments of the invention, collecting the second test data from the test module comprises:
adding a test data loopback module between an external output interface and an external input interface of the test module according to the interface type, and sending the data of the output interface to the input interface through the test data loopback module;
and acquiring data output by an output interface in the test module pair as second test data.
In some embodiments of the invention, collecting the second test data from the test module comprises:
and acquiring data output by an external output interface of the test module as the second test data through the test data loopback module.
Yet another aspect of the present invention also provides a computer apparatus, including:
at least one processor;
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of the above embodiments.
Yet another aspect of the present invention further provides a computer-readable storage medium, which stores a computer program, and the computer program realizes the steps of the method of any one of the above embodiments when executed by a processor.
This scheme has optimized on traditional scheme basis, through the self test module in the operation chip, can accomplish the configuration of the important register of test module, through enabling test module's TX interface and RX interface reversal connection function, utilize two storage modules simultaneously, read first test data from first storage module, data interface through test module sends to test module's TX interface, then after returning, receive back through test module's RX, write to the second storage module, utilize the check-up comparison module, it is unanimous whether to compare the send-receive data, supply the drive to judge test module's basic condition, the debugging speed of network function has been improved greatly.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a system for testing an on-chip communication module according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an embodiment of a system for testing an on-chip communication module according to an embodiment of the present invention;
fig. 3 is a diagram illustrating an embodiment of a system for testing an on-chip communication module according to an embodiment of the present invention;
fig. 4 is a flowchart of a method for testing an on-chip communication module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a design flow of a conventional baseboard manager chip according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a computer device according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a computer storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are only used for convenience of expression and should not be construed as a limitation to the embodiments of the present invention, and no description is given in the following embodiments.
The embodiment of the invention aims to solve the problem that the debugging period of a network module in the traditional substrate management control chip is long. And the fault point with the problem during debugging is difficult to find. As shown in fig. 5, a debugging process of a network module in a conventional baseboard management control chip is that a chip designer first performs RTL (hardware development language) code development of an EMAC function, or purchases an existing IP (intellectual property core) for code analysis, and then performs overall code development of the baseboard management chip (SoC system) and system simulation. And then carrying out back end design of the chip, including chip synthesis, layout and wiring, chip production, packaging test and the like. And after the chip flow is back, driving personnel to test the EMAC function. However, a developer needs to be driven to debug the EMAC function by referring to a design scheme given by a chip designer, particularly function introduction of each register, and the debugging period is long. And once the network function is not available, a driver cannot determine that the chip has a function error, the PHY chip on the periphery of the chip or the PCB has a problem, so that the debugging period of the network function is greatly prolonged.
Therefore, the traditional scheme has the defects that the drive test period after the chip is returned is long, the project progress is easily delayed, the network module is a basic module in the substrate management control chip, and a large number of upper-layer applications are performed under the condition that the functions of the network module are normal, so that once the drive debugging time is long, the whole project is easily delayed, and particularly, the drive debugging time is a huge hidden danger when a product is on the market or a national important special project is faced.
As shown in fig. 1, to solve the above problem, the present invention provides a test system for an on-chip communication module, which includes a self-test module 1 and a test data connection module 2, wherein:
the self-detection module 1 is configured to send first test data to the test data connection module 2 and receive second test data sent by the test data connection module 2, and verify the function of the test module 12 based on comparison between the first test data and the second test data;
the test data connection module 2 is configured to receive first test data of the self-test module 1, forward the first test data to the test module 12, and send second test data sent by the test module 12 to the self-test module 1.
In this embodiment, the present invention takes the test of the EMAC module in the bmc chip as an example, and the test module is the EMAC module in the bmc chip, as described above, the EMAC is the network module of the bmc chip. In this embodiment, the self-test module 1 according to the present invention sends the predetermined test data to the EMAC module through the test data connection module 2 based on the corresponding bus in the substrate control chip in a manner simulating normal data network data sending, or the EMAC reads the corresponding first test data from the self-test module 1 through the test data connection module 2 by using the corresponding bus.
In the present invention, the test data connection module 2 is a data interface conversion module connected to the test module 12, and the test data connection module 2 implements data interaction between the self-test module 1 and the test module 12 in a test mode, that is, sends first test data to the test module 12, and sends second test data sent by the test module 12 to the self-test module. In a normal working mode, the test data connection module 2 is directly connected to the bus of the baseboard management controller chip, and acquires corresponding data from the memory or the CPU and sends the data to the test module.
The second test data is data sent externally by the test module, and in this embodiment, the second test data refers to data sent by the EMAC module, and can be sent out through the network after passing through the PHY interface. Therefore, in this embodiment, the data sent by the EMAC module is used as the second test data, and then fed back to the self-detection module 1 by the test data connection module 2.
After the self-test module 2 receives the second test data or receives the corresponding second test data, the second test data is compared with the first test data, and if the contents of the first test data and the second test data are consistent, the function of the test module 12 is considered to be normal, so that the design purpose is realized. If the contents of the first test data and the second data are not consistent, it is assumed that there is a corresponding exception in the test module 12 and the function of some designs is not implemented.
It should be noted that the first test data and the second test data may not be in the same form, because the data bus used for sending the data to the test module and the data link used for the output interface of the test module 12 are not the same, and therefore the forms of the first test data and the second test data may not be the same. In general, the comparison of the key content information of the first test data and the second test data is, for example, self-detection of the EMAC module, the second test data should be data sent by the EMAC to the PHY module, the first test data and the second test data should be different in form, but the comparison is performed on the data content itself and the related configuration information of the EMAC during the comparison, and the related configuration information is the configuration information related to the function corresponding to the EMAC, such as an IP address, IP packet information, and the like.
In some embodiments of the present invention, corresponding pseudo second test data (which satisfies the second test data sent by the test module 12 in terms of form) may be generated in advance according to the form of the output data of the test module 12 and the relevant configuration information of the test module 12, and then the pseudo second test data may be stored in the first storage module 5, and when the first test data is provided to the test module 12, a content portion in the pseudo second test data may be sent to the test module 12. Further, when receiving the second test data sent through the test data connection module 2, the second test data is directly compared with the pseudo second test data (the first test data is matched with the second test data in form, and if the contents are the same, the comparison can be directly performed).
In some embodiments of the invention, the self-detection module comprises:
a test enable register 3, wherein the test enable register 3 is configured to receive a control signal of a CPU and enable or disable the function of the self-detection module 1.
In this embodiment, the test enable register 3 is a register for controlling the self test module 1, the CPU can access and modify the value of the test enable register 3, the self test module 1 is enabled when the value of the test enable register 3 is 1, and the self test module 1 is turned off when the value of the test enable register 3 is 0.
In some embodiments of the present invention, the self-detection module 1 further comprises:
a test status register 4, the test status register 4 configured to store the comparison verification result based on the first test data and the second test data.
In this embodiment, similar to the test enable register 3, the test status register 4 may also be accessed and modified by the CPU, and the test status register 4 is used for storing the test result of the self-test module 1 to the test module 12. If the self-detection module 1 passes the consistency of the comparison result of the first test data and the second test data, the test passes, the self-detection module 1 modifies the value of the test state register 4 to 1, the CPU reads the value of the test state register 4 through the corresponding bus to be 1, then the self-detection module 1 can know that the detection result of the self-detection module 1 to the test module 12 passes, conversely, if the comparison is inconsistent, the self-detection module 1 modifies the value of the test state register 4 to be 0, and the CPU reads the value of the test state register 4 through the corresponding bus to be 0, then the self-detection module 1 can know that the detection result of the self-detection module 1 to the test module 12 does not pass.
In some embodiments of the invention, the self-detection module 1 further comprises:
a first storage module 5, said first storage module 5 being configured to save said first test data and to provide first test data to said test module in response to a start of a test;
a second storage module 6, wherein the second storage module 6 is configured to receive and store the second test data.
In the present embodiment, the self-test module 1 is provided with a first storage module 5 for storing the first test data in advance, and is designed to be readable by the test module through the test data connection module 2, and it can be understood that, in the test mode, the data source of the test module 12 is switched to the first storage module 5.
In addition, the self-test module 1 is further provided with a second storage module 6 for storing second test data sent by the test module 12, and when the second test data is collected or the second test data is collected, the self-test module 1 reads corresponding first test data and second test data in the first storage module 5 and the second storage module 6 for comparison.
In some embodiments of the invention, the self-detection module 1 further comprises:
a comparison module 7, wherein the comparison module 7 is configured to read the first test data and the second test data from the first storage module and the second storage module, compare the first test data and the second test data, and update the comparison result to the test status register 4.
In this embodiment, the comparing module 7 is a module for determining whether the testing module 12 of the self-testing module 1 is a module for determining whether the function is normal, and compares the corresponding first testing data obtained from the first storage module 5 with the corresponding second testing data obtained from the second storage module 6, and updates the comparison result to the testing status register 4. Specifically, if the comparison result is consistent, a 1 is written to the test status register, and otherwise, a 0 is written to the test status register.
In some embodiments of the invention, the system further comprises:
a configuration data connection module 9, said configuration data connection module 9 configured to obtain configuration data from said self-test module 1 and to configure the functionality of said test module 12 based on said configuration data.
In this embodiment, the configuration data connection module 9 is connected to the test module 12 or controls the test module 12 to a certain extent, so as to obtain the configuration data corresponding to the test module to perform corresponding configuration on the function of the test module 12.
In some embodiments of the present invention, the self-detection module 1 further comprises:
a test configuration module 8, wherein the test configuration module 8 is configured to initialize a function of the test module 12 through the configuration data connection module 9.
In this embodiment, the test configuration module 8 includes relevant configuration information necessary for the test module 12, taking an EMAC test of the bmc as an example, the test configuration module 8 includes register data necessary for normal operation of the EMAC, and when the EMAC is tested, the configuration data connection module 9 may obtain data of each register (registered data necessary for internal function implementation of the EMAC, such as enable receiving, enable sending, enable Burst operation, configure IP, and the like) on the corresponding EMAC from the test configuration module 8, and write the corresponding register data into the corresponding register to implement initialization of the function of the test module 12.
In some embodiments of the invention, the system further comprises:
and the test data loopback module 10, wherein the test data loopback module 10 is configured to connect an externally output interface of the test module 12 with an input interface, acquire output data of the test module, and send the output data serving as second test data to the self-test module through the test data connection module.
In this embodiment, the test data loopback module 10 connects an external sending end of the test module 12 with a receiving end of the test module 12, and feeds back data sent by the test module 12 to the receiving end of the test module 12.
In some embodiments of the invention, the system further comprises:
and the test module control register 11 is configured to switch the function and the data connection mode of the test module.
In this embodiment, the test module controller register 11 is used to control the operation mode of the test module, and when the value is 1, it indicates that the test module 12 is switched to the test mode.
As shown in fig. 3, another aspect of the present invention further provides a method for testing an on-chip communication module, including:
s1, sending first test data to a test module, and collecting second test data sent by the test module;
s2, comparing the first test data with the second test data, and judging whether comparison results are the same;
s3, judging that the function of the test module is normal in response to the same comparison result;
and S4, judging that the function of the test module is abnormal in response to the different comparison results.
In some embodiments of the invention, the method further comprises:
the first test data is pre-stored in a first storage module, and the first test data is read from the first storage module and sent to the test module in response to the start of the test;
and storing the second test data in a second storage module, and reading the corresponding first test data and the second test data from the first storage module and the second storage module respectively for comparison in response to the completion of second test data collection.
In some embodiments of the invention, collecting the second test data from the test module comprises:
adding a test data loopback module between an external output interface and an external input interface of the test module according to the interface type, and sending the data of the output interface to the input interface through the test data loopback module;
and acquiring data output by an output interface in the test module pair as second test data.
In some embodiments of the present invention, collecting the second test data issued by the test module comprises:
and acquiring data output by an external output interface of the test module through the test data loopback module as second test data.
In some embodiments of the present invention, as shown in fig. 3, fig. 3 shows an embodiment of the present invention in which an EMAC network module of a bmc chip performs a self-test.
Firstly, before the network function of the baseboard management control chip is formally debugged, a driver and/or a user issues the enabling (setting a register) of the network hardware function self-detection. Even if the EMAC (corresponding to the TEST module 12) and the EMAC _ HARD _ way _ TEST (corresponding to the self-TEST module 11) are enabled, the enabling refers to sending the data of the corresponding register to the EMAC and the EMAC _ HARD _ way _ TEST modules, respectively, it is noted that compared with the conventional solution, the present invention inventively adds the EMAC _ HARD _ way _ TEST module (corresponding to the self-TEST module) in the hardware architecture of the chip, and the module is also to be mounted on the system bus of the bmc chip, and the CPU can access and control the module. The various sub-modules in EMAC _ HARD _ WRE _ TEST are introduced as follows:
TEST _ EN (equivalent to TEST enable register 3) & TEST _ STATE (equivalent to TEST status register 4), which are two registers, the TEST _ EN register can receive the configuration of the CPU and turn on/off the network hardware self-TEST function.
When TEST _ EN =1, the network hardware self-TEST function is enabled.
And when TEST _ EN =0, the network hardware self-TEST function is closed.
The TEST _ STATE register stores a STATE after the network hardware self-testing function is completed, wherein TEST _ STATE =1 represents that the network hardware self-testing is passed, and TEST _ STATE =0 represents that the network hardware self-testing is failed.
Further, the EMAC _ HARD _ WRE _ TEST also includes a HARD _ CFG _ GEN (equivalent to the TEST configuration module 8) submodule that issues registers (such as enable receive, enable transmit, enable Burst operation, configure IP, and the like) that are necessary (basic) for normal operation of the EMAC. And then sent to the EMAC module.
RAM _ a (corresponding to the first memory module 5) stores data to be transmitted, and after the configuration of HARD _ CFG _ GEN, the EMAC can read the data in the RAM _ a through the data interface.
RAM _ B (corresponding to the second memory module 6) stores the received data, and after the configuration of HARD _ CFG _ GEN, the EMAC may write the data to RAM _ B through the data interface.
And the COMP (equivalent to the comparison module 7) is used for reading the data in the RAM _ A and the RAM _ B, comparing, if the data are consistent in receiving and transmitting, indicating that the EMAC has normal basic functions and the hardware passes self-TEST, and then setting the TEST _ STATE to be 1.
If the receiving and sending are inconsistent, the EMAC is not normal in function, the hardware self-TEST is passed, and the TEST _ STATE is set to be 0.
Compared with the conventional scheme, the EMAC module is also modified, and mainly includes TEST _ MODE register (equivalent to the TEST module control register 11), DATA _ INTF _ SWITCH (equivalent to the TEST DATA connection module), CFG _ INTF _ SWITCH (equivalent to the configuration DATA connection module 9), and connection _ MDY (TEST DATA loopback module 10) sub-modules.
And a TEST _ MODE register which receives the configuration of the CPU, and when the register =1, the hardware self-TEST function of the EMAC is enabled, namely, the communication of the EMAC and the chip internal DATA _ INTF _ SWITCH is switched to the EMAC _ HARD _ WRE _ TEST module at the moment, the DATA is read from the RAM _ A, and the looped-back DATA of the EMAC is sent to the RAM _ B for storage.
The DATA _ INTF _ SWITCH submodule (equivalent to the TEST DATA connection module 2) is a DATA interface conversion module of the EMAC, and because a DATA interface of the EMAC is connected with a system bus in the traditional scheme and acquires DATA to be sent from a DDR, in the invention, the DATA _ INTF _ SWITCH submodule is used as a DATA interface to receive not only DATA from the DDR (in a normal mode, a hardware self-TEST function is not enabled) but also send DATA from the EMAC _ HARD _ wait _ TEST (in a TEST mode, a hardware self-TEST function is enabled). Similarly, in the conventional scheme, the data interface writes the received data to the DDR, whereas in the present invention, the data interface can write data not only to the DDR (normal mode, hardware self-TEST function is not enabled), but also to EMAC _ HARD _ wake _ TEST (TEST mode, hardware self-TEST function is enabled).
The CFG _ INTF _ SWITCH submodule (equivalent to the configuration data connection module 9) is a configuration interface conversion module of the EMAC, and because the configuration interface of the EMAC is connected with a system bus in the traditional scheme and is issued by a CPU for configuration, in the invention, the CFG _ INTF _ SWITCH submodule not only needs to receive the configuration from the CPU (in a conventional mode, a hardware self-TEST function is not enabled) but also receives the configuration information from the EMAC _ HARD _ warn _ TEST (in a TEST mode, a hardware self-TEST function is enabled).
The CONNECT _ MDY submodule (corresponding to the test data LOOPBACK module 10 described above) functions to CONNECT the TX and RX data interfaces of the EMAC in reverse, i.e., the LOOPBACK, when the test module is enabled. That is, the transmission data of the EMAC itself is directly transmitted to the data receiving interface of the EMAC through the transmission interface, and the connection mode under the conventional scheme is that the data of the TX interface passes through the PHY chip and then is transmitted to the remote end through the network cable. And the far end received by the RX interface sends data of the PHY chip through the network cable.
And after the network hardware self-TEST is finished, generating an interrupt, reporting to a CPU, setting a TEST _ STATE register according to the TEST STATE, and judging the hardware self-TEST result by reading the value of the TEST _ STATE.
If the value of TEST _ STATE is 1, the hardware self-TEST is passed, and the driver can normally perform detailed EMAC function debugging and upper-layer application debugging. If the value of TEST _ STATE is 0, the network function in the substrate management control chip is failed, and the driver cannot be debugged.
The scheme is optimized on the basis of the traditional scheme, the self-detection module is utilized to complete the configuration of an EMAC (electro magnetic communication) important register, such as TX/RX (transmitter/receiver) function enabling and Burst function enabling, the reverse connection function of an EMAC TX interface and an RX interface, two RAMs are utilized to read data from the RAM _ A, the data is sent to the TX interface of the EMAC through the data interface of the EMAC, then the data is received back through the RX of the EMAC after looping back, the data is written to the RAM _ B, and a verification comparison module is utilized to compare whether the received data is consistent or not, so that the hardware self-test of the network function in the substrate management control chip is completed, and meanwhile, a state register is arranged for driving to judge the basic state of the EMAC, and the debugging speed of the network function is greatly improved.
As shown in fig. 6, another aspect of the present invention also provides a computer device, including:
at least one processor 21;
a memory 22, the memory 21 storing computer instructions 23 executable on the processor 21, the instructions 23 when executed by the processor 21 implementing a method for on-chip communication module testing, comprising:
sending first test data to a test module, and collecting second test data sent by the test module;
comparing the first test data with the second test data, and judging whether comparison results are the same;
judging that the function of the test module is normal in response to the comparison result being the same;
and judging that the function of the test module is abnormal in response to the different comparison results.
In some embodiments of the invention, the method further comprises:
the first test data is pre-stored in a first storage module, and is read from the first storage module in response to the start of the test and sent to the test module;
and storing the second test data in a second storage module, and reading the corresponding first test data and the second test data from the first storage module and the second storage module respectively for comparison in response to the completion of second test data collection.
In some embodiments of the present invention, collecting the second test data issued by the test module comprises:
adding a test data loopback module between an external output interface and an external input interface of the test module according to the interface type, and sending the data of the output interface to the input interface through the test data loopback module;
and acquiring data output by an output interface in the test module pair as second test data.
In some embodiments of the invention, collecting the second test data from the test module comprises:
and acquiring data output by an external output interface of the test module as the second test data through the test data loopback module.
As shown in fig. 7, a further aspect of the present invention also provides a computer-readable storage medium 401, where the computer-readable storage medium 401 stores a computer program 402, and when the computer program 402 is executed by a processor, the computer program 402 implements a method for testing an on-chip communication module, including:
sending first test data to a test module, and collecting second test data sent by the test module;
comparing the first test data with the second test data, and judging whether comparison results are the same;
judging that the function of the test module is normal in response to the comparison result being the same;
and judging that the function of the test module is abnormal in response to the different comparison results.
In some embodiments of the invention, the method further comprises:
the first test data is pre-stored in a first storage module, and is read from the first storage module in response to the start of the test and sent to the test module;
and storing the second test data in a second storage module, and reading the corresponding first test data and the second test data from the first storage module and the second storage module respectively for comparison in response to the completion of second test data collection.
In some embodiments of the invention, collecting the second test data from the test module comprises:
adding a test data loopback module between an external output interface and an external input interface of the test module according to the interface type, and sending the data of the output interface to the input interface through the test data loopback module;
and acquiring data output by an output interface in the test module pair as second test data.
In some embodiments of the invention, collecting the second test data from the test module comprises:
and acquiring data output by an external output interface of the test module through the test data loopback module as second test data.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the framework of embodiments of the invention, also combinations between technical features of the above embodiments or different embodiments are possible, and there are many other variations of the different aspects of the embodiments of the invention described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (12)
1. The test system of the communication module in the chip is characterized by comprising a self-detection module and a test data connection module, wherein:
the self-detection module is configured to send first test data to the test data connection module and receive second test data sent by the test data connection module, and verify the function of the test module based on comparison of the first test data and the second test data;
the test data connection module is configured to receive first test data of the self-detection module, forward the first test data to the test module, and send second test data sent by the test module to the self-detection module;
a configuration data connection module configured to obtain configuration data from the self-detection module and configure a function of the test module based on the configuration data;
the self-detection module further comprises a test configuration module, and the test configuration module is configured to initialize the functions of the test module through the configuration data connection module;
and the test module control register is configured to switch the function and the data connection mode of the test module.
2. The system of claim 1, wherein the self-detection module comprises:
a test enable register configured to receive a control signal of a CPU and enable or disable a function of the self-test module.
3. The system of claim 1, wherein the self-detection module further comprises:
a test status register configured to store the comparison verification result based on the first test data and the second test data.
4. The system of claim 1, wherein the self-detection module further comprises:
a first storage module configured to store the first test data and to provide the first test data to the test module in response to a start of a test;
a second storage module configured to receive and store the second test data.
5. The system of claim 4, wherein the self-detection module further comprises:
and the comparison module is configured to read the first test data and the second test data from the first storage module and the second storage module, compare the first test data and the second test data, and update a comparison result to the test status register.
6. The system of claim 1, further comprising:
and the test data loop module is configured to connect an externally output interface of the test module with an input interface, acquire output data of the test module, and send the output data serving as second test data to the self-detection module through the test data connection module.
7. A method for testing an on-chip communication module, comprising:
acquiring configuration data of a test module and configuring the function of the test module based on the configuration data;
completing switching of a data connection mode of the test module in response to the functional configuration of the test module;
sending first test data to a test module, and collecting second test data sent by the test module;
comparing the first test data with the second test data, and judging whether comparison results are the same;
judging that the function of the test module is normal in response to the comparison result being the same;
and judging that the function of the test module is abnormal in response to the different comparison results.
8. The method of claim 7, further comprising:
the first test data is pre-stored in a first storage module, and is read from the first storage module in response to the start of the test and sent to the test module;
and storing the second test data in a second storage module, and reading the corresponding first test data and the second test data from the first storage module and the second storage module respectively for comparison in response to the completion of second test data collection.
9. The method of claim 7, wherein collecting second test data from the test module comprises:
adding a test data loopback module between an external output interface and an external input interface of the test module according to the interface type, and sending the data of the output interface to the input interface through the test data loopback module;
and acquiring data output by an output interface in the test module pair as second test data.
10. The method of claim 7, wherein collecting second test data from the test module comprises:
and acquiring data output by an external output interface of the test module as the second test data through the test data loopback module.
11. A computer device, comprising:
at least one processor;
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 7 to 10.
12. A computer-readable storage medium, having stored thereon a computer program for, when being executed by a processor, implementing the steps of the method according to any one of the claims 7-10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211143334.5A CN115242681A (en) | 2022-09-20 | 2022-09-20 | System, method and equipment for testing communication module in chip and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211143334.5A CN115242681A (en) | 2022-09-20 | 2022-09-20 | System, method and equipment for testing communication module in chip and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115242681A true CN115242681A (en) | 2022-10-25 |
Family
ID=83682263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211143334.5A Pending CN115242681A (en) | 2022-09-20 | 2022-09-20 | System, method and equipment for testing communication module in chip and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115242681A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115562925A (en) * | 2022-12-06 | 2023-01-03 | 苏州浪潮智能科技有限公司 | Chip interface test system, method, equipment and storage medium |
| CN116938393A (en) * | 2023-09-15 | 2023-10-24 | 湖北芯擎科技有限公司 | Chip detection method, system and storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103780322A (en) * | 2014-01-26 | 2014-05-07 | 中国电子科技集团公司第五十八研究所 | Low-cost high-reliability high-speed network communication chip testing method and circuits |
| US20150243113A1 (en) * | 2014-02-25 | 2015-08-27 | Goodrich Corporation | Systems and methods for built in test equipment for a brake control system |
| CN110069373A (en) * | 2019-04-24 | 2019-07-30 | 苏州浪潮智能科技有限公司 | A kind of BMC automatic test approach and device |
| CN111221694A (en) * | 2020-01-13 | 2020-06-02 | 西安微电子技术研究所 | Built-in self-test method and system for receiving and transmitting path of Ethernet controller |
| CN112269120A (en) * | 2020-11-05 | 2021-01-26 | 深圳市广和通无线股份有限公司 | Interface signal loop test method and device, computer equipment and storage medium |
| CN114297134A (en) * | 2021-11-30 | 2022-04-08 | 山东云海国创云计算装备产业创新中心有限公司 | Chip architecture and signal integrity test method |
-
2022
- 2022-09-20 CN CN202211143334.5A patent/CN115242681A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103780322A (en) * | 2014-01-26 | 2014-05-07 | 中国电子科技集团公司第五十八研究所 | Low-cost high-reliability high-speed network communication chip testing method and circuits |
| US20150243113A1 (en) * | 2014-02-25 | 2015-08-27 | Goodrich Corporation | Systems and methods for built in test equipment for a brake control system |
| CN110069373A (en) * | 2019-04-24 | 2019-07-30 | 苏州浪潮智能科技有限公司 | A kind of BMC automatic test approach and device |
| CN111221694A (en) * | 2020-01-13 | 2020-06-02 | 西安微电子技术研究所 | Built-in self-test method and system for receiving and transmitting path of Ethernet controller |
| CN112269120A (en) * | 2020-11-05 | 2021-01-26 | 深圳市广和通无线股份有限公司 | Interface signal loop test method and device, computer equipment and storage medium |
| CN114297134A (en) * | 2021-11-30 | 2022-04-08 | 山东云海国创云计算装备产业创新中心有限公司 | Chip architecture and signal integrity test method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115562925A (en) * | 2022-12-06 | 2023-01-03 | 苏州浪潮智能科技有限公司 | Chip interface test system, method, equipment and storage medium |
| CN116938393A (en) * | 2023-09-15 | 2023-10-24 | 湖北芯擎科技有限公司 | Chip detection method, system and storage medium |
| CN116938393B (en) * | 2023-09-15 | 2023-12-15 | 湖北芯擎科技有限公司 | Chip detection method, system and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN115242681A (en) | System, method and equipment for testing communication module in chip and storage medium | |
| US9384085B2 (en) | Method, device, and system for monitoring quickpath interconnect link | |
| KR20190131445A (en) | Traffic capture and debugging tools for identifying root causes of device failure during automated testing | |
| KR101614456B1 (en) | Multi-site testing of computer memory devices and serial io ports | |
| CN107077409B (en) | Method and apparatus for multi-interface debugging in an electronic system | |
| CN105808396A (en) | Chip debugging device, debugging method and SOC (System of Chip) chip system | |
| MX2008003299A (en) | Embedded systems debugging. | |
| CN101291261A (en) | Method and system for in-board device testing | |
| US20070011517A1 (en) | Debug system for data tracking | |
| CN105183575A (en) | Processor fault diagnosis method, device and system | |
| CN104298579A (en) | Logic chip and board card device with same | |
| CN114138644A (en) | BMC (baseboard management controller) debugging method, monitoring method, system, device, equipment and medium | |
| CN116627861B (en) | Data processing method and system based on expander, electronic equipment and storage medium | |
| CN115496018A (en) | Multi-version verification method, device and equipment for SoC (System on chip) | |
| CN112685212A (en) | Debugging and tracking method, device and system for processor exception | |
| JP5060021B2 (en) | A universal approach to simulate, emulate and test various serial bus types | |
| WO2020259339A1 (en) | Bus monitoring device and method, storage medium, and electronic device | |
| CN115794530A (en) | Hardware connection testing method, device, equipment and readable storage medium | |
| CN104572515A (en) | Tracking module, method, system and SOC (System-On-Chip) | |
| US20030225566A1 (en) | JTAG server | |
| CN114625592A (en) | Method, system, equipment and storage medium for rapid debugging of FPGA prototype verification | |
| JP2004101203A (en) | Failure analysis system for logic lsi and failure analysis method | |
| Nejedlo et al. | Intel® IBIST, the full vision realized | |
| US7689865B2 (en) | Middlesoft commander | |
| CN116719712B (en) | Processor serial port log output method and device, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |