CN114138644A - BMC (baseboard management controller) debugging method, monitoring method, system, device, equipment and medium - Google Patents
BMC (baseboard management controller) debugging method, monitoring method, system, device, equipment and medium Download PDFInfo
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Abstract
The application discloses a method, a device and a system for debugging a baseboard management controller, a method, a device and a system for monitoring the baseboard management controller, an electronic device and a readable storage medium. The method comprises the step of switching an output pin and a bus of the BMC through a programmable logic device comprising a plurality of debugging buses in advance. Sending the received BMC debugging instruction to a programmable logic device, connecting a bus to be debugged with a debugging bus corresponding to the programmable logic device, and simultaneously cutting off the physical connection between the bus to be debugged and a part to be debugged through an output bus of the programmable logic device; the debugging instruction comprises a debugging protocol and a bus to be debugged. And switching to the bus to be debugged based on the BMC debugging instruction, and receiving data information of the bus to be debugged. And calling a debugging protocol to analyze the data information, and acquiring corresponding target debugging data according to an analysis result so as to respond to the BMC debugging instruction. The method and the device can effectively shorten the software research and development period and reduce the software research and development and debugging cost.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method, an apparatus, and a system for debugging a baseboard management controller, a method, an apparatus, and a system for monitoring a baseboard management controller, an electronic device, and a readable storage medium.
Background
With the continuous development of computer technology, the application of servers in various technical fields, such as internet to financial industry, mobile communication industry to educational fund science research, etc., is more and more extensive. With the development of the application range and the diversity of application scenes of the server, the demands of clients on the server are different, and especially the customization demands are more and more. This results in that the BMC (baseboard management controller) is used as a baseband management system, the components and information to be monitored are increasingly abundant, and the requirement for the performance of the BMC is higher.
In the related art, in the development process of the BMC, the debugging operation of the component to be debugged can be executed only when the component to be debugged, such as a hard disk, has a debugging condition, for example, the component to be debugged is introduced in time, and the software and hardware environment on which the debugging depends is ready. And if the parts to be tested are not introduced timely, the application is difficult, or the testing hardware is limited, the debugging can not be carried out. This results in long development cycle and high development cost of the whole software.
In view of this, how to shorten the software development cycle and reduce the software development and debugging costs is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The application provides a method, a device and a system for debugging a baseboard management controller, a method, a device and a system for monitoring a baseboard management controller, an electronic device and a readable storage medium, which can effectively shorten the software research and development period and reduce the software research and development and debugging cost.
In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:
an embodiment of the present invention provides a method for debugging a baseboard management controller, including:
the output pins and the output bus of the BMC are switched through the programmable logic device in advance; the programmable logic device also comprises a plurality of debugging buses;
sending the received BMC debugging instruction to the programmable logic device so as to connect a bus to be debugged with a debugging bus corresponding to the programmable logic device, and simultaneously cutting off the physical connection between the bus to be debugged and a part to be debugged through an output bus of the programmable logic device; the BMC debugging instruction comprises a debugging protocol and a bus to be debugged;
switching to the bus to be debugged based on the BMC debugging instruction so as to receive data information of the bus to be debugged;
and calling the debugging protocol to analyze the data information, and acquiring corresponding target debugging data according to an analysis result so as to respond to the BMC debugging instruction.
Optionally, before obtaining the corresponding target debugging data according to the analysis result, the method further includes:
when a debugging data configuration command of the component to be debugged is received, judging whether original debugging data of the component to be debugged exists or not;
if the original debugging data of the component to be debugged exists, updating the original debugging data according to the debugging data configuration command;
and if the original debugging data of the component to be debugged does not exist, generating debugging data for the component to be debugged.
Optionally, after obtaining the corresponding target debugging data according to the analysis result, the method further includes:
responding to a data verification instruction, and displaying a data verification page to perform accuracy check on debugging data configured by the component to be debugged and the acquired debugging data;
and the data check page comprises all debugging data of the component to be debugged and the target debugging data.
Optionally, the BMC is built in the server, and the sending the received BMC debugging instruction to the programmable logic device includes:
when BMC debugging is needed and the component to be debugged has debugging conditions, outputting a bus debugging instruction through the BMC, and simultaneously sending the bus debugging instruction to the editable logic device;
and setting the working modes of the bus to be debugged of the BMC and the debugging bus of the programmable logic device corresponding to the bus to be debugged as debugging modes based on the bus debugging instruction.
Optionally, the setting, based on the bus debug instruction, the operating modes of the bus to be debugged of the BMC and the debug bus of the programmable logic device corresponding to the debug bus to be a debug mode includes:
and if the debugging condition of the part to be debugged is restart or power-off, setting the working mode of the bus to be debugged of the BMC and the working mode of the bus to be debugged, which corresponds to the debugging bus of the programmable logic device, to be a debugging mode on the basis of the bus debugging instruction and on the basis of not executing restart operation or power-off operation.
The embodiment of the present invention further provides a device for debugging a baseboard management controller, including:
the pre-deployment module is used for switching an output pin and an output bus of the BMC in advance through the programmable logic device; the programmable logic device also comprises a plurality of debugging buses;
the debugging instruction issuing module is used for sending the received BMC debugging instruction to the programmable logic device so as to connect a bus to be debugged with a debugging bus corresponding to the programmable logic device and simultaneously cut off the physical connection between the bus to be debugged and a part to be debugged through an output bus of the programmable logic device; the BMC debugging instruction comprises a debugging protocol and a bus to be debugged;
the hardware interface switching module is used for switching to the bus to be debugged based on the BMC debugging instruction so as to receive data information of the bus to be debugged;
the data analysis module is used for calling the debugging protocol to analyze the data information;
and the debugging module is used for acquiring corresponding target debugging data according to the analysis result so as to respond to the BMC debugging instruction.
The embodiment of the invention also provides a debugging system of the baseboard management controller, which comprises a BMC, a programmable logic device and a component to be debugged;
an output pin and an output bus of the BMC are connected with an input pin of the programmable logic device, and the output bus of the programmable logic device is connected to the component to be debugged;
the BMC is configured to call a computer program stored in a memory, and execute the step of the baseboard management controller debugging method on the component to be debugged.
Optionally, the programmable logic device includes a first type of output pin and a second type of output pin;
the first type of output pins are connected with each part to be debugged through a corresponding output bus;
and the second type output pin is connected with the input pin of the BMC through a corresponding output bus.
Optionally, the system further comprises a conversion chip;
the output pin of the programmable logic device is connected with the conversion chip;
if the BMC is in a debugging mode, the conversion chip is connected with an input pin of the BMC;
and if the BMC is not in the debugging mode, the conversion chip is connected with each component to be debugged.
Another aspect of the embodiments of the present invention provides a method for monitoring a baseboard management controller, including:
when monitoring that the BMC is abnormal, setting the BMC to enter a debugging mode, and debugging a target component by using any one of the substrate management controller debugging methods;
acquiring feedback information of the BMC in the debugging mode;
and if the feedback information is normal, judging that the information acquisition logic, the information processing logic and the bottom layer driving function of the BMC are normal.
An embodiment of the present invention further provides a monitoring apparatus for a baseboard management controller, including:
the debugging module is used for setting the BMC to enter a debugging mode when monitoring that the BMC is monitored to be abnormal, and debugging a target component by using any one of the debugging methods of the baseboard management controllers;
the information acquisition module is used for acquiring feedback information of the BMC in the debugging mode;
and the fault diagnosis module is used for judging that the information acquisition logic, the information processing logic and the bottom layer driving function of the BMC are normal if the feedback information is normal.
The embodiment of the invention also provides a monitoring system of the substrate management controller, which comprises a server, a programmable logic device and a part to be debugged;
the server is internally provided with a BMC, an output pin and an output bus of an SOC chip operated by the BMC are both connected to an input pin of the programmable logic device, and the output bus of the programmable logic device is connected to the component to be debugged;
the BMC implements the steps of the baseboard management controller monitoring method as described above when executing a computer program stored in a memory.
An embodiment of the present invention further provides an electronic device, which includes a processor and a memory, where the processor is configured to implement the baseboard management controller debugging method and/or the baseboard management controller monitoring method according to any one of the foregoing embodiments when executing the computer program stored in the memory.
Finally, an embodiment of the present invention provides a readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the method for debugging a baseboard management controller and/or the method for monitoring a baseboard management controller as described in any previous item are implemented.
The technical scheme provided by the application has the advantages that the debugging data of the virtual components corresponding to the components to be debugged are preconfigured in the BMC, the programmable logic device can be simultaneously connected with the components to be debugged and the BMC, whether the programmable logic device is connected with the actual components or interacted with the virtual components in the BMC is determined according to actual requirements, and therefore the method can be used as a self-testing means when the components to be tested do not have testing conditions, the accuracy of developed codes such as upper-layer application and bottom-layer driven processing logic can be at least guaranteed, the method is simple and convenient, the execution is easy, the software development period can be effectively shortened, and the software development and debugging cost is reduced.
In addition, the embodiment of the invention also provides a corresponding implementation device, electronic equipment and a readable storage medium for the debugging method of the baseboard management controller, so that the method has higher practicability, and the device, the electronic equipment and the readable storage medium have corresponding advantages.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the related art, the drawings required to be used in the description of the embodiments or the related art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flowchart illustrating a method for debugging a bmc according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a frame structure of a BMC according to an embodiment of the present invention;
fig. 3 is a schematic flowchart illustrating a monitoring method for a bmc according to an embodiment of the present invention;
fig. 4 is a structural diagram of an embodiment of a baseboard management controller debugging apparatus according to an embodiment of the present invention;
fig. 5 is a structural diagram of a monitoring apparatus of a bmc according to an embodiment of the present invention;
fig. 6 is a block diagram of an embodiment of an electronic device according to an embodiment of the present invention;
fig. 7 is a structural diagram of a substrate management controller debugging system according to an embodiment of the present invention;
fig. 8 is a structural diagram of a substrate management controller monitoring system according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and claims of this application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may include other steps or elements not expressly listed.
Having described the technical solutions of the embodiments of the present invention, various non-limiting embodiments of the present application are described in detail below.
Referring to fig. 1, fig. 1 is a schematic flowchart of a baseboard management controller debugging method according to an embodiment of the present invention, where the embodiment of the present invention includes the following:
in order to debug an entity component without a debugging condition, a self-test system process module is set up in the BMC in advance, and the self-test system process module supports the debugging method of the baseboard management controller according to the following embodiments, a software architecture of the self-test system process module is as shown in fig. 2, the self-test system process module is used for realizing a related function of a virtual component, and the architecture may include a protocol layer, a hardware interface layer, a debugging information interface layer, and a command control interface. Fig. 2 is an example of a CPLD (Complex Programmable Logic Device), where each actual component shown in the figure is a component to be debugged, such as a hard disk. In the CPLD, a bus input interface and a bus output interface are external interfaces of the CPLD, the bus input interface interacts with the BMC, and the bus output interface is connected to an actual component. The CPLD control conversion logic is used for controlling the CPLD to be in a debugging mode or a non-debugging mode, the debugging mode is used for interacting with a virtual component inside the BMC, and the non-debugging mode is used for connecting and interacting between the BMC and each actual component through the CPLD. The control command input interface receives a control command sent by the BMC.
In the BMC, the control command module is used to control the BMC to send a control command to the CPLD and process an external input command, and the database may be a Redis (reiteration) database used to store pre-configured debug data. The hardware interface layer mainly implements interaction and switching of specific buses, and buses used for monitoring the same component as one protocol are also different, for example, for monitoring RAID, i2c (Inter-Integrated Circuit bus) buses may be used, or PCIE (peripheral component interconnect express) buses may be used for distinguishing and shielding at the hardware interface layer, and the module may be switched to a corresponding bus according to a specific command issued by a user to receive corresponding data and information. The protocol layers are used to implement different protocol implementations, which may include the reception and parsing of protocol frames. For example, for monitoring of different components, MCTP (management component transport protocol) Over PCIE may be used, i2c may be used, or the functions such as reading the temperature of the EMC1413 and the like are required to perform development and debugging of relevant protocols according to a chip manual of the EMC1413 by directly responding to data corresponding to spec (Standard Performance Evaluation Corporation) organization of a hardware chip; the received data is parsed using various protocols supported by the protocol layers. And the debugging information interface layer is used for realizing the configuration function of the actual component debugging data. When reading information of different components, different test data needs to be configured to the components. In this embodiment, related data may be configured through a web or redfis Interface or an IPMI (Intelligent Platform Management Interface) command, and the data may be written into a database, such as a Redis database shown in fig. 2, and when the hardware Interface layer receives data fed back by the programmable logic device and is analyzed by the protocol layer, a related debug data framing may be obtained from the database to respond. The command control interface is used for receiving an externally issued control command such as a command issued by a user, and mainly realizes a series of IPMI commands and restful (representational State transfer) interface commands. Starting the debugging process of the BMC, and controlling a hardware interface layer to adopt a correct bus and bus protocol, debugging data and the like. Through the BMC architecture, codes do not need to be frequently modified for the programmable logic devices of specific models, only corresponding connection is needed according to the bus type and the bus condition of the server, and actual component types and interaction protocols do not need to be concerned.
S101: the output pin and the output bus of the BMC are switched through the programmable logic device in advance.
In this embodiment, the BMC is not directly connected to the actual components, but is switched through the programmable logic device. The programmable logic device may employ a CPLD in view of cost and implementation complexity. The programmable logic device of the present application may include a plurality of debug buses in addition to the input pins and the output pins. All output pins and output buses of the BMC are connected to input pins of the programmable logic device, that is, pins and buses externally presented by the BMC, such as an i2c bus, a spi (Serial Peripheral Interface) bus, an lpc (low pin count bus) bus, a pci bus, an SIO (super input output chip) and a General-purpose GPIO (General-purpose input/output) are used as inputs of the programmable logic device, such as the CPLD. The output pin is used for connecting with an actual component through an output bus or connecting to an input pin of the BMC.
S102: and sending the received BMC debugging instruction to the programmable logic device so as to connect the bus to be debugged with a debugging bus corresponding to the programmable logic device, and simultaneously cutting off the physical connection between the bus to be debugged and the part to be debugged through an output bus of the programmable logic device.
In this embodiment, when a certain actual component is to be debugged, a user may issue a BMC debug instruction to the BMC, and specify a debug protocol, a bus to be debugged, a component to be debugged, a debug time, and the like in the BMC debug instruction. When the programmable logic device is not in the debugging mode, the programmable logic device is physically connected with the actual component through the output bus, and if the programmable logic device is in the debugging mode, the programmable logic device interacts with the virtual component inside the BMC, and the physical connection between the bus to be debugged and the component to be debugged through the output bus of the programmable logic device needs to be cut off. The programmable logic device CPLD can set a corresponding output bus according to the number of the input buses and the bus type, wherein the output bus is connected to specific external equipment. In addition, another type of debugging bus output is preset by the CPLD, the bus output is switched according to a command sent by the BMC, and if the CPLD enters the BMC debugging mode, the corresponding bus is connected to the corresponding debugging bus according to the command sent by the BMC. For example, if i2c2 related functions of the BMC need to be debugged, the CPLD needs to connect the i2c2 bus input to the debug i2c bus while disconnecting the i2c2 from the actual connection components.
S103: and switching to the bus to be debugged based on the BMC debugging instruction so as to receive data information of the bus to be debugged.
After the programmable logic device and the BMC are connected in the steps, the BMC switches the bus at the hardware interface layer and switches the bus to be debugged, and therefore data fed back by the programmable logic device through the bus to be debugged can be received.
S104: and calling a debugging protocol to analyze the data information, and acquiring corresponding target debugging data according to an analysis result so as to respond to the BMC debugging instruction.
And calling a corresponding debugging protocol to analyze according to the data information fed back by the programmable logic device in the previous step to obtain a data analysis result, and acquiring debugging data of the component to be debugged from the BMC according to the analysis result. The target debug data in this step is debug data of the component to be debugged acquired from the BMC, and may be the same as or different from the pre-configured debug data, and if not, it proves that the BMC data acquisition logic is incorrect.
In the technical scheme provided by the embodiment of the invention, the debugging data of the virtual component corresponding to each component to be debugged is preconfigured in the BMC, the programmable logic device can be simultaneously connected with the component to be debugged and the BMC, and whether the programmable logic device is connected with the actual component or interacts with the virtual component in the BMC is determined according to actual requirements, so that the method can be used as a self-testing means in the development process of the BMC when the component to be tested does not have a testing condition, at least the accuracy of a developed code such as an upper-layer application and a bottom-layer driven processing logic can be ensured, the method is simple and convenient, the execution is easy, the software development cycle can be effectively shortened, and the software development and debugging cost is reduced.
In order to further improve the debugging convenience and reduce the debugging cost, based on the above embodiment, before obtaining the corresponding target debugging data according to the parsing result, the method may further include:
when a debugging data configuration command of a component to be debugged is received, judging whether original debugging data of the component to be debugged exists or not;
if the original debugging data of the component to be debugged exists, updating the original debugging data according to a debugging data configuration command;
and if the original debugging data of the component to be debugged does not exist, generating debugging data for the component to be debugged.
In this embodiment, the original debug data refers to debug data configured for a component to be debugged before the current time, and the debug data configuration command may be debug data of a newly added entity component or may be modification or deletion of the original debug data.
It can be understood that, the target debug data obtained according to the analysis result is not completely the same as the debug data of the component to be debugged, which is configured in advance in the BMC, for example, the data reading logic of the BMC is faulty, and based on this, the present application also provides an embodiment of the accuracy check, which may include the following contents:
responding to the data checking instruction, and displaying a data checking page to check the accuracy of the debugging data configured by the component to be debugged and the acquired debugging data;
the data check page comprises all debugging data and target debugging data of the part to be debugged.
In this embodiment, the data verification instruction is issued by the user, and the data verification page may be a web page or a BMC management page, which does not affect the implementation of the present application. The debug data configured by the component to be debugged is debug data configured in the BMC in advance, and the obtained debug data is data obtained by executing step S104. The debugging data of the virtual component in the BMC has a good and powerful man-machine interaction interface, the configuration of related data is realized through a web interface, an ipmi interface and other series interfaces, accuracy check can be performed according to the configured data and the data acquired by the BMC, and the debugging accuracy is improved.
In the above embodiments, the debugging operations performed on the actual components by the BMC in the BMC development process are targeted. For the developed BMC built in the server, the process of sending the received BMC debugging instruction to the programmable logic device may include:
when BMC debugging is needed and the to-be-debugged component has debugging conditions, outputting a bus debugging instruction through the BMC, and simultaneously sending the bus debugging instruction to the editable logic device; and setting the working modes of the bus to be debugged of the BMC and the debugging bus of the programmable logic device corresponding to the debugging bus as the debugging modes based on the bus debugging instruction.
In this embodiment, the server in normal operation does not need to start a debugging process of the BMC, and the editable logic device, such as the CPLD, does not need to enter the debugging mode, that is, the function does not affect the normal operation of the server and the normal monitoring of the BMC on each entity component, and only needs to issue a bus debugging command through the BMC when the server needs to be debugged and has a debugging condition, and notify the programmable logic device, such as the CPLD, to enable the BMC and the bus corresponding to the programmable logic device to enter the debugging mode. The debugging condition is that the software and hardware environments of the part to be debugged are ready, such as version, protocol, physical connection and the like. After entering the debugging mode, the normal monitoring and operation of other non-debugging buses are not influenced, the influence links are less, and the stable operation of the server can be ensured.
In addition, some probabilistic problems and phenomena disappear after the BMC is restarted, the problems and phenomena cannot be well captured and reproduced, monitoring of many parts can be debugged after power failure, in this case, the debugging difficulty of the BMC is increased, a large amount of manpower, material resources and financial resources are wasted to solve, and the debugging cost of the whole BMC is increased. Based on this, the present application also provides another embodiment, including:
and if the debugging condition of the part to be debugged is restart or power-off, setting the working mode of the bus to be debugged of the BMC and the working mode of the bus to be debugged, which corresponds to the debugging bus of the programmable logic device, to be a debugging mode on the basis of the bus debugging instruction and on the basis of not executing restart operation or power-off operation.
In this embodiment, for the situation that the component can be replaced and debugged only by restarting or powering off, the embodiment allows forcing a certain bus to enter a debugging mode under the normal operation condition, and after entering the debugging mode, the embodiment can debug by reading the relevant information in the virtual component in the BMC, so that the influence on the whole server is small, and the debugging cost and the debugging difficulty of the BMC can be reduced.
It can be understood that manufacturers of running components in the server are not uniform at present, and the adopted interaction protocols are various, even the protocols of components with different models of the same manufacturer are also various. To accommodate this diversification, BMCs have increasingly complex monitoring code logic within them, and even if architectures with excellent extensibility and redundancy are used, various problems associated with component interaction can arise during field operations, especially when firmware versions in components are inconsistent or upgraded or even components fail. Therefore, a problem occurs in monitoring of the BMC, the client feeds back that the BMC is monitored abnormally, and the BMC cannot well judge or evidence the abnormal monitoring or evidence obtaining result from the inconsistent version of the component, or a related series of phenomena caused by the problem of the component, or an abnormal phenomenon caused by the problem of the monitoring logic or driver of the BMC. In order to solve the problem, the BMC can only be analyzed and debugged by relying on larger manpower and material resources, and as a result, the whole process is finally positioned to be a component or other related problems, the logic of the BMC is in normal operation without any problem, or a component developer inputs larger manpower but is finally positioned to be the BMC. This results in that after monitoring the fault, the whole fault is eliminated or the fault location efficiency is low, which is not favorable for the stable operation of the server. Based on the above, the present application further provides a monitoring method for a baseboard management controller, please
Referring to fig. 3, fig. 3 is a schematic flow chart of a monitoring method for a BMC according to an embodiment of the present invention, where the embodiment of the present invention is applicable to a server where a BMC is located, and specifically includes the following contents:
when the server is designed, all output pins and buses of the SOC chip operated by the BMC are switched through the programmable logic device such as the CPLD, namely, pins and buses such as i2c buses and the like presented to the outside of the processor where the BMC is located are used as the input of the programmable logic device.
S301: and when monitoring that the BMC monitoring is abnormal, setting the BMC to enter a debugging mode.
S302: the target component is debugged using method steps in a baseboard management controller debugging method embodiment as any one of the previous.
S303: and acquiring feedback information of the BMC in the debugging mode.
S304: and if the feedback information is normal, judging that the information acquisition logic, the information processing logic and the bottom layer driving function of the BMC are normal.
In this embodiment, the target component may be any hardware that has a debug condition and is monitored by the BMC. If the BMC monitors abnormal conditions, self-evidence clearing and problem troubleshooting can be performed through the method provided by the embodiment. When the BMC is in the debugging mode, the feedback information of the virtual component realized by the BMC is normal, at least, the information acquisition and processing logic of the BMC including the bottom layer drive has no problem, namely, the monitoring abnormity caused by the abnormal logic of the BMC is eliminated. This requires the component developer to access the analysis and debugging. When the virtual component feedback information realized by the BMC is abnormal after the BMC is in the debugging mode, the fact that the information acquisition and processing logic of the BMC including the bottom layer drive is problematic is shown, the BMC can be preferentially subjected to abnormity detection, and manpower, material resources and financial resources for debugging and problem troubleshooting are reduced, so that the troubleshooting efficiency of the server can be improved, and the fault repairing efficiency of the server is improved.
It should be noted that, in the present application, there is no strict sequential execution order among the steps, and as long as a logical order is met, the steps may be executed simultaneously or according to a certain preset order, and fig. 1 and fig. 3 are only schematic manners, and do not represent only such an execution order.
In order to make the technical solutions of the present application more clearly apparent to those skilled in the art, the present application also provides an illustrative example to illustrate the technical solutions, which may include:
when detecting that the BMC has an error through a PCIE bus monitoring RAID (disk array), the RAID needs to be debugged, and accordingly, a bus to be debugged is a PCIE bus. And the user issues a debugging instruction to the BMC, starts a debugging mode function, and specifies a debugging protocol and a bus to be debugged. Then the BMC enters a debugging mode, switches the current bus to the PCIE bus through a hardware interface layer, and issues a debugging command to the CPLD. At the moment, the first output bus of the CPLD is connected with the RAID, the CPLD enters a debugging mode after receiving a debugging instruction, the physical connection between the first output bus and the hard disk is cut off, and the PCIE bus is connected with the corresponding debugging bus in the CPLD. The CPLD feeds data back to the BMC through the debugging bus, the BMC calls a corresponding protocol of the protocol layer to analyze the received data, and the debugging data of the RAID is read in the database based on the analysis result.
Therefore, the embodiment of the invention can effectively shorten the software development period and reduce the software development and debugging cost.
The embodiment of the invention also provides a corresponding device for the debugging method of the substrate management controller, thereby further ensuring that the method has higher practicability. Wherein the means can be described separately from the functional module point of view and the hardware point of view. In the following, the baseboard management controller debugging apparatus provided by the embodiment of the present invention is introduced, and the baseboard management controller debugging apparatus described below and the baseboard management controller debugging method described above may be referred to correspondingly.
Based on the angle of the functional module, referring to fig. 4, fig. 4 is a structural diagram of a baseboard management controller debugging apparatus according to an embodiment of the present invention, in a specific implementation manner, the apparatus may include:
the pre-deployment module 401 is used for pre-switching an output pin and an output bus of the BMC through the programmable logic device; the programmable logic device also includes a plurality of debug buses.
A debug instruction issuing module 402, configured to send the received BMC debug instruction to the programmable logic device, so as to connect the bus to be debugged with a debug bus corresponding to the programmable logic device, and simultaneously cut off the physical connection between the bus to be debugged and the component to be debugged through an output bus of the programmable logic device; the BMC debugging instruction comprises a debugging protocol and a bus to be debugged.
And a hardware interface switching module 403, configured to switch to the bus to be debugged based on the BMC debugging instruction, so as to receive data information of the bus to be debugged.
And the data analysis module 404 is configured to invoke a debugging protocol to analyze the data information.
And the debugging module 405 is configured to obtain corresponding target debugging data according to the analysis result, so as to respond to the BMC debugging instruction.
Optionally, in some embodiments of this embodiment, the apparatus may further include a data configuration module, configured to determine whether there is original debug data of the component to be debugged when a debug data configuration command of the component to be debugged is received; if the original debugging data of the component to be debugged exists, updating the original debugging data according to a debugging data configuration command; and if the original debugging data of the component to be debugged does not exist, generating debugging data for the component to be debugged.
Optionally, in other embodiments of this embodiment, the apparatus may further include a verification module, for example, configured to respond to the data verification instruction, and display a data verification page, so as to perform accuracy check on the debugging data configured by the component to be debugged and the acquired debugging data; the data check page comprises all debugging data and target debugging data of the part to be debugged.
Optionally, in some other embodiments of this embodiment, the debug instruction issuing module 402 may be further configured to: the BMC is arranged in the server, when BMC debugging is needed and a component to be debugged has a debugging condition, a bus debugging instruction is output through the BMC, and the bus debugging instruction is sent to the editable logic device; and setting the working modes of the bus to be debugged of the BMC and the debugging bus of the programmable logic device corresponding to the debugging bus as the debugging modes based on the bus debugging instruction.
As an optional implementation manner of the foregoing embodiment, the debug instruction issuing module 402 may be further configured to: and if the debugging condition of the part to be debugged is restart or power-off, setting the working mode of the bus to be debugged of the BMC and the working mode of the bus to be debugged, which corresponds to the debugging bus of the programmable logic device, to be a debugging mode on the basis of the bus debugging instruction and on the basis of not executing restart operation or power-off operation.
In addition, this embodiment further provides a monitoring apparatus for a bmc, and fig. 5 is a structural diagram of a debugging apparatus for a bmc according to an embodiment of the present invention in a specific implementation manner, where the apparatus may include:
the debugging module 501 is configured to set the BMC to enter a debugging mode when monitoring that the BMC is abnormal, and debug the target component by using any one of the foregoing methods for debugging the BMC.
The information obtaining module 502 is configured to obtain feedback information that the BMC is in the debug mode.
And the fault diagnosis module 503 is configured to determine that the information acquisition logic, the information processing logic and the bottom layer driving function of the BMC are normal if the feedback information is normal.
The functions of the functional modules of the baseboard management controller debugging device and the baseboard management controller monitoring device in the embodiments of the present invention can be specifically implemented according to the method in the embodiments of the method, and the specific implementation process can refer to the related description of the embodiments of the method, which is not described herein again.
Therefore, the embodiment of the invention can effectively shorten the software development period and reduce the software development and debugging cost.
The baseboard management controller debugging apparatus mentioned above is described from the perspective of a functional module, and further, the present application also provides an electronic device described from the perspective of hardware. Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 6, the electronic device includes a memory 60 for storing a computer program; the processor 61 is configured to implement the steps of the baseboard management controller debugging method and/or the baseboard management controller monitoring method according to any one of the above embodiments when executing the computer program.
The processor 61 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the processor 61 may also be a controller, a microcontroller, a microprocessor or other data processing chip, and the like. The processor 61 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 61 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 61 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content that the display screen needs to display. In some embodiments, the processor 61 may further include an AI (Artificial Intelligence) processor for processing computing operations related to machine learning.
Memory 60 may include one or more computer-readable storage media, which may be non-transitory. Memory 60 may also include high speed random access memory as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. The memory 60 may in some embodiments be an internal storage unit of the electronic device, for example a hard disk of a server. The memory 60 may also be an external storage device of the electronic device in other embodiments, such as a plug-in hard disk provided on a server, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the memory 60 may also include both internal storage units of the electronic device and external storage devices. The memory 60 may be used for storing various data and application software installed in the electronic device, such as: the code of the program that executes the vulnerability handling method, etc. may also be used to temporarily store data that has been output or is to be output. In this embodiment, the memory 60 is at least used for storing a computer program 601, wherein the computer program is loaded and executed by the processor 61, and then the relevant steps of the baseboard management controller debugging method and/or the baseboard management controller monitoring method disclosed in any one of the foregoing embodiments can be implemented. In addition, the resources stored by the memory 60 may also include an operating system 602, data 603, and the like, and the storage may be transient storage or permanent storage. Operating system 602 may include Windows, Unix, Linux, etc., among others. The data 603 may include, but is not limited to, data corresponding to a baseboard management controller debugging result and/or a baseboard management controller monitoring result, and the like.
In some embodiments, the electronic device may further include a display 62, an input/output interface 63, a communication interface 64, otherwise known as a network interface, a power supply 65, and a communication bus 66. The display 62 and the input/output interface 63, such as a Keyboard (Keyboard), belong to a user interface, and the optional user interface may also include a standard wired interface, a wireless interface, and the like. Alternatively, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch device, or the like. The display, which may also be referred to as a display screen or display unit, as appropriate, is used for displaying information processed in the electronic device and for displaying a visualized user interface. The communication interface 64 may optionally include a wired interface and/or a wireless interface, such as a WI-FI interface, a bluetooth interface, etc., typically used to establish a communication link between an electronic device and other electronic devices. The communication bus 66 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 6, but this is not intended to represent only one bus or type of bus.
Those skilled in the art will appreciate that the configuration shown in fig. 6 is not intended to be limiting of the electronic device and may include more or fewer components than those shown, such as a sensor 67 that performs various functions.
The functions of the functional modules of the electronic device according to the embodiments of the present invention may be specifically implemented according to the method in the above method embodiments, and the specific implementation process may refer to the description related to the above method embodiments, which is not described herein again.
Therefore, the embodiment of the invention can effectively shorten the software development period and reduce the software development and debugging cost.
It is to be understood that, if the baseboard management controller debugging method in the above embodiments is implemented in the form of a software functional unit and sold or used as a stand-alone product, it may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application may be substantially or partially implemented in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods of the embodiments of the present application, or all or part of the technical solutions. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), an electrically erasable programmable ROM, a register, a hard disk, a multimedia card, a card type Memory (e.g., SD or DX Memory, etc.), a magnetic Memory, a removable magnetic disk, a CD-ROM, a magnetic or optical disk, and other various media capable of storing program codes.
Accordingly, an embodiment of the present invention further provides a readable storage medium, which stores a computer program, where the computer program is executed by a processor, and the method for debugging a baseboard management controller and/or the method for monitoring a baseboard management controller according to any of the above embodiments.
An embodiment of the present invention further provides a baseboard management controller debugging system, please refer to fig. 7, which may include:
the baseboard management controller debugging system may include a BMC71, a programmable logic device 72, and a component to be debugged 73. The output pin and the output bus of the BMC71 are connected to the input pin of the programmable logic device 72, and the output bus of the programmable logic device 72 is connected to the component to be debugged 73.
The BMC72 is configured to call a computer program stored in a memory, and execute the steps of any one of the embodiments of the baseboard management controller debugging method on a component to be debugged.
The bus switching mode of the programmable logic device 72 may include internal switching and external switching according to the kind of the output pin, the first: the programmable logic device comprises a first class output pin and a second class output pin; the first class of output pins are connected with each part to be debugged through a corresponding output bus; the second type output pin is connected with the input pin of the BMC through a corresponding output bus. And the second method comprises the following steps: the programmable logic device only comprises an output pin, and the whole system can also comprise a conversion chip. The output pin of the programmable logic device is connected with the conversion chip; if the BMC is in a debugging mode, the conversion chip is connected with an input pin of the BMC; and if the BMC is not in the debugging mode, the conversion chip is connected with each component to be debugged.
Finally, an embodiment of the present invention further provides a baseboard management controller management system, please refer to fig. 8, which includes:
a baseboard management controller monitoring system can include a server 81, a programmable logic device 82, and a component 83 to be debugged. The BMC is built in the server 81, an output pin and an output bus of an SOC chip operated by the BMC are both connected to an input pin of the programmable logic device, and an output bus of the programmable logic device 82 is connected to the component 83 to be debugged. The BMC implements the steps in the foregoing baseboard management controller monitoring method embodiments when used to execute a computer program stored in a memory.
In this embodiment, the programmable logic device, such as a CPLD, also includes two bus control modes, one of which is to internally implement bus direction control. That is, the CPLD includes two types of pins, one type is an input pin, the other type is an output pin, the input pin has only one set (which may include i2c bus, peci bus, etc.), the output pin includes two sets, one set is connected to the actual component device (this set also includes i2c bus, peci bus, etc.), the other set is connected to the input pin of the BMC, the CPLD output interacts with the actual component or interacts with the BMC internal module in the actual application process, and is controlled by the CPLD, and the control instruction of the CPLD is sent by the BMC. The second scheme is as follows: and a specific chip is connected outside the CPLD to realize the control of the bus trend. Namely, the CPLD includes two types of pins, one type is an input pin, the other type is an output pin, the input pin has only one group (including i2c bus, peci bus, etc.), the output pin includes one group (this group also includes i2c bus, peci bus, etc.), this group of output bus is connected to a specific conversion chip, this chip realizes the interaction of the bus to the component or the control of the interaction with the debugging component of the BMC, this chip sends the instruction control through the CPLD, and the CPLD sends the instruction control by the BMC.
The functions of the functional modules of the system according to the embodiment of the present invention may be specifically implemented according to the method in the embodiment of the method, and the specific implementation process may refer to the description related to the embodiment of the method, which is not described herein again.
Therefore, the embodiment of the invention can effectively shorten the software development period and reduce the software development and debugging cost.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. For hardware including devices and electronic equipment disclosed by the embodiment, the description is relatively simple because the hardware includes the devices and the electronic equipment correspond to the method disclosed by the embodiment, and the relevant points can be obtained by referring to the description of the method.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The foregoing details are provided for a baseboard management controller debugging method, device and system, a baseboard management controller monitoring method, device and system, an electronic device, and a readable storage medium. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present application.
Claims (14)
1. A debugging method of a baseboard management controller is characterized by comprising the following steps:
the output pins and the output bus of the BMC are switched through the programmable logic device in advance; the programmable logic device also comprises a plurality of debugging buses;
sending the received BMC debugging instruction to the programmable logic device so as to connect a bus to be debugged with a debugging bus corresponding to the programmable logic device, and simultaneously cutting off the physical connection between the bus to be debugged and a part to be debugged through an output bus of the programmable logic device; the BMC debugging instruction comprises a debugging protocol and a bus to be debugged;
switching to the bus to be debugged based on the BMC debugging instruction so as to receive data information of the bus to be debugged;
and calling the debugging protocol to analyze the data information, and acquiring corresponding target debugging data according to an analysis result so as to respond to the BMC debugging instruction.
2. The baseboard management controller debugging method of claim 1, wherein before obtaining the corresponding target debugging data according to the parsing result, the method further comprises:
when a debugging data configuration command of the component to be debugged is received, judging whether original debugging data of the component to be debugged exists or not;
if the original debugging data of the component to be debugged exists, updating the original debugging data according to the debugging data configuration command;
and if the original debugging data of the component to be debugged does not exist, generating debugging data for the component to be debugged.
3. The baseboard management controller debugging method of claim 2, wherein after obtaining the corresponding target debugging data according to the parsing result, further comprising:
responding to a data verification instruction, and displaying a data verification page to perform accuracy check on debugging data configured by the component to be debugged and the acquired debugging data;
and the data check page comprises all debugging data of the component to be debugged and the target debugging data.
4. The baseboard management controller debugging method of any one of claims 1 to 3, wherein the BMC is built in a server, and the sending the received BMC debugging command to the programmable logic device comprises:
when BMC debugging is needed and the component to be debugged has debugging conditions, outputting a bus debugging instruction through the BMC, and simultaneously sending the bus debugging instruction to the editable logic device;
and setting the working modes of the bus to be debugged of the BMC and the debugging bus of the programmable logic device corresponding to the bus to be debugged as debugging modes based on the bus debugging instruction.
5. The baseboard management controller debugging method of claim 4, wherein setting the operating modes of the bus to be debugged of the BMC and the bus to be debugged corresponding to the debugging bus of the programmable logic device to the debugging modes based on the bus debugging instruction comprises:
and if the debugging condition of the part to be debugged is restart or power-off, setting the working mode of the bus to be debugged of the BMC and the working mode of the bus to be debugged, which corresponds to the debugging bus of the programmable logic device, to be a debugging mode on the basis of the bus debugging instruction and on the basis of not executing restart operation or power-off operation.
6. A baseboard management controller debugging device is characterized by comprising:
the pre-deployment module is used for switching an output pin and an output bus of the BMC in advance through the programmable logic device; the programmable logic device also comprises a plurality of debugging buses;
the debugging instruction issuing module is used for sending the received BMC debugging instruction to the programmable logic device so as to connect a bus to be debugged with a debugging bus corresponding to the programmable logic device and simultaneously cut off the physical connection between the bus to be debugged and a part to be debugged through an output bus of the programmable logic device; the BMC debugging instruction comprises a debugging protocol and a bus to be debugged;
the hardware interface switching module is used for switching to the bus to be debugged based on the BMC debugging instruction so as to receive data information of the bus to be debugged;
the data analysis module is used for calling the debugging protocol to analyze the data information;
and the debugging module is used for acquiring corresponding target debugging data according to the analysis result so as to respond to the BMC debugging instruction.
7. A debugging system of a baseboard management controller is characterized by comprising a BMC, a programmable logic device and a component to be debugged;
an output pin and an output bus of the BMC are connected with an input pin of the programmable logic device, and the output bus of the programmable logic device is connected to the component to be debugged;
the BMC is used for calling a computer program stored in a memory and executing the steps of the baseboard management controller debugging method according to any one of claims 1 to 5 on the component to be debugged.
8. The baseboard management controller debugging system of claim 7, wherein the programmable logic device comprises a first class of output pins and a second class of output pins;
the first type of output pins are connected with each part to be debugged through a corresponding output bus;
and the second type output pin is connected with the input pin of the BMC through a corresponding output bus.
9. The baseboard management controller debugging system of claim 7, further comprising a translation chip;
the output pin of the programmable logic device is connected with the conversion chip;
if the BMC is in a debugging mode, the conversion chip is connected with an input pin of the BMC;
and if the BMC is not in the debugging mode, the conversion chip is connected with each component to be debugged.
10. A monitoring method of a baseboard management controller is characterized by comprising the following steps:
when monitoring that the BMC is abnormal, setting the BMC to enter a debugging mode, and debugging a target component by using the debugging method of the baseboard management controller according to any one of claims 1 to 5;
acquiring feedback information of the BMC in the debugging mode;
and if the feedback information is normal, judging that the information acquisition logic, the information processing logic and the bottom layer driving function of the BMC are normal.
11. A baseboard management controller monitoring apparatus, comprising:
the debugging module is used for setting the BMC to enter a debugging mode when monitoring that the BMC is monitored to be abnormal, and debugging a target component by using the debugging method of the baseboard management controller according to any one of claims 1 to 5;
the information acquisition module is used for acquiring feedback information of the BMC in the debugging mode;
and the fault diagnosis module is used for judging that the information acquisition logic, the information processing logic and the bottom layer driving function of the BMC are normal if the feedback information is normal.
12. A monitoring system of a substrate management controller is characterized by comprising a server, a programmable logic device and a component to be debugged;
the server is internally provided with a BMC, an output pin and an output bus of an SOC chip operated by the BMC are both connected to an input pin of the programmable logic device, and the output bus of the programmable logic device is connected to the component to be debugged;
the BMC when executing a computer program stored in a memory implements the steps of the baseboard management controller monitoring method of claim 10.
13. An electronic device comprising a processor and a memory, the processor being configured to implement the steps of the baseboard management controller debugging method according to any one of claims 1 to 5 and/or the baseboard management controller monitoring method according to claim 10 when executing the computer program stored in the memory.
14. A readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the baseboard management controller debugging method according to any one of claims 1 to 5 and/or the baseboard management controller monitoring method according to claim 10.
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