CN115129552B - I2C bus transmission status monitoring method, device, equipment and storage medium - Google Patents
I2C bus transmission status monitoring method, device, equipment and storage medium Download PDFInfo
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- CN115129552B CN115129552B CN202210763829.1A CN202210763829A CN115129552B CN 115129552 B CN115129552 B CN 115129552B CN 202210763829 A CN202210763829 A CN 202210763829A CN 115129552 B CN115129552 B CN 115129552B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3041—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is an input/output interface
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
- G06F11/3093—Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes
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Abstract
The invention discloses a transmission state monitoring method of an I2C bus, which comprises the following steps: transmitting system management bus information of the baseboard management controller to the complex programmable logic device; the system management bus information is sent to each slave device through an I2C Switch chip virtually obtained in the complex programmable logic device; reading system management bus information corresponding to each slave device from a system management bus interface corresponding to each slave device respectively by using the FPGA; and determining the I2C bus transmission state between the baseboard management controller and each slave device according to the system management bus information. By applying the transmission state monitoring method of the I2C bus, the problem positioning efficiency is improved, the development efficiency of products is improved, the development period of the products is shortened, and the maintenance of the later products is facilitated. The invention also discloses a device, equipment and a storage medium for monitoring the transmission state of the I2C bus, which have corresponding technical effects.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, a device, and a computer readable storage medium for monitoring a transmission state of an I2C bus.
Background
At present, the server plays a vital role in the life of people, such as mobile payment, mobile phone and computer communication, map navigation and the like, which are not separated from the ultra-strong computing power of the server. With the progress of science and technology, the functions of the server are more and more complex, the accessed equipment and used devices are more and more, and the stability requirement on the server is higher and more. Information transfer between different devices in a server has an important bus protocol called an I2C (Inter-INTEGRATED CIRCUIT) bus, which is a two-wire serial bus for connecting a controller and peripheral devices thereof for master-slave communication. I2C has two buses in total: one serial data line SDA (Serial Data), one serial clock line SCL (Serial Clock Line), SDA is the data line, used to transfer data, SCL is the clock line, used to control the timing of data transmission. All serial data lines SDA connected to the I2C bus devices are connected to the SDA of the bus, and the clock line SCL of each device is connected to the SCL of the bus. Each device on the I2C bus has its own unique address to ensure accuracy of access between different devices.
Various I2C error reporting problems can be encountered in research and development tests of the server, the various problems are in an existing server design mechanism, only the BMC (Baseboard Management Controller ) can read information of each device through an I2C bus, the information can not be read, simple log record can be carried out in a log, and problem positioning is carried out through professional equipment in the later period. The design mechanism seriously affects the efficiency of positioning problems of research engineers, prolongs the development period of products, and increases the maintenance difficulty of later-stage products.
In summary, how to effectively solve the problems of low positioning efficiency, long product development period, and high maintenance difficulty of the later-stage product of the I2C bus is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a transmission state monitoring method of an I2C bus, which improves problem positioning efficiency, improves product development efficiency, shortens product development period and is convenient for later product maintenance; another object of the present invention is to provide a transmission status monitoring apparatus, device and computer readable storage medium for an I2C bus.
In order to solve the technical problems, the invention provides the following technical scheme:
a transmission state monitoring method of an I2C bus comprises the following steps:
transmitting system management bus information of the baseboard management controller to the complex programmable logic device;
Transmitting the system management bus information to each slave device through an I2C Switch chip virtually obtained in the complex programmable logic device;
Reading system management bus information corresponding to each slave device from a system management bus interface corresponding to each slave device respectively by using an FPGA;
And determining the I2C bus transmission state between the baseboard management controller and each slave device according to each system management bus information.
In one embodiment of the present invention, after the system management bus information corresponding to each slave device is read from the system management bus interface corresponding to each slave device by using the FPGA, the method further includes:
and storing the system management bus information corresponding to each slave device into a flash memory chip pre-mounted in the FPGA.
In one embodiment of the present invention, after storing the system management bus information corresponding to each slave device in a flash memory chip pre-mounted on the FPGA, the method further includes:
And exporting system management bus information in a flash memory chip of the FPGA by utilizing a Typc-C connector externally connected to the FPGA.
In one embodiment of the present invention, after the system management bus information corresponding to each slave device is read from the system management bus interface corresponding to each slave device by using the FPGA, the method further includes:
and outputting and displaying the system management bus information.
In one embodiment of the present invention, the outputting and displaying the system management bus information includes:
and outputting the system management bus information to a liquid crystal display connected with the FPGA through a low-voltage differential signal so as to display the system management bus information by using the liquid crystal display.
In one specific embodiment of the present invention, the reading, by using an FPGA, system management bus information corresponding to each slave device from a system management bus interface corresponding to each slave device, includes:
Receiving a system management bus interface selection signal;
determining a target system management bus interface according to the system management bus interface selection signal;
Reading target system management bus information corresponding to target slave equipment from the target system management bus interface by using an FPGA;
determining an I2C bus transfer state between the baseboard management controller and each slave device according to each system management bus information, including:
And determining the I2C bus transmission state between the baseboard management controller and the target slave device according to the target system management bus information.
In one embodiment of the present invention, determining an I2C bus transmission status between the baseboard management controller and the target slave device according to the target system management bus information includes:
outputting and displaying the target system management bus information;
when the display content is a preset binary coded signal, determining that the I2C bus state between the baseboard management controller and the target slave device is normal;
when the display content is error prompt information, determining that the I2C bus state between the baseboard management controller and the target slave device is abnormal;
And when the display content is that the address display of the target slave device is normal but the data display is abnormal, determining that the I2C bus connection between the baseboard management controller and the target slave device is normal and the data acquisition is abnormal.
A transmission status monitoring device of an I2C bus, comprising:
The first information sending module is used for sending the system management bus information of the baseboard management controller to the complex programmable logic device;
the second information sending module is used for sending the system management bus information to each slave device through an I2CSwitch chip obtained virtually in the complex programmable logic device;
The information reading module is used for reading the system management bus information corresponding to each slave device from the system management bus interface corresponding to each slave device respectively by using the FPGA;
and the state determining module is used for determining the I2C bus transmission state between the baseboard management controller and each slave device according to each system management bus information.
A transmission status monitoring device of an I2C bus, comprising:
A memory for storing a computer program;
and the processor is used for realizing the steps of the transmission state monitoring method of the I2C bus when executing the computer program.
A computer readable storage medium having stored thereon a computer program which when executed by a processor implements the steps of the transmission status monitoring method of an I2C bus as described above.
The invention provides a transmission state monitoring method of an I2C bus, which is used for sending system management bus information of a baseboard management controller to a complex programmable logic device; the system management bus information is sent to each slave device through an I2C Switch chip virtually obtained in the complex programmable logic device; reading system management bus information corresponding to each slave device from a system management bus interface corresponding to each slave device respectively by using the FPGA; and determining the I2C bus transmission state between the baseboard management controller and each slave device according to the system management bus information.
According to the technical scheme, the complex programmable logic device is connected with the baseboard management controller, the I2C Switch chip is obtained in the complex programmable logic device in advance virtually, the baseboard management controller sends system management bus information to the complex programmable logic device, each slave device is mounted through each system management bus interface in advance, the complex programmable logic device sends the system management bus information to each slave device through each system management bus interface, the complex programmable logic device is arranged on an FPGA connected with the complex programmable logic device, and the system management bus information corresponding to each slave device is read from the system management bus interface corresponding to each slave device through the FPGA, so that the transmission state and data of the I2C are obtained, inconvenience and trouble caused by problem location by using special equipment are avoided, the problem location efficiency is improved, the product development period is shortened, and the later product maintenance is facilitated.
Correspondingly, the invention also provides an I2C bus transmission state monitoring device, equipment and a computer readable storage medium corresponding to the I2C bus transmission state monitoring method, which have the technical effects and are not repeated herein.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a prior art transmission state monitoring system for an I2C bus;
FIG. 2 is a flowchart of a method for monitoring a transmission status of an I2C bus according to an embodiment of the present invention;
FIG. 3 is a flowchart of another embodiment of a method for monitoring a transmission status of an I2C bus according to the present invention;
FIG. 4 is a block diagram illustrating a transmission status monitoring system of an I2C bus according to an embodiment of the present invention;
FIG. 5 is a block diagram illustrating a transmission status monitor device for an I2C bus according to an embodiment of the present invention;
FIG. 6 is a block diagram illustrating a transmission status monitor device for an I2C bus according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a specific structure of a transmission status monitoring device for an I2C bus according to the present embodiment.
Detailed Description
Referring to fig. 1, fig. 1 is a block diagram of a transmission status monitoring system of an I2C bus in the prior art. The I2C Switch chip such as slave device and the down-hook 9548 is connected through the I2C interface of the baseboard management controller to expand. The transmission state and data of the I2C cannot be effectively monitored, the problem needs to be located by using professional equipment, the locating efficiency is low, the difficulty is high, the development efficiency of products is affected, and the development period of the products is long.
Therefore, in the transmission state monitoring method of the I2C bus, the problem locating efficiency is improved, the development efficiency of products is improved, the development period of the products is shortened, and the maintenance of the later products is facilitated.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 2, fig. 2 is a flowchart showing a method for monitoring a transmission status of an I2C bus according to an embodiment of the present invention, the method may include the following steps:
S201: and sending the system management bus information of the baseboard management controller to the complex programmable logic device.
A complex programmable logic device (Complex Programmable Logic Device, CPLD) is preset to connect with the baseboard management controller. When the baseboard management controller communicates with the slave device, system management Bus information (SYSTEM MANAGEMENT Bus, SMBUS) of the baseboard management controller is sent to the complex programmable logic device.
S202: and transmitting the system management bus information to each slave device through an I2C Switch chip obtained virtually in the complex programmable logic device.
The I2C Switch chip is obtained in advance virtually in the complex programmable logic device, and after the system management bus information of the baseboard management controller is sent to the complex programmable logic device, the system management bus information is sent to each slave device through the I2C Switch chip obtained virtually in the complex programmable logic device.
For example, taking a general server as an example, the rate of SMBUS (I2C) signals connected to the current baseboard management controller is usually 100Kb/s, the SMBUS signal rate between the baseboard management controller on the main board and the complex programmable logic device can be increased to 2Mb/s, multiple SMBUS channels are output inside the complex programmable logic device through an I2C Switch chip with the same function as a 9548 chip in a virtual way, and the rate of each SMBUS channel is 100Kb/s, so that slave devices are connected. Therefore, only one system management bus interface is needed between the baseboard management controller and the complex programmable logic device.
S203: and reading the system management bus information corresponding to each slave device from the system management bus interface corresponding to each slave device by using the FPGA.
An FPGA (Field Programmable GATE ARRAY, programmable logic device) connected to the complex programmable logic device is preset. After the system management bus information is sent to each slave device through the I2C Switch chip virtually obtained in the complex programmable logic device, the FPGA is utilized to read the system management bus information corresponding to each slave device from the system management bus interface corresponding to each slave device, for example, the system management bus information is transmitted to a connector reserved on a main BOARD carrying the baseboard management controller and the complex programmable logic device, and the system management bus information is transmitted to a connector on a DEBUG BOARD (DEBUG BOARD) where the FPGA is located through the connector, so that the transmission of the system management bus information from the slave device to the FPGA is realized.
In a specific embodiment of the present invention, after step S203, the method may further include the steps of:
and storing the system management bus information corresponding to each slave device into a flash memory chip pre-mounted in the FPGA.
After the system management bus information corresponding to each slave device is read from the system management bus interface corresponding to each slave device by using the FPGA, the system management bus information corresponding to each slave device is stored in a flash memory chip pre-mounted in the FPGA. Therefore, log record of system management bus information is realized, and subsequent log information reading is facilitated, and I2C bus state judgment and maintenance between the slave device and the baseboard management controller are carried out.
In a specific embodiment of the present invention, after storing the system management bus information corresponding to each slave device in a flash memory chip pre-mounted on the FPGA, the method may further include the steps of:
And exporting system management bus information in a flash memory chip of the FPGA by utilizing a Typc-C connector externally connected to the FPGA.
After the system management bus information corresponding to each slave device is stored in a flash memory chip pre-mounted in the FPGA, the system management bus information in the flash memory chip of the FPGA is derived by using a Typc-C connector (USB_DP/DN) externally connected to the FPGA. The system management bus information in the flash memory chip is exported, so that the log information can be conveniently stored in a centralized way.
In a specific embodiment of the present invention, after step S203, the method may further include the steps of:
and outputting and displaying the system management bus information.
And after the system management bus information corresponding to each slave device is read from the system management bus interface corresponding to each slave device by using the FPGA, outputting and displaying the system management bus information. Through the output display of the information of the system management bus, a user can intuitively embody the transmission state and data of the I2C bus.
In a specific embodiment of the present invention, performing an output display operation on system management bus information may include the following steps:
And outputting the system management bus information to a liquid crystal display connected with the FPGA through a low-voltage differential signal so as to display the system management bus information by using the liquid crystal display.
After the system management bus information corresponding to each slave device is read from the system management bus interface corresponding to each slave device by using the FPGA, the system management bus information is output to the liquid crystal display connected to the FPGA through a Low-Voltage differential signal (Low-Voltage DIFFERENTIAL SIGNALING, LVDS) so as to display the system management bus information by using the liquid crystal display. Thus, visual display of system management bus information is realized.
S204: and determining the I2C bus transmission state between the baseboard management controller and each slave device according to the system management bus information.
After the system management bus information corresponding to each slave device is read from the system management bus interface corresponding to each slave device by using the FPGA, the I2C bus transmission state between the substrate management controller and each slave device is determined according to the system management bus information. The system management bus information changes according to the specific communication connection condition between the baseboard management controller and the corresponding slave device, and the I2C bus transmission state between the baseboard management controller and the slave device can be determined according to the specific content of the system management bus information.
According to the technical scheme, the complex programmable logic device is connected with the baseboard management controller, the I2C Switch chip is obtained in the complex programmable logic device in advance virtually, the baseboard management controller sends system management bus information to the complex programmable logic device, each slave device is mounted through each system management bus interface in advance, the complex programmable logic device sends the system management bus information to each slave device through each system management bus interface, the complex programmable logic device is arranged on an FPGA connected with the complex programmable logic device, and the system management bus information corresponding to each slave device is read from the system management bus interface corresponding to each slave device through the FPGA, so that the transmission state and data of the I2C are obtained, inconvenience and trouble caused by problem location by using special equipment are avoided, the problem location efficiency is improved, the product development period is shortened, and the later product maintenance is facilitated.
It should be noted that, based on the above embodiments, the embodiments of the present invention further provide corresponding improvements. The following embodiments relate to the same steps as those in the above embodiments or the steps corresponding to the steps may be referred to each other, and the corresponding beneficial effects may also be referred to each other, which will not be described in detail in the following modified embodiments.
Referring to fig. 3, fig. 3 is a flowchart illustrating another implementation of a method for monitoring a transmission status of an I2C bus according to an embodiment of the present invention, the method may include the following steps:
s301: and sending the system management bus information of the baseboard management controller to the complex programmable logic device.
S302: and transmitting the system management bus information to each slave device through an I2C Switch chip obtained virtually in the complex programmable logic device.
S303: a system management bus interface selection signal is received.
After the system management bus information is sent to each slave device through the I2C Switch chip virtually obtained in the complex programmable logic device, the system management bus information corresponding to the specific slave device can be selected to be output and displayed, for example, a system management bus interface selection signal can be generated according to the selection of a key Switch, and the state detection system receives the system management bus interface selection signal.
S304: and determining a target system management bus interface according to the system management bus interface selection signal.
The system management bus interface selection signal comprises a target system management bus interface, and after the system management bus interface selection signal is received, the target system management bus interface is determined according to the system management bus interface selection signal.
S305: and reading target system management bus information corresponding to the target slave device from the target system management bus interface by using the FPGA.
After determining the target system management bus interface according to the system management bus interface selection signal, reading target system management bus information corresponding to the target slave device from the target system management bus interface by using the FPGA. Thus realizing the output of the system management bus information of the specific slave device or selectively outputting the whole system management bus information.
S306: and determining the I2C bus transmission state between the baseboard management controller and the target slave device according to the target system management bus information.
In one embodiment of the present invention, step S306 may include the steps of:
step one: outputting and displaying the management bus information of the target system;
Step two: when the display content is a preset binary coded signal, determining that the I2C bus state between the baseboard management controller and the target slave device is normal;
step three: when the display content is error prompt information, determining that the I2C bus state between the baseboard management controller and the target slave device is abnormal;
step four: when the display content is that the address display of the target slave device is normal but the data display is abnormal, the I2C bus connection between the baseboard management controller and the target slave device is normal and the data acquisition is abnormal.
For convenience of description, the above four steps may be combined for explanation.
Referring to fig. 4, fig. 4 is a block diagram illustrating a transmission status monitoring system of an I2C bus according to an embodiment of the present invention. And after the target system management bus information corresponding to the target slave device is read from the target system management bus interface by using the FPGA, outputting and displaying the target system management bus information. When the display content is a preset binary coded signal, as shown in a display 011111001010001001 …, it is determined that the I2C bus state between the baseboard management controller and the target slave device is normal. When the display content is ERROR prompt information, such as ERROR-! ! ! An I2C bus state exception between the baseboard management controller and the target slave device is determined. When the display content is that the Address display of the target slave device is normal but the data display is abnormal, such as display Address:0x80no reading-! ! ! And determining that the I2C bus connection between the baseboard management controller and the target slave device is normal and the data acquisition is abnormal. Therefore, the I2C transmission information is more transparent and intelligent.
As shown in FIG. 4, the power supply used for the debug board work is connected with the main board power supply from the interface with the main board, the debug board is supported to work, the debug board supports hot plug, and the enabling signal and the reset signal on the debug board are controlled by the FPGA.
Corresponding to the above method embodiment, the present invention further provides an I2C bus transmission state monitoring device, where the transmission state monitoring device of the I2C bus described below and the transmission state monitoring method of the I2C bus described above may be referred to correspondingly.
Referring to fig. 5, fig. 5 is a block diagram illustrating a transmission status monitoring apparatus for an I2C bus according to an embodiment of the present invention, where the apparatus may include:
A first information sending module 51, configured to send system management bus information of the baseboard management controller to the complex programmable logic device;
The second information sending module 52 is configured to send the system management bus information to each slave device through an I2CSwitch chip that is virtually obtained in the complex programmable logic device;
An information reading module 53, configured to read, by using the FPGA, system management bus information corresponding to each slave device from a system management bus interface corresponding to each slave device;
The status determining module 54 is configured to determine an I2C bus transmission status between the baseboard management controller and each slave device according to each system management bus information.
According to the technical scheme, the complex programmable logic device is connected with the baseboard management controller, the I2C Switch chip is obtained in the complex programmable logic device in advance virtually, the baseboard management controller sends system management bus information to the complex programmable logic device, each slave device is mounted through each system management bus interface in advance, the complex programmable logic device sends the system management bus information to each slave device through each system management bus interface, the complex programmable logic device is arranged on an FPGA connected with the complex programmable logic device, and the system management bus information corresponding to each slave device is read from the system management bus interface corresponding to each slave device through the FPGA, so that the transmission state and data of the I2C are obtained, inconvenience and trouble caused by problem location by using special equipment are avoided, the problem location efficiency is improved, the product development period is shortened, and the later product maintenance is facilitated.
In one embodiment of the present invention, the apparatus may further include:
And the information storage module is used for storing the system management bus information corresponding to each slave device into a flash memory chip pre-mounted in the FPGA after the system management bus information corresponding to each slave device is read from the system management bus interface corresponding to each slave device by the FPGA.
In one embodiment of the present invention, the apparatus may further include:
And the information export module is used for exporting the system management bus information in the flash memory chip of the FPGA by utilizing the Typc-C connector externally connected to the FPGA after storing the system management bus information corresponding to each slave device into the flash memory chip pre-mounted in the FPGA.
In one embodiment of the present invention, the apparatus may further include:
and the information display module is used for outputting and displaying the system management bus information after the system management bus information corresponding to each slave device is read from the system management bus interface corresponding to each slave device by using the FPGA.
In one embodiment of the present invention, the information display module is specifically a module that outputs system management bus information to a liquid crystal display connected to the FPGA through a low voltage differential signal, so as to display the system management bus information by using the liquid crystal display.
In one embodiment of the present invention, the information reading module 53 includes:
a selection signal receiving sub-module for receiving a system management bus interface selection signal;
the interface determining submodule is used for determining a target system management bus interface according to the system management bus interface selection signal;
The information reading sub-module is used for reading target system management bus information corresponding to the target slave device from the target system management bus interface by using the FPGA;
the status determination module 54 is specifically a module that determines the I2C bus transfer status between the baseboard management controller and the target slave device based on the target system management bus information.
In one embodiment of the present invention, the status determination module 54 includes:
the output display sub-module is used for outputting and displaying the target system management bus information;
the state normal determining submodule is used for determining that the state of the I2C bus between the baseboard management controller and the target slave device is normal when the display content is a preset binary coded signal;
The state abnormality determining sub-module is used for determining that the I2C bus state between the baseboard management controller and the target slave device is abnormal when the display content is error prompt information;
And the connection normal determination submodule is used for determining that the I2C bus connection between the baseboard management controller and the target slave device is normal and the data acquisition is abnormal when the display content is that the address display of the target slave device is normal but the data display is abnormal.
Corresponding to the above method embodiment, referring to fig. 6, fig. 6 is a schematic diagram of an I2C bus transmission status monitoring device provided by the present invention, where the device may include:
A memory 332 for storing a computer program;
A processor 322, configured to implement the steps of the method for monitoring the transmission status of the I2C bus in the method embodiment described above when executing a computer program.
Specifically, referring to fig. 7, fig. 7 is a schematic diagram of a specific structure of an I2C bus transmission status monitoring device according to the present embodiment, where the I2C bus transmission status monitoring device may have a relatively large difference due to different configurations or performances, and may include a processor (central processing units, CPU) 322 (e.g. one or more processors) and a memory 332, where the memory 332 stores one or more computer applications 342 or data 344. Wherein the memory 332 may be transient storage or persistent storage. The program stored in memory 332 may include one or more modules (not shown), each of which may include a series of instruction operations in the data processing apparatus. Still further, the processor 322 may be configured to communicate with the memory 332 to execute a series of instruction operations in the memory 332 on the transmission status monitoring device 301 of the I2C bus.
The transmission status monitoring device 301 for an I2C bus may also include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input/output interfaces 358, and/or one or more operating systems 341.
The steps in the transmission state monitoring method of the I2C bus described above may be implemented by the structure of the transmission state monitoring device of the I2C bus.
Corresponding to the above method embodiments, the present invention also provides a computer readable storage medium having a computer program stored thereon, which when executed by a processor, performs the steps of:
Transmitting system management bus information of the baseboard management controller to the complex programmable logic device; the system management bus information is sent to each slave device through an I2C Switch chip virtually obtained in the complex programmable logic device; reading system management bus information corresponding to each slave device from a system management bus interface corresponding to each slave device respectively by using the FPGA; and determining the I2C bus transmission state between the baseboard management controller and each slave device according to the system management bus information.
The computer readable storage medium may include: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
For the description of the computer-readable storage medium provided by the present invention, refer to the above method embodiments, and the disclosure is not repeated here.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. The apparatus, device and computer readable storage medium of the embodiments are described more simply because they correspond to the methods of the embodiments, and the description thereof will be given with reference to the method section.
The principles and embodiments of the present invention have been described herein with reference to specific examples, but the description of the examples above is only for aiding in understanding the technical solution of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
Claims (8)
1. A method for monitoring a transmission state of an I2C bus, comprising:
transmitting system management bus information of the baseboard management controller to the complex programmable logic device;
Transmitting the system management bus information to each slave device through an I2C Switch chip virtually obtained in the complex programmable logic device;
Reading system management bus information corresponding to each slave device from a system management bus interface corresponding to each slave device respectively by using an FPGA; determining an I2C bus transmission state between the baseboard management controller and each slave device according to each system management bus information;
The method for reading the system management bus information corresponding to each slave device from the system management bus interfaces corresponding to each slave device respectively by using the FPGA comprises the following steps:
Receiving a system management bus interface selection signal;
determining a target system management bus interface according to the system management bus interface selection signal;
Reading target system management bus information corresponding to target slave equipment from the target system management bus interface by using an FPGA;
determining an I2C bus transfer state between the baseboard management controller and each slave device according to each system management bus information, including:
outputting and displaying the target system management bus information;
when the display content is a preset binary coded signal, determining that the I2C bus state between the baseboard management controller and the target slave device is normal;
when the display content is error prompt information, determining that the I2C bus state between the baseboard management controller and the target slave device is abnormal;
And when the display content is that the address display of the target slave device is normal but the data display is abnormal, determining that the I2C bus connection between the baseboard management controller and the target slave device is normal and the data acquisition is abnormal.
2. The transmission state monitoring method of an I2C bus according to claim 1, further comprising, after reading, by the FPGA, system management bus information corresponding to each of the slave devices from a system management bus interface corresponding to each of the slave devices, respectively:
and storing the system management bus information corresponding to each slave device into a flash memory chip pre-mounted in the FPGA.
3. The method for monitoring a transmission state of an I2C bus according to claim 2, further comprising, after storing the system management bus information corresponding to each of the slave devices in a flash memory chip pre-mounted in the FPGA:
And exporting system management bus information in a flash memory chip of the FPGA by utilizing a Typc-C connector externally connected to the FPGA.
4. The transmission state monitoring method of an I2C bus according to claim 1, further comprising, after reading, by the FPGA, system management bus information corresponding to each of the slave devices from a system management bus interface corresponding to each of the slave devices, respectively:
and outputting and displaying the system management bus information.
5. The method for monitoring the transmission status of an I2C bus according to claim 4, wherein performing an output display operation on the system management bus information comprises:
and outputting the system management bus information to a liquid crystal display connected with the FPGA through a low-voltage differential signal so as to display the system management bus information by using the liquid crystal display.
6. A transmission state monitoring device for an I2C bus, comprising:
The first information sending module is used for sending the system management bus information of the baseboard management controller to the complex programmable logic device;
The second information sending module is used for sending the system management bus information to each slave device through an I2C Switch chip obtained virtually in the complex programmable logic device;
The information reading module is used for reading the system management bus information corresponding to each slave device from the system management bus interface corresponding to each slave device respectively by using the FPGA; a state determining module, configured to determine an I2C bus transmission state between the baseboard management controller and each slave device according to each system management bus information;
Wherein, the information reading module includes:
a selection signal receiving sub-module for receiving a system management bus interface selection signal;
the interface determining submodule is used for determining a target system management bus interface according to the system management bus interface selection signal;
The information reading sub-module is used for reading target system management bus information corresponding to the target slave device from the target system management bus interface by using the FPGA;
The state determining module is specifically a module for determining the I2C bus transmission state between the substrate management controller and the target slave device according to the target system management bus information;
the state determination module includes:
the output display sub-module is used for outputting and displaying the target system management bus information;
the state normal determining submodule is used for determining that the state of the I2C bus between the baseboard management controller and the target slave device is normal when the display content is a preset binary coded signal;
The state abnormality determining sub-module is used for determining that the I2C bus state between the baseboard management controller and the target slave device is abnormal when the display content is error prompt information;
And the connection normal determination submodule is used for determining that the I2C bus connection between the baseboard management controller and the target slave device is normal and the data acquisition is abnormal when the display content is that the address display of the target slave device is normal but the data display is abnormal.
7. A transmission state monitoring device of an I2C bus, comprising:
A memory for storing a computer program;
a processor for implementing the steps of the transmission status monitoring method of the I2C bus according to any one of claims 1 to 5 when executing the computer program.
8. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, implements the steps of the transmission status monitoring method of an I2C bus according to any one of claims 1 to 5.
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| CN108919935A (en) * | 2018-07-12 | 2018-11-30 | 浪潮电子信息产业股份有限公司 | A monitoring method, device and equipment for a power supply on a server motherboard |
| CN114138644A (en) * | 2021-11-29 | 2022-03-04 | 山东云海国创云计算装备产业创新中心有限公司 | BMC (baseboard management controller) debugging method, monitoring method, system, device, equipment and medium |
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| CN108919935A (en) * | 2018-07-12 | 2018-11-30 | 浪潮电子信息产业股份有限公司 | A monitoring method, device and equipment for a power supply on a server motherboard |
| CN114138644A (en) * | 2021-11-29 | 2022-03-04 | 山东云海国创云计算装备产业创新中心有限公司 | BMC (baseboard management controller) debugging method, monitoring method, system, device, equipment and medium |
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