CN116521496A - Method, system, computer device and storage medium for verifying server performance - Google Patents

Abstract

The invention discloses a server performance verification method, a system, computer equipment and a storage medium, wherein the method comprises the following steps: receiving an error injection instruction and generating a hardware true error occurrence scheme based on the error injection instruction; transmitting the hardware real error occurrence scheme to target hardware so that the target hardware can generate real errors based on the hardware real error occurrence scheme; acquiring log information of the real errors, and acquiring a hardware real error occurrence scheme and register information; processing the real error based on the log information of the real error, the hardware real error occurrence scheme, and the register information to verify the server performance; various real hardware errors occur and are identified by the server through the occurrence of the real hardware errors; the hardware real error occurrence scheme, the register and the log information are grabbed, and the server performance test efficiency is optimized.

Description

Server performance verification method, system, computer equipment and storage medium

technical field

The invention relates to the field of server testing, in particular to a server performance verification method, system, computer equipment and storage medium.

Background technique

In the prior art, when verifying server performance, the xdp (extenddebugport, extended debugging port) interface on the server motherboard is usually used for error injection testing. Error injection is a simulated error or only occurs at the hardware interface, not a real error in the hardware. Moreover, the PEI card and MEI card provided by Intel can only be injected into a single type, so the accuracy of the error injection test is limited and the efficiency is low.

Contents of the invention

The purpose of the present invention is to provide a server performance verification method, system, computer equipment and storage medium.

The technical solution of the present invention is: in the first aspect, the present invention provides a server performance verification method, the method comprising:

receiving an error injection instruction and generating a real hardware error occurrence scheme based on the error injection instruction;

Sending the hardware real error occurrence scheme to the target hardware, so that the target hardware generates a real error based on the hardware real error occurrence scheme;

Obtain the log information of the real error, and obtain the hardware real error occurrence scheme and register information;

The real error is processed based on the log information of the real error, the hardware real error occurrence scheme and the register information to verify the performance of the server.

In a preferred implementation manner, the receiving the error injection instruction and generating a real hardware error occurrence scheme based on the error injection instruction includes:

Receive error injection instructions;

Read server hardware configuration information, the server hardware configuration information at least includes: hardware model, hardware quantity, content capacity and memory location;

A real hardware error occurrence scheme is generated based on the error injection instruction and the server hardware configuration information, and the hardware real error occurrence scheme at least includes an error list, an error priority, and an error type.

In a preferred implementation manner, before receiving the error injection instruction and generating a real hardware error occurrence scheme based on the error injection instruction, the method further includes:

A preset error injection scheme is displayed on the human-computer interaction interface for the user to select to input an error injection command, and the preset error injection scheme includes any one of self-defined errors, random errors, and fault torrents.

In a preferred implementation manner, in response to the error injection scheme selected by the user is a custom error, the generation of a real hardware error occurrence scheme based on the error injection instruction and the server hardware configuration information includes:

Receive user-defined hardware type information, custom error type information, custom error occurrence times information, and error location information;

A real hardware error occurrence solution is generated based on the user-defined hardware type information, user-defined error type information, user-defined error frequency information, error location information, and the server hardware configuration information.

In a preferred implementation manner, in response to the error injection scheme selected by the user being a random error, the generation of a real hardware error occurrence scheme based on the error injection instruction and the server hardware configuration information includes:

A real hardware error occurrence scheme is randomly generated based on the server hardware configuration information.

In a preferred implementation manner, in response to the error injection scheme selected by the user being a fault flood, the generation of a real hardware error occurrence scheme based on the error injection instruction and the server hardware configuration information includes:

Randomly generate errors based on the server hardware configuration information for a preset period of time to generate a real hardware error occurrence solution.

In a preferred implementation manner, before sending the hardware real error occurrence scheme to the target hardware for the target hardware to generate a real error based on the hardware real error occurrence scheme, the method further includes:

Analyzing the hardware real error occurrence scheme to obtain hardware real error category information, the hardware real error category information includes at least one of CPU hardware errors, memory hardware errors, PCIE hardware errors and other errors;

Analyzing the hardware real error occurrence scheme to obtain target hardware layer information corresponding to the hardware real error category information;

Analyzing the hardware real error occurrence scheme to obtain target error type information corresponding to the target hardware layer information;

The sending the real error occurrence scheme of the hardware to the target hardware includes:

Sending the target hardware layer information and the target error type information to target hardware based on the hardware real error type information.

In a preferred implementation manner, the analyzing the hardware real error occurrence scheme to obtain hardware real error category information includes:

Analyzing the hardware real error occurrence scheme based on the error priority and the error list to obtain hardware real error category information.

In a preferred implementation manner, when the solution for analyzing the real hardware error occurrence obtains the target error type information corresponding to the target hardware layer information, a first error random number is also generated;

Before the parsing of the hardware real error occurrence scheme to obtain the target error type information corresponding to the target hardware layer information, the method further includes:

Correcting the target hardware layer information based on the first erroneous random number.

In a preferred implementation manner, when the solution for analyzing the real hardware error occurrence obtains the target error type information corresponding to the target hardware layer information, a second error random number is also generated.

Before sending the target hardware layer information and the target error type information to the target hardware based on the real hardware error category information, the method further includes:

Correcting the target error type information based on the second error random number.

In a preferred embodiment, the sending the hardware real error occurrence scheme to the target hardware, so that the target hardware generates a real error based on the hardware real error occurrence scheme includes:

Sending the target hardware layer information and the target error type information to target hardware in the form of error packets or error streams to generate real errors.

In a preferred implementation manner, the obtaining log information of the real error includes:

Grab the log information of the real error based on the preset interface, the preset interface includes at least one of a serial port, an XDP interface, an IPMI interface, a redfish interface and an SSH interface; the log information of the real error is generated by the target hardware After a real error occurs, it is reported to the OSkernel and BMC via the UEFI system for generation.

In a preferred implementation manner, said acquisition of hardware real error occurrence scheme and register information includes:

Obtain the real error occurrence scheme of the hardware;

Acquiring register information for error transfer and processing trigger register setting, where the register information at least includes SMI link information and CSMI link information.

In a preferred implementation manner, said acquisition of error transmission and processing trigger register setting register information includes:

Obtain the register information that is passed to the trigger register setting in the UEFI system after an error occurs.

In a preferred implementation manner, the processing of the real error based on the real error log information, the hardware real error occurrence scheme and the register information to verify the server performance includes:

Judging whether the log of the real error is consistent with the hardware real error occurrence scheme, and judging whether the register information is consistent with the hardware real error occurrence scheme;

If the real error log is consistent with the hardware real error occurrence scheme, and the register information is consistent with the hardware real error occurrence scheme, then verify that the performance of the server is qualified.

In a preferred implementation manner, the judging whether the real error log is consistent with the hardware real error occurrence scheme includes:

Judging whether the log of the real error is consistent with the error information in the hardware real error occurrence scheme, the error information includes error type, error location, error times, and error occurrence time.

In a preferred implementation manner, the judging whether the register information is consistent with the hardware real error occurrence scheme includes:

Judging whether the error type in the register information is consistent with the error type in the hardware real error occurrence scheme.

In a second aspect, the present invention also provides a server performance verification system, the system comprising:

A receiving and generating module, configured to receive an error injection instruction and generate a real hardware error occurrence scheme based on the error injection instruction;

A sending module, configured to send the hardware real error occurrence scheme to the target hardware, so that the target hardware generates a real error based on the hardware real error occurrence scheme;

An obtaining module, configured to obtain the log information of the real error, and obtain the hardware real error occurrence scheme and register information;

A processing module, configured to process the real error based on the real error log information, the hardware real error occurrence scheme, and the register information to verify the server performance.

In a third aspect, the present invention also provides a computer device, the computer device comprising:

one or more processors;

And a memory associated with the one or more processors, the memory is used to store program instructions, and when the program instructions are read and executed by the one or more processors, perform any one of the steps in the first aspect. The server performance verification method described in the item.

In the fourth aspect, the present invention also provides a computer-readable storage medium, the computer-readable storage medium stores computer instructions, and the computer instructions cause the computer to execute the server performance as described in any one of the first aspect. Authentication method.

The present invention has the advantages of providing a server performance verification method, system, computer equipment and storage medium, the method comprising: receiving an error injection instruction and generating a hardware real error occurrence scheme based on the error injection instruction; sending the hardware real error occurrence scheme; The error occurrence scheme is sent to the target hardware for the target hardware to generate a real error based on the real error occurrence scheme of the hardware; the log information of the real error is obtained, and the hardware real error occurrence scheme and register information are obtained; based on the real error The log information, the hardware real error occurrence scheme and the register information process the real error to verify the performance of the server; through the occurrence of real hardware errors, various real hardware errors occur and are recognized by the server; grab hardware real The error occurrence scheme and register and log information optimize the efficiency of server performance testing.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

FIG. 1 is a schematic diagram of the architecture of server performance verification in this application;

Fig. 2 is a flowchart of the server performance verification method provided by the present application;

Fig. 3 is a framework flowchart of the server performance verification provided by the present application;

Fig. 4 is the architectural diagram of the server performance verification system provided by the present application;

FIG. 5 is a structural diagram of a computer device provided by the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the application clearer, the technical solutions in the embodiments of the application will be clearly and completely described below in conjunction with the drawings in the embodiments of the application. Obviously, the described embodiments are only Some embodiments of this application are not all embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

As described in the background technology, in the prior art

The server motherboard has an xdp (extenddebugport, extended debug port) interface, which is a JTAG (jointtestactiongroup, joint test working group) type interface. This interface is an international standard test protocol (ieee1149.1 compatible), mainly used for error injection testing . In the prior art, error injection is a simulated error or an error that only occurs at the hardware interface, not an error that actually occurs in the hardware. However, for the physical PEI card or MEI card provided by Intel, only a single, single type of error can be injected into the same type, and it cannot be sustained and A large number of hardware errors are randomly generated.

In order to solve the above problems, the present application creatively proposes a server performance verification method, system, computer equipment and storage medium, the method includes: receiving an error injection instruction and generating a real hardware error occurrence scheme based on the error injection instruction; sending The hardware real error occurrence scheme is sent to the target hardware for the target hardware to generate a real error based on the hardware real error occurrence scheme; obtain the log information of the real error, and obtain the hardware real error occurrence scheme and register information; The log information of the real error, the hardware real error occurrence scheme and the register information process the real error to verify the performance of the server; through the occurrence of real hardware errors, various real hardware errors occur and are recognized by the server; Capture real hardware error occurrence schemes and register and log information, optimizing the efficiency of server performance testing.

The solutions of the present application will be described in detail below with reference to the drawings and various embodiments.

Embodiment 1: This embodiment introduces the architecture of server performance verification in this application.

Specifically, as shown in Figure 1, the architecture includes:

Server hardware and hardware interface, described server hardware and hardware interface comprise CPU (CentralProcessingUnit/Processor, central processing unit) hardware interface, internal memory hardware interface, PCIE (PCI-Express, bus and interface standard) hardware interface, PCH (PlatformControllerHub, is the integrated south bridge of intel company) hardware interface and corresponding hardware, of course, also includes other hardware interfaces set according to actual needs, the CPU hardware interface, memory hardware interface, PCIE hardware interface, PCH hardware interface and other The hardware interfaces set according to actual needs are all visible and interactive; the hardware receives and executes the errors issued by the error verification system through the hardware interfaces;

The architecture also includes: a human-computer interaction interface and a log input module, wherein the human-computer interaction interface is connected to the error verification system for users to input error injection instructions, display error injection schemes for users to choose, monitor error occurrence progress, and view Error history, check the error occurrence scheme and display the verification result after verification; the log capture interface includes but not limited to serial port, XDP interface, IPMI interface, redfish interface, SSH interface, etc., used to capture the log after the error is noted, Provide log information for error handling mechanism;

The architecture also includes an error generating device, wherein the error verification system is deployed in the error generating device, and includes an error generating module and an error diagnosing module inside. The error occurrence module is responsible for generating the real error occurrence plan of the hardware according to the error injection instruction input by the user, and parses it into an error occurrence instruction passed to the hardware. Comply with the hardware real error occurrence scheme.

Embodiment 2: Based on the architecture of server performance verification introduced in Embodiment 1 above, this embodiment introduces the process of server performance verification in this application with reference to FIG. 2 and FIG. 3 .

Specifically, referring to FIG. 2 and FIG. 3, the present application provides a server performance verification method, the method comprising:

S210. Receive an error injection instruction and generate a real hardware error occurrence scheme based on the error injection instruction.

Specifically, the system is connected to the human-computer interaction interface, and the user inputs an error injection instruction on the human-computer interaction interface, and the system generates a real hardware error occurrence scheme after receiving the error injection instruction transmitted by the human-computer interaction interface.

In one embodiment, the receiving an error injection instruction and generating a real hardware error occurrence scheme based on the error injection instruction includes:

S211. Displaying a preset error injection scheme on the human-computer interaction interface for the user to select to input an error injection command, the preset error injection scheme includes any one of custom errors, random errors, and fault floods.

Specifically, in order to improve the user-friendliness, when the user inputs an error injection command through the input and output functions of the human-computer interaction interface, various error injection solutions are provided on the human-computer interaction interface, including but not limited to: custom errors (user-defined errors) You can customize the hardware type, error type, error occurrence times, error location, etc.), random errors (errors will be randomly generated according to the server hardware configuration), fault flood (according to the server hardware configuration, a large number of hardware errors will be continuously and randomly generated).

S212. Receive an error injection instruction.

Receive the preset error injection scheme and specific content selected by the user, and the user can choose any one of custom errors, random errors, and fault torrents. Of course, if the preset error injection scheme also includes other error injection schemes, the user can also choose, not limited to the above-mentioned custom errors, random errors, and fault torrents.

S213. Read server hardware configuration information, where the server hardware configuration information at least includes: hardware model, hardware quantity, content capacity, and memory location.

Specifically, the system reads the server hardware configuration, such as hardware model, hardware quantity, memory capacity, location and other information, and confirms the currently available configuration hardware, which is used to formulate a real hardware error occurrence plan.

S214. Generate a real hardware error occurrence scheme based on the error injection instruction and the server hardware configuration information, where the hardware real error occurrence scheme at least includes an error list, an error priority, and an error type.

Specifically, (1) in response to the error injection scheme selected by the user as a custom error, the generation of a real hardware error occurrence scheme based on the error injection instruction and the server hardware configuration information includes:

S2141. Receive user-defined hardware type information, user-defined error type information, user-defined error frequency information, and error location information;

S2142. Generate a real hardware error occurrence scheme based on the user-defined hardware type information, user-defined error type information, user-defined error frequency information, error location information, and the server hardware configuration information.

If the user-defined hardware type information, user-defined error type information, user-defined error frequency information, and error location information entered by the user conflict with the server hardware configuration information read, the conflict content information is sent to the human-computer interaction interface for display reminder. Exemplarily, the user-defined hardware type information entered by the user is the CPU hardware type, but the read server hardware configuration information shows that the current CPU type hardware is unavailable, then the user injection instruction conflicts with the read server hardware configuration information, and the error cannot be executed , display conflict content information - CPU hardware is not available to the human-computer interaction interface for display reminders.

(2) In response to the error injection scheme selected by the user being a random error, the generation of a real hardware error occurrence scheme based on the error injection instruction and the server hardware configuration information includes:

S2143. Randomly generate a real hardware error occurrence scheme based on the server hardware configuration information.

(3) In response to the error injection scheme selected by the user as a fault flood, the generation of a real hardware error occurrence scheme based on the error injection instruction and the server hardware configuration information includes:

S2144. Randomly generate errors for a preset period of time based on the server hardware configuration information to generate a real hardware error occurrence solution.

SA10. Analyze the hardware real error occurrence scheme to obtain hardware real error category information, and the hardware real error category information includes at least one of CPU hardware errors, memory hardware errors, PCIE hardware errors, and other errors.

Preferably, this step includes: analyzing the hardware real error occurrence scheme based on the error priority and the error list to obtain hardware real error category information.

Specifically, after the real hardware error occurrence scheme is generated, the system grabs the hardware real error occurrence scheme and analyzes them step by step. Since the server integrates and deploys CPU hardware interfaces, memory hardware interfaces, PCIE hardware interfaces, PCH hardware interfaces, and corresponding hardware, as well as other hardware interfaces that are set according to actual needs, the system deploys hardware analysis corresponding to each hardware and hardware interface module. After the system captures the real hardware error occurrence scheme, it will be analyzed in the corresponding hardware analysis module according to the error priority and error list.

Exemplarily, the error list in the hardware real error occurrence scheme includes CPU hardware errors and memory hardware errors, then based on the error priority-the CPU hardware error priority is higher than the memory hardware error priority in the CPU hardware analysis module and the memory analysis module successively parsed in the module.

SA20. Analyze the hardware real error occurrence scheme to obtain target hardware layer information corresponding to the hardware real error category information.

Specifically, after identifying and analyzing the error category that the real hardware error occurrence scheme belongs to, continue to analyze and obtain error hardware layer information.

Exemplarily, after parsing the actual hardware error occurrence scheme is CPU hardware error category, further parsing the corresponding hardware layer information. The hardware layer includes the transport layer, data layer and processing layer. The transport layer is responsible for data transmission, reception and output. Taking PCIE hardware as an example, the conventional names are RX (Receive receiving data) and TX (transport transmitting data). The data layer stores a large amount of data, and the processing layer involves data processing and calculation. The deeper the hardware hierarchy, the higher the severity of data transmission errors.

When the scheme for parsing the actual occurrence of hardware errors acquires the target error type information corresponding to the target hardware layer information, a first error random number is also generated.

SA30. Correct the target hardware layer information based on the first erroneous random number.

The hardware layer analysis process will generate the first error random number, and the first error random number will correct the error after the analysis of the target hardware layer information is completed. The purpose is to prevent the error distribution from being affected by the algorithm when the error is parsed to the next level. Fixed step-by-step state, as occurs with the usual normal distribution. The role of the random number is to allow errors to be fully covered within a controllable range, reducing the risk of uneven coverage.

SA40. Analyze the hardware real error occurrence scheme to obtain target error type information corresponding to the target hardware layer information.

When the scheme for analyzing the real hardware error occurrence obtains the target error type information corresponding to the target hardware layer information, a second error random number is also generated.

Specifically, after the error is parsed to the hardware layer, the error needs to be further parsed, and the error is further refined in each hardware layer to obtain the target error type information. For example, a single BIT error that can occur at any hardware layer is called a bit jump. The error of a bit jump is due to the flipping of a single BIT or multiple BITs in binary data. Other errors also involve CRC errors, read and write process errors and many other types of errors.

SA50. Correct the target error type information based on the second error random number.

The error type parsing process will generate a second error random number, and the second error random number will correct the error after the analysis of the target error type information is completed. The purpose is to prevent the error distribution from being affected by the algorithm and form a fixed step-by-step state. normal distribution of . The role of the random number is to allow errors to be fully covered within a controllable range, reducing the risk of uneven coverage.

S220. Send the hardware real error occurrence scheme to the target hardware, so that the target hardware generates a real error based on the hardware real error occurrence scheme.

Specifically, the sending the real error occurrence scheme of the hardware to the target hardware includes:

S221. Send the target hardware layer information and the target error type information to target hardware based on the hardware real error type information.

More specifically, sending the target hardware layer information and the target error type information to the target hardware in the form of error packets or error streams to generate real errors.

After the analysis of the error type is completed, the error will be sent to the hardware in the form of an error packet or error stream. The manifestations of hardware errors are also different, roughly divided into hardware physical layer setting: a certain physical layer of the hardware is completely paralyzed, Unable to work; link failure: some or all of the data transmission link fails, resulting in data that cannot be read or added to the calculation sequence; data error: translocation, missing, compilation errors, etc. in data reading, writing and transmission Data cannot be used, data errors occur, data cannot be used; and other types of errors cause errors in hardware operation.

The target hardware executes after receiving the target hardware layer information and target error type information issued by the system, and generates real errors.

S230. Obtain log information of real errors, and acquire hardware real error occurrence schemes and register information.

In an implementation manner, the obtaining log information of the real error includes:

S231. Capture the log information of the real error based on a preset interface, the preset interface including a serial port, an XDP (extenddebugport, extended debug port) interface, an IPMI interface (IntelligentPlatformManagementInterface, an intelligent platform management interface), a redfish interface, and an SSH interface at least one of; the log information of the real error is reported by the target hardware to OSkernel (operating system kernel) and BMC (BaseboardManagementController, baseboard management control via UEFI (UnifiedExtensibleFirmwareInterface, Unified Extensible Firmware Interface) system after the real error occurs device) generated.

Specifically, if the target hardware executes an error, it will be passed to the UEFI system after the error occurs, and UEFI will process the error and may reject it to allow the hardware to correct it again, or consider it as a real error after a certain value is accumulated to trigger register setting. The target hardware reports the error to the UEFI system, and the UEFI system reports the error to the OSkernel and BMC, which will generate a log and log information (including but not limited to massage, dmasg, etc.).

In an implementation manner, the acquiring the real hardware error occurrence scheme and register information includes:

S232. Obtain a real hardware error occurrence scheme.

S233. Acquire register information for error transfer and processing trigger register setting, where the register information at least includes SMI (Serial Management Interface, serial management interface) link information and CSMI link information.

Specifically, the acquisition of error transfer and processing of the register information of trigger register setting includes:

Obtain the register information that is passed to the trigger register setting in the UEFI system after an error occurs.

After the error occurs, it is passed to the UEFI system. After the error is passed and processed, it will trigger register setting, and the register information (including but not limited to SMI link, CSMI link, etc.) will be passed to the system for error handling.

S240. Process real errors based on real error log information, hardware real error occurrence scheme, and register information to verify server performance.

In one embodiment, the processing the real error based on the real error log information, the hardware real error occurrence scheme and the register information to verify the server performance includes:

Judging whether the log of the real error is consistent with the hardware real error occurrence scheme, and judging whether the register information is consistent with the hardware real error occurrence scheme;

If the real error log is consistent with the hardware real error occurrence scheme, and the register information is consistent with the hardware real error occurrence scheme, then verify that the performance of the server is qualified.

Preferably, the judging whether the log of the real error is consistent with the hardware real error occurrence scheme includes:

Judging whether the log of the real error is consistent with the error information in the hardware real error occurrence scheme, the error information includes error type, error location, error times, and error occurrence time.

The judging whether the register information is consistent with the hardware real error occurrence scheme includes:

Judging whether the error type in the register information is consistent with the error type in the hardware real error occurrence scheme. The register information includes an error type list, and it is judged whether the register information is consistent with the hardware actual error occurrence scheme by comparing whether the error type list in the register information matches the error type list in the hardware actual error occurrence scheme.

Whether the error type in the real solution is consistent with the register information.

The error handling process pulls the real hardware error occurrence scheme, register information, and log information to perform the fault handling process. Error handling is divided into manual inspection and automatic inspection. The main purpose is to compare whether the hardware actual error occurrence scheme matches the real error log. And whether it matches the register information, so as to verify whether the RSA function of the server is normal. Automated checks execute automated use cases, and the final results of the execution are presented in the human-machine interface. The manual inspection method will directly display the captured information to the operator for manual testing.

The server performance verification method provided in this embodiment, through the occurrence of real hardware errors, various real hardware errors occur and are recognized by the server; capture the real hardware error occurrence scheme and register and log information, and optimize the server performance test efficiency;

Further, multiple real hardwares are integrated and deployed to the server, so that multiple real hardware errors occur and are recognized by the server.

Furthermore, according to the read server configuration information, an error occurrence scheme conforming to the configuration of the server to be tested is formulated, and the adaptability to various servers is excellent.

Further, realize large-scale and continuous injection of real hardware errors;

Furthermore, by analyzing the errors, the hardware errors are refined step by step, resulting in a large number of diverse and complex hardware errors, which is very close to the real environment used by customers.

Embodiment 3: Corresponding to Embodiment 1 to Embodiment 2 above, the server performance verification system provided by this application will be introduced below with reference to FIG. 4 . Wherein, the system may be realized by means of hardware or software, or by a combination of software and hardware, which is not limited in this application.

In an example, the present application provides a server performance verification system, and the server performance verification system includes:

The receiving and generating module 410 is configured to receive an error injection instruction and generate a real hardware error occurrence scheme based on the error injection instruction;

A sending module 420, configured to send the hardware real error occurrence scheme to the target hardware, so that the target hardware generates a real error based on the hardware real error occurrence scheme;

The obtaining module 430 is used to obtain the log information of the real error, and obtain the hardware real error occurrence scheme and register information;

The processing module 440 is configured to process the real error based on the real error log information, the hardware real error occurrence scheme and the register information to verify the server performance.

In one embodiment, the reception generating module 410 includes:

A receiving unit 411, configured to receive an error injection instruction;

A reading unit 412, configured to read server hardware configuration information, the server hardware configuration information at least including: hardware model, hardware quantity, content capacity and memory location;

The generation unit 413 is configured to generate a real hardware error occurrence scheme based on the error injection instruction and the server hardware configuration information, and the hardware real error occurrence scheme at least includes an error list, an error priority, and an error type.

Preferably, the system also includes:

The display module 450 is used to display a preset error injection scheme on the human-computer interaction interface for the user to select to input an error before the receiving and generating module 410 receives the error injection instruction and generates a real hardware error occurrence scheme based on the error injection instruction. An injection instruction, the preset error injection scheme includes any one of custom errors, random errors and fault floods.

More preferably, the generating unit 413 is specifically configured to: receive user-defined hardware type information, user-defined error type information, user-defined error occurrence number information, and error location information;

A real hardware error occurrence solution is generated based on the user-defined hardware type information, user-defined error type information, user-defined error frequency information, error location information, and the server hardware configuration information.

More preferably, the generating unit 413 is specifically configured to: in response to the error injection scheme selected by the user being a random error, randomly generate a real hardware error occurrence scheme based on the server hardware configuration information.

More preferably, the generating unit 413 is specifically configured to: respond to the error injection scheme selected by the user as fault flood, randomly generate errors based on the server hardware configuration information for a preset period of time to generate a real hardware error occurrence scheme.

Preferably, the system also includes:

The first analysis module 460 is used for the sending module 420 to send the hardware real error occurrence scheme to the target hardware, so that the target hardware can analyze the hardware real error before generating a real error based on the hardware real error occurrence scheme The occurrence scheme obtains the real error category information of hardware, and the real error category information of the hardware includes at least one of CPU hardware error, memory hardware error, PCIE hardware error and other errors;

The second analysis module 470 is used to analyze the hardware real error occurrence scheme to obtain the target hardware layer information corresponding to the hardware real error category information;

The third parsing module 480 is configured to parse the hardware real error occurrence scheme to obtain the target error type information corresponding to the target hardware layer information;

The sending module 420 is specifically configured to: send the target hardware layer information and the target error type information to the target hardware based on the hardware real error type information.

More preferably, the first parsing module 460 is specifically used for:

Analyzing the hardware real error occurrence scheme based on the error priority and the error list to obtain hardware real error category information.

More preferably, the first parsing module 460 is further configured to generate a first error random number when parsing the hardware real error occurrence scheme to obtain the target error type information corresponding to the target hardware layer information;

The system also includes:

The correction module 490 is configured to correct the target hardware layer information based on the first error random number before the second parsing module 470 parses the hardware real error occurrence scheme to obtain the target hardware layer information corresponding to the hardware real error category information .

More preferably, the second parsing module 470 is further configured to generate a second error random number when parsing the hardware real error occurrence scheme to obtain the target error type information corresponding to the target hardware layer information;

The correction module 490 is further configured to correct the error based on the second error random number before the sending module 420 sends the target hardware layer information and the target error type information to the target hardware based on the hardware real error type information. The target error type information.

More preferably, the sending module 420 is specifically configured to: send the target hardware layer information and the target error type information to the target hardware in the form of error packets or error streams to generate real errors.

More preferably, the acquisition module 430 includes:

The grabbing unit 431 is configured to grab log information of the real error based on a preset interface, the preset interface including at least one of a serial port, an XDP interface, an IPMI interface, a redfish interface, and an SSH interface; The log information is reported by the target hardware to the OSkernel and BMC via the UEFI system after a real error occurs.

More preferably, the obtaining module 430 also includes:

The first acquiring unit 432 is configured to acquire a real hardware error occurrence scheme;

The second obtaining unit 433 is configured to obtain register information for error transmission and processing trigger register setting, where the register information includes at least SMI link information and CSMI link information.

More preferably, the second acquiring unit 433 is specifically configured to: acquire the register information transmitted to trigger register setting in the UEFI system after an error occurs.

More preferably, the processing module 440 is specifically configured to determine whether the real error log is consistent with the hardware real error occurrence scheme, and determine whether the register information is consistent with the hardware real error occurrence scheme;

If the real error log is consistent with the hardware real error occurrence scheme, and the register information is consistent with the hardware real error occurrence scheme, then the processing module 440 verifies that the performance of the server is qualified.

More preferably, the processing module 440 includes:

The first judging unit 441 is configured to judge whether the real error log is consistent with the error information in the hardware real error occurrence scheme, and the error information includes error type, error location, error times and error occurrence time.

More preferably, the processing module 440 also includes:

The second judging unit 442 is configured to judge whether the error type in the register information is consistent with the error type in the hardware real error occurrence scheme.

Embodiment 4: Corresponding to Embodiment 1 to Embodiment 3 above, the computer equipment provided by this application will be introduced below with reference to FIG. 5 . In an example, as shown in FIG. 5, the present application provides a computer device, which includes:

one or more processors;

And a memory associated with the one or more processors, the memory is used to store program instructions, and when the program instructions are read and executed by the one or more processors, perform the following operations:

receiving an error injection instruction and generating a real hardware error occurrence scheme based on the error injection instruction;

Sending the hardware real error occurrence scheme to the target hardware, so that the target hardware generates a real error based on the hardware real error occurrence scheme;

Obtain the log information of the real error, and obtain the hardware real error occurrence scheme and register information;

The real error is processed based on the log information of the real error, the hardware real error occurrence scheme and the register information to verify the performance of the server.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Receive error injection instructions;

Read server hardware configuration information, the server hardware configuration information at least includes: hardware model, hardware quantity, content capacity and memory location;

A real hardware error occurrence scheme is generated based on the error injection instruction and the server hardware configuration information, and the hardware real error occurrence scheme at least includes an error list, an error priority, and an error type.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

A preset error injection scheme is displayed on the human-computer interaction interface for the user to select to input an error injection command, and the preset error injection scheme includes any one of self-defined errors, random errors, and fault torrents.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Receive user-defined hardware type information, custom error type information, custom error occurrence times information, and error location information;

A real hardware error occurrence solution is generated based on the user-defined hardware type information, user-defined error type information, user-defined error frequency information, error location information, and the server hardware configuration information.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

A real hardware error occurrence scheme is randomly generated based on the server hardware configuration information.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Randomly generate errors based on the server hardware configuration information for a preset period of time to generate a real hardware error occurrence solution.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Analyzing the hardware real error occurrence scheme to obtain hardware real error category information, the hardware real error category information includes at least one of CPU hardware errors, memory hardware errors, PCIE hardware errors and other errors;

Analyzing the hardware real error occurrence scheme to obtain target hardware layer information corresponding to the hardware real error category information;

Analyzing the hardware real error occurrence scheme to obtain target error type information corresponding to the target hardware layer information;

The sending the real error occurrence scheme of the hardware to the target hardware includes:

Sending the target hardware layer information and the target error type information to target hardware based on the hardware real error type information.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Analyzing the hardware real error occurrence scheme based on the error priority and the error list to obtain hardware real error category information.

The first error random number is also generated when the solution for analyzing the real hardware error occurrence obtains the target error type information corresponding to the target hardware layer information;

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Correcting the target hardware layer information based on the first erroneous random number.

When the scheme for analyzing the real hardware error occurrence obtains the target error type information corresponding to the target hardware layer information, a second error random number is also generated.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Correcting the target error type information based on the second error random number.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Sending the target hardware layer information and the target error type information to target hardware in the form of error packets or error streams to generate real errors.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Grab the log information of the real error based on the preset interface, the preset interface includes at least one of a serial port, an XDP interface, an IPMI interface, a redfish interface and an SSH interface; the log information of the real error is generated by the target hardware After a real error occurs, it is reported to the OSkernel and BMC via the UEFI system for generation.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Obtain the real error occurrence scheme of the hardware;

Acquiring register information for error transfer and processing trigger register setting, where the register information at least includes SMI link information and CSMI link information.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Obtain the register information that is passed to the trigger register setting in the UEFI system after an error occurs.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Judging whether the log of the real error is consistent with the hardware real error occurrence scheme, and judging whether the register information is consistent with the hardware real error occurrence scheme;

If the real error log is consistent with the hardware real error occurrence scheme, and the register information is consistent with the hardware real error occurrence scheme, then verify that the performance of the server is qualified.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Judging whether the log of the real error is consistent with the error information in the hardware real error occurrence scheme, the error information includes error type, error location, error times, and error occurrence time.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Judging whether the error type in the register information is consistent with the error type in the hardware real error occurrence scheme.

When the program instructions are read and executed by the one or more processors, operations corresponding to the steps in the above method embodiments can also be performed, and reference can be made to the above description, which will not be repeated here. Referring to FIG. 5 , it exemplarily shows the architecture of a computer device, which may specifically include a processor 510 , a video display adapter 511 , a disk drive 512 , an input/output interface 513 , a network interface 514 , and a memory 520 . The processor 510 , video display adapter 511 , disk drive 512 , input/output interface 513 , network interface 514 , and the memory 520 can be connected by communication bus 530 .

Wherein, the processor 510 may be implemented by a general-purpose central processing unit (Central Processing Unit, CPU), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute related programs to Realize the technical solution provided by this application.

The memory 520 may be implemented in the form of a read-only memory (ReadOnlyMemory, ROM), a random access memory (RandomAccessMemory, RAM), a static storage device, a dynamic storage device, and the like. The memory 520 may store an operating system 521 for controlling the operation of the computer device 500 and a basic input output system (BIOS) 522 for controlling low-level operations of the computer device 500 . In addition, a web browser 523, a data storage management 524, an icon font processing system 525, etc. can also be stored. The above-mentioned icon font processing system 525 may be an application program in the embodiment of the present application that specifically implements the operations of the foregoing steps. In a word, when implementing the technical solutions provided by the present application through software or firmware, related program codes are stored in the memory 520 and invoked by the processor 510 for execution.

The input/output interface 513 is used to connect the input/output module to realize information input and output. The input/output/module can be configured in the device as a component (not shown in the figure), or can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, mouse, touch screen, microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, and the like.

The network interface 514 is used to connect the communication module (not shown in the figure), so as to realize the communication interaction between the device and other devices. The communication module can realize communication through wired means (such as USB, network cable, etc.), and can also realize communication through wireless means (such as mobile network, WIFI, Bluetooth, etc.).

Bus 530 includes a path for transferring information between the various components of the device (eg, processor 510, video display adapter 511, disk drive 512, input/output interface 513, network interface 514, and memory 520).

In addition, the computer device 500 can also obtain information on specific collection conditions from the virtual resource object collection condition information database 541 for condition judgment, and so on.

It should be noted that although the above computer device 500 only shows the processor 510, the video display adapter 511, the disk drive 512, the input/output interface 513, the network interface 514, the memory 520, the bus 530, etc., in the specific implementation process , the computer equipment may also include other components necessary for proper operation. In addition, those skilled in the art can understand that the above-mentioned device may only include components necessary to realize the solution of the present application, and does not necessarily include all the components shown in the figure.

It can be known from the above description of the implementation manners that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general-purpose hardware platform. Based on this understanding, the essence of the technical solution of this application or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products can be stored in storage media, such as ROM/RAM, disk , optical disc, etc., including several instructions to make a computer device (which may be a personal computer, a cloud server, or a network device, etc.) execute the methods described in various embodiments or some parts of the embodiments of the present application.

Embodiment 5: Corresponding to Embodiment 1 to Embodiment 4 above, the computer-readable storage medium provided by the present application will be introduced below. In one example, the present application provides a computer-readable storage medium, the computer-readable storage medium stores computer instructions, and the computer instructions cause the computer to perform the following operations:

receiving an error injection instruction and generating a real hardware error occurrence scheme based on the error injection instruction;

Sending the hardware real error occurrence scheme to the target hardware, so that the target hardware generates a real error based on the hardware real error occurrence scheme;

Obtain the log information of the real error, and obtain the hardware real error occurrence scheme and register information;

The real error is processed based on the log information of the real error, the hardware real error occurrence scheme and the register information to verify the performance of the server.

The computer instructions cause the computer to also perform the following operations:

Receive error injection instructions;

Read server hardware configuration information, the server hardware configuration information at least includes: hardware model, hardware quantity, content capacity and memory location;

A real hardware error occurrence scheme is generated based on the error injection instruction and the server hardware configuration information, and the hardware real error occurrence scheme at least includes an error list, an error priority, and an error type.

The computer instructions cause the computer to also perform the following operations:

A preset error injection scheme is displayed on the human-computer interaction interface for the user to select to input an error injection command, and the preset error injection scheme includes any one of self-defined errors, random errors, and fault torrents.

The computer instructions cause the computer to also perform the following operations:

Receive user-defined hardware type information, custom error type information, custom error occurrence times information, and error location information;

A real hardware error occurrence solution is generated based on the user-defined hardware type information, user-defined error type information, user-defined error frequency information, error location information, and the server hardware configuration information.

The computer instructions cause the computer to also perform the following operations:

A real hardware error occurrence scheme is randomly generated based on the server hardware configuration information.

When the program instructions are read and executed by the one or more processors, the following operations are also performed:

Randomly generate errors based on the server hardware configuration information for a preset period of time to generate a real hardware error occurrence scheme.

The computer instructions cause the computer to also perform the following operations:

Analyzing the hardware real error occurrence scheme to obtain hardware real error category information, the hardware real error category information includes at least one of CPU hardware errors, memory hardware errors, PCIE hardware errors and other errors;

Analyzing the hardware real error occurrence scheme to obtain target hardware layer information corresponding to the hardware real error category information;

Analyzing the hardware real error occurrence scheme to obtain target error type information corresponding to the target hardware layer information;

The sending the real error occurrence scheme of the hardware to the target hardware includes:

Sending the target hardware layer information and the target error type information to target hardware based on the hardware real error type information.

The computer instructions cause the computer to also perform the following operations:

Analyzing the hardware real error occurrence scheme based on the error priority and the error list to obtain hardware real error category information.

The first error random number is also generated when the solution for analyzing the real hardware error occurrence obtains the target error type information corresponding to the target hardware layer information;

The computer instructions cause the computer to also perform the following operations:

Correcting the target hardware layer information based on the first erroneous random number.

When the scheme for analyzing the real hardware error occurrence obtains the target error type information corresponding to the target hardware layer information, a second error random number is also generated.

The computer instructions cause the computer to also perform the following operations:

Correcting the target error type information based on the second error random number.

The computer instructions cause the computer to also perform the following operations:

Sending the target hardware layer information and the target error type information to target hardware in the form of error packets or error streams to generate real errors.

The computer instructions cause the computer to also perform the following operations:

Grab the log information of the real error based on the preset interface, the preset interface includes at least one of a serial port, an XDP interface, an IPMI interface, a redfish interface and an SSH interface; the log information of the real error is generated by the target hardware After a real error occurs, it is reported to the OSkernel and BMC via the UEFI system for generation.

The computer instructions cause the computer to also perform the following operations:

Obtain the real error occurrence scheme of the hardware;

Acquiring register information for error transfer and processing trigger register setting, where the register information at least includes SMI link information and CSMI link information.

The computer instructions cause the computer to also perform the following operations:

Obtain the register information that is passed to the trigger register setting in the UEFI system after an error occurs.

The computer instructions cause the computer to also perform the following operations:

Judging whether the log of the real error is consistent with the hardware real error occurrence scheme, and judging whether the register information is consistent with the hardware real error occurrence scheme;

If the real error log is consistent with the hardware real error occurrence scheme, and the register information is consistent with the hardware real error occurrence scheme, then verify that the performance of the server is qualified.

The computer instructions cause the computer to also perform the following operations:

Judging whether the log of the real error is consistent with the error information in the hardware real error occurrence scheme, the error information includes error type, error location, error times, and error occurrence time.

The computer instructions cause the computer to also perform the following operations:

Judging whether the error type in the register information is consistent with the error type in the hardware real error occurrence scheme.

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, please refer to part of the description of the method embodiment. The device embodiments described above are only illustrative, and the modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in One place, or it can be distributed to multiple network modules. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without creative effort.

In addition, it should be understood that the terms "first", "second", "third" and "fourth" in this application are only used for descriptive purposes, and should not be understood as indicating or implying relative importance or implying The number of technical characteristics indicated. Thus, a feature defined as "first", "second", "third" and "fourth" may expressly or implicitly include one or more of such features.

Of course, the above-mentioned embodiments are only for illustrating the technical conception and characteristics of the present invention, and its purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and not to limit the protection scope of the present invention. All modifications made according to the spirit of the main technical solutions of the present invention shall fall within the protection scope of the present invention.

Claims (20)

1. A server performance verification method, characterized in that the method comprises: receiving an error injection instruction and generating a real hardware error occurrence scheme based on the error injection instruction; Sending the hardware real error occurrence scheme to the target hardware, so that the target hardware generates a real error based on the hardware real error occurrence scheme; Obtain the log information of the real error, and obtain the hardware real error occurrence scheme and register information; The real error is processed based on the log information of the real error, the hardware real error occurrence scheme and the register information to verify the performance of the server. 2. The server performance verification method according to claim 1, wherein said receiving the error injection instruction and generating a real hardware error occurrence scheme based on the error injection instruction comprises: Receive error injection instructions; Read server hardware configuration information, the server hardware configuration information at least includes: hardware model, hardware quantity, content capacity and memory location; A real hardware error occurrence scheme is generated based on the error injection instruction and the server hardware configuration information, and the hardware real error occurrence scheme at least includes an error list, an error priority, and an error type. 3. The server performance verification method according to claim 2, wherein before receiving the error injection instruction and generating a real hardware error occurrence scheme based on the error injection instruction, the method further comprises: A preset error injection scheme is displayed on the human-computer interaction interface for the user to select to input an error injection command, and the preset error injection scheme includes any one of self-defined errors, random errors, and fault torrents. 4. The server performance verification method according to claim 3, wherein, in response to the error injection scheme selected by the user as a custom error, the real hardware error is generated based on the error injection instruction and the server hardware configuration information Happening scenarios include: Receive user-defined hardware type information, custom error type information, custom error occurrence times information, and error location information; A real hardware error occurrence solution is generated based on the user-defined hardware type information, user-defined error type information, user-defined error frequency information, error location information, and the server hardware configuration information. 5. The server performance verification method according to claim 3, wherein: In response to the error injection scheme selected by the user being a random error, the generating a real hardware error occurrence scheme based on the error injection instruction and the server hardware configuration information includes: A real hardware error occurrence scheme is randomly generated based on the server hardware configuration information. 6. The server performance verification method according to claim 3, wherein: In response to the error injection scheme selected by the user being a fault flood, the generating a real hardware error occurrence scheme based on the error injection instruction and the server hardware configuration information includes: Randomly generate errors based on the server hardware configuration information for a preset period of time to generate a real hardware error occurrence scheme. 7. The server performance verification method according to any one of claims 2-6, wherein the sending of the hardware real error occurrence scheme to the target hardware for the target hardware to occur based on the hardware real error Before the scenario produces a real error, the method also includes: Analyzing the hardware real error occurrence scheme to obtain hardware real error category information, the hardware real error category information includes at least one of CPU hardware errors, memory hardware errors, bus and interface standard hardware errors, and integrated South Bridge errors; Analyzing the hardware real error occurrence scheme to obtain target hardware layer information corresponding to the hardware real error category information; Analyzing the hardware real error occurrence scheme to obtain target error type information corresponding to the target hardware layer information; The sending the real error occurrence scheme of the hardware to the target hardware includes: Sending the target hardware layer information and the target error type information to target hardware based on the hardware real error type information. 8. The server performance verification method according to claim 7, wherein said analyzing said hardware real error occurrence scheme to obtain hardware real error category information comprises: Analyzing the hardware real error occurrence scheme based on the error priority and the error list to obtain hardware real error category information. 9. The method for verifying server performance according to claim 8, wherein said parsing said hardware real error occurrence scheme also generates a first error random number when obtaining target error type information corresponding to said target hardware layer information; Before the parsing of the hardware real error occurrence scheme to obtain the target error type information corresponding to the target hardware layer information, the method further includes: Correcting the target hardware layer information based on the first erroneous random number. 10. The server performance verification method according to claim 9, characterized in that, when analyzing the real hardware error occurrence scheme to obtain the target error type information corresponding to the target hardware layer information, a second error random number is also generated; Before sending the target hardware layer information and the target error type information to the target hardware based on the real hardware error type information, the method further includes: Correcting the target error type information based on the second error random number. 11. The server performance verification method according to claim 10, wherein the sending the hardware real error occurrence scheme to the target hardware for the target hardware to generate a real error based on the hardware real error occurrence scheme comprises : Sending the target hardware layer information and the target error type information to target hardware in the form of error packets or error streams to generate real errors. 12. The server performance verification method according to claim 11, wherein said acquiring log information of said real error comprises: Grab the log information of the real error based on the preset interface, the preset interface includes at least one of a serial port, an extended debugging port interface, an intelligent platform management interface, a redfish interface and an SSH interface; the log information of the real error is obtained by The target hardware is reported to the kernel of the operating system and generated by the baseboard management controller through the unified extensible firmware interface system after the real error occurs. 13. The method for verifying server performance according to claim 12, wherein said acquisition of a real hardware error occurrence scheme and register information comprises: Obtain the real error occurrence scheme of the hardware; Acquiring register information for error transfer and processing trigger register setting, where the register information at least includes serial management interface link information and CSMI link information. 14. The server performance verification method according to claim 13, wherein said acquisition of error transfer and processing trigger register setting register information comprises: Register information that is passed to trigger register setting in the unified extensible firmware interface system after an error occurs is acquired. 15. The server performance verification method according to claim 14, wherein the log information based on the real error, the hardware real error occurrence scheme and the register information process the real error to verify the Server capabilities include: Judging whether the log of the real error is consistent with the hardware real error occurrence scheme, and judging whether the register information is consistent with the hardware real error occurrence scheme; If the real error log is consistent with the hardware real error occurrence scheme, and the register information is consistent with the hardware real error occurrence scheme, then verify that the performance of the server is qualified. 16. The server performance verification method according to claim 15, wherein the judging whether the log of the real error is consistent with the hardware real error occurrence scheme comprises: Judging whether the log of the real error is consistent with the error information in the hardware real error occurrence scheme, the error information includes error type, error location, error times, and error occurrence time. 17. The server performance verification method according to claim 15, wherein the judging whether the register information is consistent with the hardware real error occurrence scheme comprises: Judging whether the error type in the register information is consistent with the error type in the hardware real error occurrence scheme. 18. A server performance verification system, characterized in that the system comprises: A receiving and generating module, configured to receive an error injection instruction and generate a real hardware error occurrence scheme based on the error injection instruction; A sending module, configured to send the hardware real error occurrence scheme to the target hardware, so that the target hardware generates a real error based on the hardware real error occurrence scheme; An obtaining module, configured to obtain the log information of the real error, and obtain the hardware real error occurrence scheme and register information; A processing module, configured to process the real error based on the real error log information, the hardware real error occurrence scheme, and the register information to verify the server performance. 19. A computer device, characterized in that the computer device comprises: one or more processors; And a memory associated with the one or more processors, the memory is used to store program instructions, and when the program instructions are read and executed by the one or more processors, perform any of the following claims 1-17 A method for verifying server performance. 20. A computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions cause the computer to perform the server performance verification according to any one of claims 1-17 method.