JP2022033610A - Device for electronic apparatus, control method for device for electronic apparatus, and control program for device for electronic apparatus - Google Patents

Abstract

To provide a device for an electronic apparatus that easily determines if a cause of inability to communicate with a processor is a communication interface by referring to a log, and a control method and a control program for the same.SOLUTION: In a system SYS, a device for an electronic apparatus 100 has a communication interface (endpoint) 20 that is connected with a CPU 200, a state detection unit 31, a register access detection unit 32, and a log generation unit 34. The communication interface has a plurality of operating states, and the state detection unit detects transition of the plurality of operating states and link information indicating a connection state between the processor and the communication interface at the detection of the transition. The register access detection unit detects the access to a storage unit performed by the processor. The log generation unit generates a log including the link information and transition information indicating the transition detected by the state detection unit and generates a log including access information indicating the access detected by the access detection unit.SELECTED DRAWING: Figure 1

Description

The present invention relates to a device for an electronic device, a control method for the device for the electronic device, and a control program for the device for the electronic device.

In recent years, semiconductor devices having a CPU (Central Processing Unit) interface and having a module accessible to the CPU have been used in various electronic devices. An example of an electronic device is an image forming apparatus such as a copier.

In the analysis when a failure occurs in such an electronic device, a debugging device such as an ICE (In Circuit Emulator) is used in a conventional general method. The debug device can trace the access contents of the CPU or set a desired value in the register to investigate the cause of the failure.

However, when investigating the cause of a failure with a debug device, the debug device is brought to the analysis location and connected to the electronic device to be analyzed, so it takes time and effort to prepare for analysis. Further, when the CPU is built in the device mounted on the electronic device, the debug device cannot be connected to the CPU interface, so that the analysis by the debug device cannot be performed.

In order to solve such a problem, a method of monitoring access to a register from the CPU, creating log information of the detected register access, and saving the created log to the built-in memory so that it can be output to the outside is known. (See, for example, Patent Document 1).

Further, there is known an arithmetic unit having a processor, a main storage device for storing an operation log of the processor, and a log collection device connected to the processor via a PCI (Peripheral Component Interconnect) Express bus. The log collecting device includes a watchdog timer that monitors a signal output from the processor at a predetermined cycle, a DMAC (Direct Memory Access Controller), and a storage unit.

When the watchdog timer detects that the processor is inoperable, the log collecting device uses the DMAC to transfer the operation log held in the main storage device to the storage unit at high speed. This makes it possible to acquire an operation log even when the processor cannot operate (see, for example, Patent Document 2).

However, the log collection device does not acquire the link information of PCI Express as a log. Therefore, when the DMAC cannot acquire the operation log from the main storage device, the log collecting device cannot determine whether the cause is due to the link down of PCI Express. In order to acquire the link information of PCI Express as a log, it is necessary to connect the debug device to the external terminal that can output the link information etc. and analyze the link information acquired by the debug device, which is very troublesome. rice field.

The disclosed technique has been made in view of the above problems, and an object thereof is to easily determine whether or not the cause of the inability to communicate with the processor is the communication interface by referring to the log.

In order to solve the above technical problem, the device for an electronic device of one embodiment of the present invention is connected to a processor and has a communication interface having a plurality of operating states, a transition of the plurality of operating states, and a time of detecting the transition. The state detection unit that detects the link information indicating the connection state between the processor and the communication interface, the access detection unit that detects the access of the storage unit by the processor, and the transition detected by the state detection unit are shown. It is characterized by having a log generation unit that generates a log including transition information and the link information, and generates a log including access information indicating the access detected by the access detection unit.

It is possible to easily determine whether the cause of the inability to communicate with the processor is the communication interface by referring to the log.

It is a block diagram which shows an example of the device for the electronic device in 1st Embodiment of this invention. It is a flow figure which shows an example of the operation of the debug controller of FIG. It is a flow diagram which shows another example of the operation of the debug controller of FIG. It is a block diagram which shows an example of the device for the electronic device in 2nd Embodiment of this invention. It is explanatory drawing which shows an example of the format of the log of the link state of PCIe. It is a block diagram which shows an example of the format of a register access log. It is a block diagram which shows an example of the device for the electronic device in 3rd Embodiment of this invention. It is a block diagram which shows an example of the device for the electronic device in 4th Embodiment of this invention.

Hereinafter, embodiments will be described with reference to the drawings. In each drawing, the same components may be designated by the same reference numerals and duplicate explanations may be omitted. In the following, the code indicating a signal is also used as a code indicating a signal line.

(First Embodiment)
FIG. 1 is a block diagram showing an example of a device for an electronic device according to the first embodiment. The device 100 for electronic devices shown in FIG. 1 is connected to the CPU 200 via the PCI Express bus and the root complex 300 of the PCI Express. PCI Express is also referred to as PCIe. The CPU 200 and the device 100 for electronic devices can communicate with each other via the PCIe bus. The CPU 200 is an example of a processor.

The device 100 for electronic devices includes a PCIe physical layer interface (PHY) 10, a PCIe endpoint 20, and a debug controller 30. The PHY 10 receives a control signal, a data signal, or the like from the CPU 200 via the route complex 300 and the PCIe bus, and transfers the received signal to the endpoint 20. Although the endpoint 20 is connected only to the debug controller 30 in FIG. 1, it can actually be connected to various devices. PHY10 is an example of a communication interface and an example of a PCI Express interface.

The endpoint 20 manages PCIe links, detects errors, and the like. The endpoint 20 outputs LTSSM information indicating the state of the LTSSM (Link Training and Status State Machine), link information indicating the status of the PCIe link, and a register access signal issued by the CPU 200. The link information is information indicating the connection state between the CPU 200 and the PHY 10. The LTSSM information and the link information are supplied to the debug controller 30. The register access signal is supplied to the outside of the debug controller 30 and the device 100 for electronic devices.

The register access signal output from the CPU 200 is used, for example, to access a register included in various functional modules (not shown) mounted on the system SYS. The register is an example of a storage unit. The various functional modules may be mounted on the device 100 for electronic devices. The operation mode and the like of various functional modules are switched according to the set value of the register. The CPU 200 can read not only the value set in the register but also the value set in the register by the register access signal.

The debug controller 30 has a state detection unit 31, a register access detection unit 32, an arbitration unit 33, a log generation unit 34, and a log holding unit 35. The state detection unit 31, the register access detection unit 32, the arbitration unit 33, and the log generation unit 34 may be realized by hardware or software. When realized by software, the state detection unit 31, the register access detection unit 32, the arbitration unit 33, and the log generation unit 34 are realized by a control program executed by a computer such as a CPU (not shown) mounted on the debug controller 30. .. Then, by executing the control program, a control method for the device 100 for an electronic device is realized.

The state detection unit 31 detects the transition of the LTSSM state based on the LTSSM information, and outputs change information including the transition information and the link information indicating the detected transition to the arbitration unit 33. The LTSMM state is an example of a plurality of operating states that the LTSSM can take. For example, when the state detection unit 31 detects a change in both the LTSSM state and the LTSSM substate, the state detection unit 31 mediates the change information including the transition information including the state information before the transition and the information of the state after the transition and the link information. Output to unit 33.

The register access detection unit 32 detects the occurrence of register access based on the register access signal output from the endpoint 20. When the register access detection unit 32 detects the occurrence of register access, the register access detection unit 32 outputs access information indicating the address, data, read / write type, etc. included in the register access signal to the arbitration unit 33. The register access detection unit 32 is an example of an access detection unit that detects register access by the CPU 200.

The arbitration unit 33 outputs the received change information to the log generation unit 34, and outputs the received access information to the log generation unit 34. When the arbitration unit 33 receives the change information and the access information at the same time, the arbitration unit 33 performs an arbitration process for determining the order of output to the log generation unit 34, and logs the change information and the access information according to the order determined by the arbitration process. It is sequentially output to the generation unit 34. For example, when the change information and the access information are received in the same reception cycle, the arbitration unit 33 determines simultaneous reception and executes the arbitration process.

The log generation unit 34 generates a log recording change information or access information received from the arbitration unit 33 in the order of reception from the arbitration unit 33. Therefore, the order determined by the arbitration unit 33 by the arbitration process is also the log generation order. For example, the log generation unit 34 generates a log including each state before and after the transition of the LTSSM received from the arbitration unit 33 and the link information. Further, the log generation unit 34 generates a log including access information indicating the register access received from the arbitration unit 33. The log generation unit 34 stores the generated log in the log holding unit 35.

For example, the information stored in the log holding unit 35 can be read from the outside of the debug controller 30 via a serial interface (not shown) or the like. The log holding unit 35 may be provided outside the debug controller 30. In order to operate the debug controller 30 only during debugging and stop it at times other than debugging, even if an enable signal for enabling the operation of the debug controller 30 is supplied to the debug controller 30 from the outside of the device 100 for electronic devices. good.

By providing the debug controller 30 in the device 100 for electronic devices, it is possible to record not only after the link-up of the PCIe link but also the change in the state of the LTSSM during the lick-up and the link state of the PCIe link as a log. As a result, the behavior of the PCIe link during link-up can be recorded as a log, and the defect during link-up can be debugged. For example, it is possible to easily identify the cause when the PCIe link does not link up.

As a result, when communication cannot be performed between the CPU 200 and the device 100 for electronic devices, it is possible to easily determine whether or not the cause lies in the PCIe interface by referring to the log. Therefore, a developer or the like who develops a system SYS including a CPU 200 and a device 100 for an electronic device can debug whether or not the operation of the PCIe link is normal based on the generated log.

Further, it is possible to check the state of the LTSSM at the time of starting the system SYS (that is, at the time of linking up the PCIe link) without preparing a debugging device for constantly monitoring the change of the state of the LTSSM. As a result, debugging of the system SYS can be facilitated as compared with the conventional case.

FIG. 2 is a flow chart showing an example of the operation of the debug controller 30 of FIG. The flow shown in FIG. 2 is started, for example, based on the activation of the device 100 for an electronic device and the start of the link-up by PCIe. Since the debug controller 30 is mounted on the device 100 for electronic devices, the flow shown in FIG. 3 may be started when the device 100 for electronic devices is started.

First, in step S10, the debug controller 30 detects whether or not the state transition of the LTSSM has occurred by the state detection unit 31. The debug controller 30 executes step S12 when a transition of the LTSSM state occurs. The debug controller 30 repeats the determination in step S10 until the transition of the LTSSM state occurs. The debug controller 30 executes step S12 when the state detection unit 31 detects a transition of both the LTSSM state and the LTSSM substate in step S10.

In step S12, the debug controller 30 records the pre-transition and post-transition states and link information of the LTSSM by the log generation unit 34. Next, in step S14, the debug controller 30 generates a log including the recorded information by the log generation unit 34, and ends the operation shown in FIG. For example, the log generated by the log generation unit 34 is held in the log holding unit 35.

As shown in FIG. 2, the debug controller 30 can detect a change in the LTSSM state immediately after the start of PCIe link-up and record it together with the link information. That is, the debug controller 30 can record a defect or the like that occurs during link-up as a log.

FIG. 3 is a flow chart showing another example of the operation of the debug controller 30 of FIG. The flow shown in FIG. 3 is started, for example, based on the fact that the CPU 200 is started. When the device 100 for an electronic device is mounted on the same substrate as the CPU 200 and is started at the same time as the CPU 200, the flow shown in FIG. 3 may be started at the same time as the device 100 for the electronic device is started.

First, in step S20, the debug controller 30 determines whether or not the CPU 200 has performed register access based on the register access signal. When the register access is executed, the debug controller 30 executes step S22. The debug controller 30 repeats the determination in step S20 until the register access is performed.

In step S22, the debug controller 30 records the address, data, and read / write type of the register access performed by the CPU 200. Next, in step S24, the debug controller 30 generates a log including the recorded information by the log generation unit 34, and ends the operation shown in FIG. For example, the log generated by the log generation unit 34 is held in the log holding unit 35.

As described above, in the first embodiment, the debug controller 30 is provided in the device 100 for electronic devices. Therefore, not only after the PCIe link is linked up, but also the change in the LTSSM state during the lick-up and the link state of the PCIe link can be recorded as a log. As a result, the behavior of the PCIe link during link-up can be recorded as a log, and the defect during link-up can be debugged. For example, it is possible to easily identify the cause when the PCIe link does not link up.

As a result, when communication cannot be performed between the CPU 200 and the device 100 for electronic devices, it is possible to easily determine whether or not the cause lies in the PCIe interface by referring to the log. Therefore, a developer or the like who develops a system SYS including a CPU 200 and a device 100 for an electronic device can debug whether or not the operation of the PCIe link is normal based on the generated log.

Further, it is possible to check the state of the LTSSM at the time of starting the system SYS (that is, at the time of linking up the PCIe link) without preparing a debugging device for constantly monitoring the change of the state of the LTSSM. As a result, debugging of the system SYS can be facilitated as compared with the conventional case.

(Second embodiment)
FIG. 4 is a block diagram showing an example of a device for an electronic device according to a second embodiment of the present invention. The same elements as in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The device 100 for an electronic device shown in FIG. 4 has a debug controller 30A instead of the debug controller 30 of FIG. Other configurations and functions of the device 100 for electronic devices are the same as those in FIG. 1.

The debug controller 30A has an arbitration unit 33A instead of the arbitration unit 33 in FIG. Further, the debug controller 30A adds a time counting unit 36 to the debug controller 30 of FIG. The time count unit 36 outputs the count value CNT to the arbitration unit 33A. Other configurations and functions of the debug controller 30A are the same as those of the debug controller 30 of FIG. The state detection unit 31, the register access detection unit 32, the arbitration unit 33A, and the log generation unit 34 may be realized by hardware or software, as in the debug controller 30 of FIG.

The time counting unit 36 starts operation when the electronic device device 100 is started, counts the time, and outputs the counted time as a count value CNT to the arbitration unit 33A. For example, the time counting unit 36 counts the number of clocks of a clock signal (not shown) as time based on the reset signal released when the device 100 for an electronic device is started. The clock signal supplied to the time count unit 36 may be a clock signal for operating the electronic device device 100, or may be a clock signal obtained by dividing the frequency of the clock signal for operating the electronic device device 100. The time count unit 36 is an example of a timer. The count value CNT output by the time count unit 36 is an example of time information.

When the arbitration unit 33A receives the change information or the access information including the transition information and the link information, the arbitration unit 33A adds the count value CNT being counted by the time counting unit 36 to the change information or the access information. When the arbitration unit 33A receives the change information and the access information at the same time, the arbitration unit 33A adds the same count value CNT to the change information and the access information. Then, the arbitration unit 33A outputs the change information to which the count value CNT is added or the access information to which the count value CNT is added to the log generation unit 34.

For example, the log generation unit 34 receives change information and access information to which the same count value CNT is added at different timings, and generates each log. Therefore, for example, when a log containing change information and a log containing access information are generated in this order, whether the LTSSM state transition and register access occur in the order in which the logs are generated or at the same time. Can be determined by the count value CNT. As a result, the developer who develops the system SYS including the CPU 200 and the device 100 for the electronic device can accurately grasp the operation of the PCIe link based on the log including the count value CNT, and improves the debugging efficiency. be able to.

FIG. 5 is an explanatory diagram showing an example of the format of the PCIe link state log. The log generation unit 34 generates change information received and recorded from the arbitration unit 33A as a log in the format shown in FIG. The log has an area of 8 bytes for each change information (upper byte 7 and lower byte 0).

In the 5-byte area of bytes 7-byte 3, the 40-bit count value CNT counted by the time count unit 36 in FIG. 4 is stored as count information time_ctt [39: 0]. The power management information Powerdun [1: 0] is stored in the bit 5-bit 4 of the byte 2. The amplitude information txswing of the transmission signal is stored in the bit 3 of the byte 2. "0" of the amplitude information txswing indicates a full swing, and "1" of the amplitude information txswing indicates a half swing (low voltage specification).

Waveform information txdeemp is stored in bit 2 of the byte 2. A "1" in the waveform information txdeemph indicates selection of de-emphasis, and a "0" in the waveform information txdeemph indicates selection of Coefficient. The transfer rate information link_spd is stored in bit 1 of byte 2.

A "0" in the transfer rate information link_spd indicates GEN1 (PCI Express 1.1), and a "1" in the transfer rate information link_spd indicates GEN2 (PCI Express 2.0). Link-up information dl_up is stored in bit 0 of byte 2. A "0" in the link-up information dl_up indicates a communicable state, and a "1" in the link-up information dl_up indicates a communicable state (that is, a link-up state).

Bit 7-bit 4 of byte 1 stores the state information ltssm_before before the transition of LTSSM. Bit 2-bit 0 of byte 1 stores substate information ltssm_st_before before the transition of LTSSM. The state information ltssm_after after the transition of LTSSM is stored in bit 7-bit 4 of byte 0. Bit 2-bit 0 of byte 0 stores substate information ltssm_st_after after the transition of LTSSM. Note that "0" is stored in the bit in which none of the above information is stored.

FIG. 6 is a block diagram showing an example of a register access log format. The log generation unit 34 generates the access information received and recorded from the arbitration unit 33A as a log in the format shown in FIG. The log has an area of 16 bytes (upper byte group and lower byte group) for each access information.

The most significant bit of the high-order byte group and the low-order byte group stores identification information num [0] for distinguishing the high-order byte group and the low-order byte group. "1" is stored in the identification information num of the upper byte group, and "0" is stored in the identification information num of the lower byte group. The count value CNT is stored as 40-bit count information time_ct [39: 0] in the 5-byte area of bytes 4-byte 0 of the high-order byte group.

Read / write information rw for register access is stored in bit 6 of byte 7 of the lower byte group. A "0" in the read / write information rw indicates a read access, and a "1" in the read / write information rw indicates a write access. Bit 5 of byte 7 of the lower byte group to bit 0 of byte 4 store 30-bit address information addr [29: 0] indicating an access address. Byte 3-byte 0 of the lower byte group stores data information data [31: 0] indicating data. "0" is stored in the other areas of the high-order byte group and the low-order byte group.

As described above, the same effect as that of the first embodiment can be obtained in the second embodiment. Further, in the second embodiment, when the arbitration unit 33A receives the change information or the access information, the count value CNT is added to the change information or the access information, and the log generation unit 34 adds the count value CNT to each of the change information and the access information. Generate a log with a log attached. Thereby, it is possible to determine whether the transition of the LTSSM state and the register access occur in the order of log generation or at the same time by the count value CNT. As a result, the developer of the system SYS can accurately grasp the operation of the PCIe link in the debugging of the system SYS, and the debugging efficiency can be improved.

(Third embodiment)
FIG. 7 is a block diagram showing an example of a device for an electronic device according to a third embodiment of the present invention. The same elements as those in FIGS. 1 and 4 are designated by the same reference numerals, and detailed description thereof will be omitted. The device 100 for an electronic device shown in FIG. 7 has a debug controller 30B instead of the debug controller 30 of FIG. Other configurations and functions of the device 100 for electronic devices are the same as those in FIG. 1.

Further, in this embodiment, the system SYS including the CPU 200 and the device 100 for electronic devices has a large-capacity memory 400 and a data bus DB connecting the large-capacity memory 400 and the device 100 for electronic devices. Further, the signal line for transmitting the register access signal output by the endpoint 20 is connected to the data bus DB. The large-capacity memory 400 is an example of an external memory that can store the log generated by the log generation unit 34.

The debug controller 30B adds a time count unit 36, a memory interface unit 37, a built-in memory 38, and a DMA transfer unit 39 to the debug controller 30 of FIG. Further, the debug controller 30B has an arbitration unit 33B instead of the arbitration unit 33 in FIG. 1, and has a log generation unit 34B instead of the log generation unit 34. The state detection unit 31, the register access detection unit 32, the arbitration unit 33B, and the log generation unit 34B may be realized by hardware or software, as in the debug controller 30 of FIG.

The memory interface unit 37 is connected to the arbitration unit 33B, the built-in memory 38, and the log generation unit 34B. The log generation unit 34B is connected to the memory interface unit 37 and the DMA transfer unit 39. For example, the built-in memory 38 is a dual port memory having a write port WP and a read port RP. The DMA transfer unit 39 is connected to the large-capacity memory 400 via the data bus DB, and can transfer data or the like to the large-capacity memory 400 at high speed without imposing a load on the CPU 200. Similar to the time counting unit 36 shown in FIG. 4, the time counting unit 36 counts the time from the start of the electronic device device 100, and outputs the counted time as a count value CNT to the arbitration unit 33B.

The arbitration unit 33B has a function of storing change information and access information in the built-in memory 38 via the memory interface unit 37. For example, the large-capacity memory 400 may not be immediately accessible via the data bus DB due to initialization processing such as formatting at the time of starting the system SYS. During the period when the large-capacity memory 400 cannot be accessed, the arbitration unit 33B sends a write request to write at least one of the change information received from the state detection unit 31 and the access information received from the register access detection unit 32 to the built-in memory 38. Output to 37.

The memory interface unit 37 generates a write command including at least one of change information and access information based on the received write request, and outputs the generated write command to the write port WP of the built-in memory 38. Then, at least one of the change information and the access information is written in the built-in memory 38. As a result, even when the change information or access information cannot be stored in the large-capacity memory 400 at the time of starting the system SYS, the change information or access information generated during the start of the system SYS can be retained without loss. can.

On the other hand, it is assumed that the startup of the system SYS is completed, the data bus DB becomes available, and information can be written from the debug controller 30B to the large-capacity memory 400 by the DMA transfer unit 39. In this case, the log generation unit 34B receives a signal from the DMA transfer unit 39 indicating that the DMA transfer to the data bus DB has become possible. Further, the log generation unit 34B outputs a read request for reading the change information and the access information held in the built-in memory 38 from the built-in memory 38 to the memory interface unit 37.

The memory interface unit 37 generates a read command based on the received read request, outputs the command to the read port RP of the built-in memory 38, and reads change information and access information from the built-in memory 38. The memory interface unit 37 outputs the change information and the access information read from the built-in memory 38 to the log generation unit 34B as a response to the read request.

The arbitration unit 33B mediates the change information received from the state detection unit 31 and the access information received from the register access detection unit 32 after the start-up of the system SYS is completed, and then the log generation unit via the memory interface unit 37. It has a function to output to 34B. The log generation unit 34B outputs the change information and the access information received from the memory interface unit 37 to the DMA transfer unit 39 together with the transfer request to the large-capacity memory 400. The DMA transfer unit 39 performs DMA transfer of the received change information and access information to the large-capacity memory 400 via the data bus DB.

In this embodiment, the change information and access information generated during the startup of the system SYS and the change information and access information generated after the startup of the system SYS are transferred to the large-capacity memory 400 in no particular order. However, since the count value CNT is added to the change information and the access information by the arbitration unit 33B, by referring to the count value CNT, the generation time of the change information and the access information written in the large capacity memory 400 in no particular order can be obtained. The order can be determined.

The change information and access information written in the large-capacity memory 400 by DMA transfer can be read out via a serial interface or the like that can access the data bus DB. Therefore, the developer of the system SYS or the like reads the log including the change information to which the count value CNT is added and the log including the access information to which the count value CNT is added from the large-capacity memory 400 when debugging the system SYS. Can be done. Since the change information and access information read from the large-capacity memory 400 include those generated during the startup of the system SYS, the developer and the like can accurately grasp the operation of the PCIe link and improve the debugging efficiency. can do.

As described above, the same effects as those of the first and second embodiments can be obtained in the third embodiment. Further, in the third embodiment, the debug controller 30B is provided with the memory interface unit 37 and the built-in memory 38. As a result, even when the change information or the access information cannot be stored in the large-capacity memory 400 at the time of starting the system SYS, the change information or the access information generated during the start of the system SYS is not lost in the built-in memory 38. Can be retained.

The change information and access information transferred from the built-in memory 38 to the large capacity memory 400 after the large capacity memory 400 becomes accessible includes the count value CNT. Therefore, by referring to the count value CNT included in the log written in the large-capacity memory 400 in no particular order, the LTSSM state transition occurrence time indicated by the change information and the register access occurrence time indicated by the access information can be determined. The order can be determined.

(Fourth Embodiment)
FIG. 8 is a block diagram showing an example of a device for an electronic device according to a fourth embodiment of the present invention. The same elements as those in FIGS. 1, 4 and 7 are designated by the same reference numerals, and detailed description thereof will be omitted. The device 100 for an electronic device shown in FIG. 8 has a debug controller 30C instead of the debug controller 30B in FIG. 7. Other configurations and functions of the device 100 for electronic devices and the configuration of the system SYS including the CPU 200 and the device 100 for electronic devices are the same as those in FIG. 7.

The debug controller 30C has an arbitration unit 33C instead of the arbitration unit 33B of the debug controller 30B of FIG. 7, and has a log generation unit 34C instead of the log generation unit 34B of the debug controller 30B of FIG. Further, the debug controller 30C has a memory interface unit 37C instead of the memory interface unit 37 in FIG. 7. The state detection unit 31, the register access detection unit 32, the arbitration unit 33C, and the log generation unit 34C may be realized by hardware or software, as in the debug controller 30 of FIG. The built-in memory 38 may be a single port memory.

The memory interface unit 37C is connected to the arbitration unit 33C and the built-in memory 38. The log generation unit 34C is connected to the arbitration unit 33C and the DMA transfer unit 39.

The arbitration unit 33C has a function of storing change information and access information in the built-in memory 38 via the memory interface unit 37C. Further, the arbitration unit 33C has a function of reading change information and access information stored in the built-in memory 38 from the built-in memory 38 via the memory interface unit 37C. Further, the arbitration unit 33C has a function of outputting change information and access information to the log generation unit 34, similarly to the arbitration unit 33 of FIG.

Similar to the arbitration unit 33B shown in FIG. 7, the arbitration unit 33C outputs a write request for writing at least one of the change information and the access information to the built-in memory 38 to the memory interface unit 37C. The memory interface unit 37C generates a write command including at least one of change information and access information based on the received write request, and outputs the generated write command to the write port WP of the built-in memory 38. Then, at least one of the change information and the access information is written in the built-in memory 38.

On the other hand, when the startup of the system SYS is completed and the large-capacity memory 400 becomes accessible, the arbitration unit 33C sends a read request to read the change information and the access information held by the internal memory 38 from the internal memory 38. Output to 37C. The memory interface unit 37C generates a read command based on the received read request, outputs the command to the built-in memory 38, and reads the change information and the access information from the built-in memory 38. The memory interface unit 37C outputs the change information and the access information read from the built-in memory 38 to the arbitration unit 33C as a response to the read request.

The arbitration unit 33C outputs the change information and access information received from the memory interface unit 37C to the log generation unit 34C. Further, the arbitration unit 33C outputs the change information received from the state detection unit 31 and the access information received from the register access detection unit 32 to the log generation unit 34C after arbitration after the start-up of the system SYS is completed.

Similar to the log generation unit 34B shown in FIG. 7, the log generation unit 34C outputs the change information and the access information received from the arbitration unit 33C to the DMA transfer unit 39 toward the large-capacity memory 400. The DMA transfer unit 39 performs DMA transfer of the received change information and access information to the large-capacity memory 400 via the data bus DB.

As described above, the same effect as that of the first to third embodiments can be obtained in the fourth embodiment.

Although the present invention has been described above based on each embodiment, the present invention is not limited to the requirements shown in the above embodiments. With respect to these points, the gist of the present invention can be changed to the extent that the gist of the present invention is not impaired, and can be appropriately determined according to the application form thereof.

10 Physical layer interface (PHY)
20 Endpoint 30, 30A, 30B, 30C Debug controller 31 Status detection unit 32 Register access detection unit 33, 33A, 33B, 33C Mediation unit 34, 34B, 34C Log generation unit 35 Log retention unit 36 Time count unit 37, 37C Memory Interface unit 38 Built-in memory 39 DMA transfer unit 100 Electronic device device 200 CPU
300 Route Complex CNT Count Value DB Data Bus SYS System

Japanese Patent No. 6127766 Japanese Unexamined Patent Publication No. 2014-182676

Claims (6)

A communication interface that is connected to a processor and has multiple operating states,
A state detection unit that detects the transition of the plurality of operating states and the link information indicating the connection state between the processor and the communication interface at the time of detecting the transition.
An access detection unit that detects access to the storage unit by the processor, and an access detection unit.
A log generation unit that generates a log including the transition information indicating the transition detected by the state detection unit and the link information, and generates a log including the access information indicating the access detected by the access detection unit.
A device for an electronic device characterized by having. When the transition detection by the state detection unit and the access detection by the access detection unit occur at the same time, the arbitration unit that determines the generation order of the logs generated by the log generation unit.
It has a timer that outputs time information indicating the time, and
The arbitration unit outputs the time information at the time of detecting the transition to the log generation unit together with the transition information and the link information, and outputs the time information at the time of detecting the access together with the access information indicating the access. Output to the log generator
The device for an electronic device according to claim 1, wherein the log generation unit generates a log in which the transition information, the link information, and the time information are added to the access information. A built-in memory capable of storing the transition information, the link information, and the access information, and
It has an external memory that is connected to the outside of the device for an electronic device and can store a log generated by the log generation unit.
The arbitration section
During the period when the external memory cannot be accessed, the transition information, the link information, and the access information are stored in the built-in memory.
When the external memory becomes accessible, the transition information, the link information, and the access information are read from the built-in memory and output to the log generation unit.
The device for an electronic device according to claim 2, wherein the log generation unit outputs the generated log to the external memory. The communication interface is a PCI Express interface.
The device for an electronic device according to any one of claims 1 to 3, wherein the state detection unit detects a transition of the status of the link training status state machine. A method for controlling a device for an electronic device, which is connected to a processor and has a communication interface having a plurality of operating states.
The transition of the plurality of operating states and the link information indicating the connection state between the processor and the communication interface at the time of detecting the transition are detected.
Detecting the access of the storage unit by the processor,
A method for controlling a device for an electronic device, which comprises generating a log including the detected transition information indicating the transition and the link information, and generating a log including the detected access information indicating the access. A control program for a device for an electronic device that is connected to a processor and has a communication interface having multiple operating states.
The transition of the plurality of operating states and the link information indicating the connection state between the processor and the communication interface at the time of detecting the transition are detected.
Detecting the access of the storage unit by the processor,
A device for an electronic device characterized by generating a log including the detected transition information indicating the transition and the link information, and causing a computer to execute a process of generating a log including the detected access information indicating the access. Control program.

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