CN111221694A - Built-in self-test method and system for receiving and transmitting path of Ethernet controller - Google Patents
Built-in self-test method and system for receiving and transmitting path of Ethernet controller Download PDFInfo
- Publication number
- CN111221694A CN111221694A CN202010033571.0A CN202010033571A CN111221694A CN 111221694 A CN111221694 A CN 111221694A CN 202010033571 A CN202010033571 A CN 202010033571A CN 111221694 A CN111221694 A CN 111221694A
- Authority
- CN
- China
- Prior art keywords
- test
- module
- path
- data frame
- self
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2268—Logging of test results
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
The invention discloses a built-in self-test method and a built-in self-test system for a receiving and transmitting path of an Ethernet controller, wherein a path for data to wrap from a transmitting path to a receiving path is constructed by adopting the concept of loop-back in a chip; generating test excitation in the controller and comparing and analyzing the result to judge whether the core function and the transceiving channel of the controller operate normally or not and automatically position when a fault occurs; meanwhile, a pin multiplexing mode is adopted, and flexible configuration and output of a test mode and a test result are realized.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a built-in self-test method and a built-in self-test system for a transmitting and receiving channel of an Ethernet controller, which are particularly suitable for chips which have limitations on the number of pins and hardware resources of the controller, complex interface protocols and higher requirements on electrical characteristics, such as low-power-consumption embedded gigabit Ethernet controllers, gigabit Ethernet controllers and the like.
Background
Currently, in mainstream ethernet controllers, the interface bandwidth can reach or exceed 1000 Mbps. In other words, gigabit and higher bandwidth ethernet controllers occupy a significant portion of the market. In fact, the maximum bandwidth of current ethernet networks can reach 100Gbps, and the next generation of 400Gbps standards are being established.
However, the increasing bandwidth of the network interface brings new difficulties and higher test costs to the test work of the ethernet controller chip. On one hand, physical electrical signals and protocol specifications of a high-speed interface are more and more complex, so that the generation difficulty of test vectors is continuously increased, and the test period and the risk are increased; on the other hand, the difficulty of sampling and analyzing data sent by the high-speed interface is increased, so that the performance requirement of ATE test equipment is continuously improved, and the test cost is increased.
The Built-In Self Test (BIST) technology does not depend on expensive Test equipment, and can complete Self Test only by depending on the Self structure of a chip, so that the Test complexity and the Test cost can be greatly reduced under the condition of ensuring the Test speed. However, most of the current BIST technologies are applied to testing and scanning of internal memory resources of a chip, and logic built-in self-test for a specific functional level of the chip cannot be unified and standardized. In particular, for ethernet controller chips, self-test methods for their core data transceiving functions have not been commonly applied and less research effort has been associated.
One of the existing technologies is to encode a physical layer digital control system through a Verilog hardware description language, and embed a perfect built-in self-test system therein to facilitate chip testing, so as to implement self-test of a Rapid IO physical chip. However, the method only aims at the physical layer application of Rapid IO, and self test of the whole controller is not realized, so that the method has great limitation in practical application. In addition, the method needs to configure a plurality of registers through a peripheral interface in the test process, and the registers need to be read after the test is finished to obtain the result, so that the operation flow is complex, the steps are complex, and the user friendliness is insufficient. There is also a way to analyze and discuss the types of faults mainly contained in the chip and to propose a complete set of testable design solutions for the controller chip. Although the scheme also adopts a built-in self-test method, the built-in self-test method only realizes the built-in self-test of the memory and does not involve the test of the core function level of the controller. And the test data packet is transmitted in parallel by adopting an improved multicast routing algorithm, the test excitation circuit and the response analysis circuit are added in the tested circuit, and the test time is reduced by adopting a test and data transmission parallel execution strategy. It is only applicable to circuits or devices such as switching, routing, etc., and is not applicable to network terminal devices such as ethernet controllers. In addition, the test mode is single, and the test of different load pressures and different data forwarding types cannot be provided, so that the functionality and the practicability of the test device still have a larger optimization space.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a built-in self-test method and system for the transceiving path of the ethernet controller, which effectively solve the problems of high complexity of test excitation generation, high difficulty of data protocol analysis, etc. in the testing and aging process of the chip of the high-bandwidth ethernet controller, based on the idea of the built-in self-test technology, effectively accelerate the progress of the chip in the testing and aging stage, improve the testing efficiency, reduce the testing cost, and keep the compatibility of chip pin definitions without occupying additional chip pins.
The invention adopts the following technical scheme:
a built-in self-test method facing to a transceiving path of an Ethernet controller comprises the following steps:
s1, analyzing the test mode according to the test mode selection method, and judging whether the configuration of the test mode conforms to the regulation of the test mode selection method; if the configuration is correct, go to step S2; otherwise, the test is quitted, and the whole test is finished;
s2, switching a data receiving and transmitting path facing to the interface end of the processor, so that the data receiving and transmitting path is respectively connected with a self-testing unit in the chip;
s3, configuring the test environment according to the test mode obtained in the step S1, including the loopback depth, the work rate of the MAC and the PHY, and the duplex mode of the MAC and the PHY;
s4, generating a test data frame according to the test mode obtained in the step S1, sending the test data frame through a sending path, and starting a timer after the sending is finished;
s5, judging whether the self-test unit receives the data frame before the timer is overtime; if the data frame is received, step S6; otherwise, analyzing and positioning the fault existing in the test;
s6, caching the received data frame, and extracting the length, source address, destination address, VLAN ID and frame type of the data frame;
s7, comparing the received data frame with the data frame sent out in the step S4, and if the received data frame and the data frame are consistent, entering the step S8; otherwise, analyzing and positioning the fault existing in the test;
s8, recording and counting the test result and the test times, and then outputting the test result according to the specification of the test result feedback method;
s9, judging whether the test reaches the set test times according to the test mode obtained in the step S1; if the times are reached, the test is finished; otherwise, return to step S4 to continue the start of the test.
Specifically, in step S1, the test mode selection method uses IO pin multiplexing, and first determines reset, and if reset is invalid, the method ends, and if reset is valid, the designated output pin is switched to the input pin, and the input signal is sampled, and the corresponding test mode is analyzed and recorded.
Furthermore, the test parameters comprise loop depth, test rate, duplex mode, test times, data frame length and data frame type, and the input values of the pins are sampled and stored during the reset period, so that the recording of various parameters is realized, and the selection of the test mode is completed.
Specifically, in step S3, the loop depth is where the data arrives at the receiving path from the transmitting path in the controller; the system comprises an MDI layer loop, a TBI layer loop, a PCS layer loop in a PHY, a GMII layer loop and a buffer area loop in an MAC; the operating rates of the MAC and PHY are the rates that the link needs to achieve in the test; the duplex mode of the MAC and PHY is tested in either full duplex or half duplex mode.
Specifically, in step S8, the test result feedback method uses IO pin multiplexing, switches the driving source of the designated output pin during the test, and outputs the test result through the output pin, where the information output by the test result includes: the total test times, the test success times, the test failure times and the fault positioning analysis results, wherein the test failure times comprise test overtime times and data frame receiving and sending inconsistent times.
Specifically, in the test, when the timer is overtime or the received data frame is inconsistent with the transmitted data frame, the reason causing the test failure is automatically analyzed and positioned according to the description of the fault analysis positioning method, and finally, a corresponding analysis result is returned, and the test is ended.
Further, the fault analysis positioning method specifically comprises the following steps: firstly, determining whether the loop depth is minimum, if so, generating a fault analysis positioning result, outputting the fault analysis positioning result, and ending; if the loop returning depth is not the minimum, reducing the loop returning depth to the previous level by adopting a downshifting mode, and reconfiguring the test environment; and according to the on-chip loop testing method, carrying out data transceiving test again, if the test is unsuccessful, returning to judge the loop depth again, if the test is successful, generating a fault analysis positioning result and outputting the fault analysis positioning result, and ending.
The built-in self-test system comprises a test main control module, wherein the test main control module can control the whole test process and the test link, the test main control module is connected with an IO pin of a chip through a pin control module, and the pin control module is used for realizing capture of a test mode, output of a test result and switching of a data transceiving path; the test main control module is connected with the data sending path through the excitation generating module, the excitation generating module completes the generation of the test data frame and transmits the test data frame to the data sending path according to the interface time sequence to realize the sending of the data frame; the test main control module is connected with the control state register module through the controller configuration module, and the controller configuration module is used for configuring the internal register of the chip; the test main control module is connected with the fault positioning module through the response analysis module, the response analysis module is connected with the data receiving path, the received data frames are cached, analyzed and compared, whether the data frames are consistent with the data frames generated by the excitation generation module or not is judged, then the data frames are fed back to the test main control module, the fault positioning module performs step-by-step test on the loop back path in an automatic downshift mode, analyzes and positions the loop back path with faults according to the test result, and sends the loop back to the test main control module.
Specifically, the test main control module configures a corresponding register in the chip through the controller configuration module according to the test mode obtained by the pin configuration module to construct a test environment; after the test environment is established, controlling an excitation generation module to generate a corresponding test data frame; continuously monitoring the state of the control response analysis module, and storing and analyzing the test result fed back by the control response analysis module; and under the condition that the test has faults, the test main control module starts a fault positioning module to analyze and position the faults existing in the test.
Specifically, the configuration information of the controller configuration module includes an MAC loopback level, a PHY loopback level, a work rate of an MAC, an MAC duplex mode, an MAC receiving and filtering mode, a PHY work rate, and a PHY duplex mode, and in the configuration process, an original value of a register is recorded first, and then configuration is performed; during resetting, the pin control module drives the IO bidirectional pin as input, and adopts and analyzes the input value; after entering the test mode, the pin control module drives the IO bidirectional pin to be output and switches the output driving source to the test main control module; and after entering the test mode, the pin control module cuts off the connection between the processor interface and the data receiving and transmitting path, and connects the data receiving and transmitting path with the response analysis module and the excitation generation module respectively.
Compared with the prior art, the invention has at least the following beneficial effects:
the built-in self-test method for the receiving and transmitting path of the Ethernet controller effectively solves the problems of complex high-speed interface excitation and complex data and protocol analysis of the chip of the Ethernet controller in a data receiving and transmitting test, and realizes the self-test and self-diagnosis of the chip of the Ethernet controller on the aspect of a data receiving and transmitting function, thereby accelerating the progress of the chip in the finished test and the aging stage, improving the test efficiency of the chip, and reducing the complexity and the cost of the chip test aging.
Furthermore, the test mode selection method and the test result feedback method can enable the chip to rapidly and accurately enter a self-test mode by multiplexing the IO pin in the reset period and the test period respectively, and output the test result intuitively and actively, thereby reducing the design complexity of a peripheral test environment and simultaneously keeping the compatibility with the original IO pin of the chip.
Furthermore, according to the test mode determined by the test mode selection method, a flexible test mode is provided, and the test mode can be freely configured in the aspects of test depth, test rate, duplex and frame length, so that the requirements of various test applications are met.
A built-in self-test system facing a receiving and transmitting path of an Ethernet controller gradually reduces the loop-back depth of a test by adopting an automatic downshift mode when the test is unsuccessful, and simultaneously automatically analyzes a data path with a fault, finally judges the approximate position of the fault and helps a user to locate the problem more quickly.
In conclusion, the invention improves the testing efficiency, reduces the testing cost, does not occupy additional chip pins and keeps the compatibility of the chip pin definition.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
FIG. 1 is a flowchart of an on-chip loopback test method of the present invention;
FIG. 2 is a flow chart of a test mode selection method of the present invention;
FIG. 3 is a flow chart of a fault analysis positioning method of the present invention;
fig. 4 is a block diagram showing the general structure of the hardware circuit of the present invention.
Detailed Description
The invention provides a built-in self-test method facing a transceiving path of an Ethernet controller, which adopts the concept of loop-back in a chip to construct a path for data to wrap back from a transmitting path to a receiving path; generating test excitation in the controller and comparing and analyzing the result to judge whether the core function and the transceiving channel of the controller operate normally or not and automatically position when a fault occurs; meanwhile, a pin multiplexing mode is adopted, and flexible configuration and output of a test mode and a test result are realized.
Referring to fig. 1, a built-in self-test method for a transceiver path of an ethernet controller according to the present invention includes the following steps:
s1, analyzing the test mode according to the test mode selection method, and judging whether the configuration of the test mode accords with the regulation of the test mode selection method, namely whether the configuration is correct; if the configuration is correct, the operation of step S2 is performed; otherwise, the test is quitted, and the whole test is finished;
referring to fig. 2, the test mode selection method adopts the concept of IO pin multiplexing, and samples the pin input signal during the power-on reset period of the chip, thereby implementing the selection of the test mode.
In particular, for ethernet controllers, the LED pins are used only as output pins during normal operation and are relatively independent in function, so the method provides for the configuration of the test mode to be performed using these output pins as input pins during reset. It should be noted that the LED pins are only used as examples, but not limited to the LED pins.
During the power-on reset, the pins are pulled up or pulled down to realize the input of necessary information required in the test, and the test parameters comprise:
loop back depth, test rate, duplex mode, test times, data frame length, data frame type. And during resetting, the input values of the pins are sampled and stored, so that various parameters are recorded, and the selection of a test mode is completed.
The test mode selection method provided by the invention not only can provide flexible, simple and rapid mode configuration, but also can keep compatibility with the original IO pin of the chip.
S2, switching a data receiving and transmitting path facing to the interface end of the processor, so that the receiving and transmitting of data do not point to the processor end any more, but are connected with a self-testing unit in the chip;
the operation mainly realizes the isolation of the data receiving and transmitting path and the processing interface in the controller, and ensures that the operations of excitation injection, result analysis and the like in the test process are all completed by the self-test unit.
S3, according to the test mode obtained in the step S1, correspondingly configuring the test environment, specifically including loop depth, work rates of MAC and PHY, and duplex mode of MAC and PHY;
the loop back depth refers to where data arrives from the transmit path to the receive path in the controller. The loop depth comprises MDI layer loop, TBI layer loop, PCS layer loop in PHY, GMII layer loop and buffer zone loop in MAC. The operating rate of the MAC and PHY means the rate at which the link needs to be reached during testing, and the duplex mode of the MAC and PHY means that the testing is performed in full duplex or half duplex mode.
S4, generating a corresponding test data frame according to the test mode obtained in the step S1, sending the data frame by a sending path, and starting a timer immediately after the sending is finished;
the timer mainly aims to ensure that the test can enter a fault analysis positioning stage under the condition that a data frame is not received for a long time, and the situation of waiting for death is avoided. Meanwhile, the timing time of the timer needs to be longer than the maximum data transceiving loop time.
S5, judging whether the self-test unit receives the data frame before the timer is overtime; if the data frame is received, performing the next operation according to step S6; otherwise, step S10 is entered, and the fault existing in the test is analyzed and positioned;
s6, caching the received data frame, and extracting the length, source address, destination address, VLAN ID and frame type of the data frame;
s7, comparing the received data frame with the data frame sent in the step S4, and judging whether the received data frame and the data frame are consistent; if yes, go to step S8; otherwise, step S10 is entered, and the fault existing in the test is analyzed and positioned;
s8, recording and counting the test result and the test times, and then outputting the test result according to the specification of the test result feedback method;
the test result feedback method adopts the IO pin multiplexing idea, and switches the drive source of the appointed output pins in the test process, so that the test result is output through the output pins.
Taking the LED pin as an example, during normal operation, the LED pin is an output pin and only outputs the status information of the controller. And after entering the test mode, the LED pins do not output the state information of the controller any more, but serve as output pins of the test result, and the test result is output. It should be noted that the LED pins are only used as examples, but not limited to the LED pins.
The information output by the test result comprises: the total test times, the test success times, the test failure times and the fault positioning analysis results. The times of test failure comprise the times of test overtime and the times of inconsistency of the data frame receiving and sending.
Therefore, in combination with the test mode selection method and the test result feedback method, these multiplexed IO pins have three states, which are the output state in the normal mode, the test mode selection input state during the reset period, and the test result output state in the test mode.
S9, judging whether the test reaches the set test times according to the test mode obtained in the step S1; if the times are reached, the test is finished; otherwise, returning to the step S4 to continue the test;
and S10, when the timer is overtime or the received data frame is inconsistent with the transmitted data frame in the test, automatically analyzing and positioning the reason causing the test failure according to the description of the fault analysis positioning method, finally returning the corresponding analysis result, and ending the test.
A variety of different loop back depths are provided in the test mode of the method of the present invention. From bottom to top, the OSI reference model can be divided into MDI layer loopback, TBI layer loopback, PCS layer loopback, GMII layer loopback and buffer zone loopback. Among them, the MDI layer loop is closest to the real data transceiving because the loop path covers substantially the whole transceiving path, so the loop depth is large. And the buffer area loop is closest to the self-test unit, and data is not processed by the MAC and the PHY, so that the transceiving path is shortest and the loop depth is smaller. Thus, the loop back path closer to the physical interface is specified herein to have a deeper loop back depth.
The fault analysis positioning method judges and positions a data path with a fault in an automatic downshift mode based on different loop return depths, and the whole operation flow is shown in fig. 3.
The automatic downshift means that in the test process, if the test fails in the current configuration mode all the time, the self-test unit automatically downshifts the test mode, that is, the loop-back depth is reduced, the path is shortened, the test is performed again, and so on until the test depth is reduced to the minimum.
In this manner, the self-test unit can automatically determine the approximate location of the fault, thereby helping the user locate the problem more quickly. For example, in the case that the MDI layer loop is not successful, the failure analysis positioning method is started, and the automatic downshift process is performed and then the test is performed until the GMII layer loop is successfully tested, which may indicate that data is normally received and transmitted in the MAC and is not normally received and transmitted in the PHY layer, so that a failure exists in the PHY.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 4, a hardware circuit corresponding to the built-in self-test method for the ethernet controller transceiver path according to the present invention includes a test main control module 1, a stimulus generation module 2, a response analysis module 3, a fault location module 4, a controller configuration module 5, and a pin control module 6.
The test main control module 1 controls the whole test flow and test links, and the number of the test main control module is 1.
The test main control module 1 configures corresponding registers in the chip through the controller configuration module according to the test mode obtained by the pin configuration module, so as to construct a test environment; after the test environment is established, controlling an excitation generation module to generate a corresponding test data frame; continuously monitoring the state of the control response analysis module, and storing and analyzing the test result fed back by the control response analysis module; and under the condition that the test has faults, the test main control module starts a fault positioning module to analyze and position the faults existing in the test.
The excitation generating module 2 completes the generation of the test data frame according to the control of the test main control module, and transmits the test data frame to the data transmitting path according to the corresponding interface time sequence, thereby realizing the transmission of the data frame, and the number of the data frame is 1.
Under different configurations of the test main control module, the module can generate data frames with different lengths and different types. However, no matter what kind of data frame is generated, the module needs to ensure that the data frame is correct and correct, and meets the requirement of the ethernet protocol.
The response analysis module 3 has the main functions of caching, analyzing and comparing the received data frames, judging whether the data frames are consistent with the data frames generated by the excitation generation module, and feeding back the data frames to the test main control module, wherein the number of the data frames is 1.
When the receiving timer is overtime or the received and transmitted data frames are inconsistent, the module informs the current state of the module to the fault positioning module and triggers the fault positioning module to analyze faults existing in the test.
The fault location module 4 mainly functions to test the loop paths step by step in an automatic downshift manner, and analyze and locate the loop paths with faults according to the test result, wherein the number of the loop paths is 1.
The working process is as follows: firstly, recording the current fault state, then analyzing the current test environment, and judging whether the downshift processing can be carried out: if yes, informing the test main control module to reconfigure a new test environment and starting testing; and if not, generating a fault positioning result. After the test is restarted, if the test is successful, recording the state and generating a fault positioning result; and if the test fails, returning to repeat iteration again.
The controller configuration module 5 has a main function of correspondingly configuring the internal registers of the chip according to the control of the test main control module, and the number of the internal registers is 1.
The configured information includes MAC loopback level, PHY loopback level, MAC working rate, MAC duplex mode, MAC receive filter mode, PHY working rate, PHY duplex mode, and the like. During the configuration process, the module records the original value of the register first and then performs the configuration. The purpose of this is that after exiting self-test mode, the module can restore the register to its original value, thus ensuring that the chip can work properly after exiting self-test mode.
The pin control module 6 mainly functions to switch the designated IO bidirectional pin and the processor interface according to the reset state of the chip and the control of the test main control module, so as to capture the test mode, output the test result, and switch the data transceiving paths, and the number of the pins is 1.
During the reset period, the pin control module 6 drives the IO bidirectional pin as input, and adopts and analyzes the input value; after entering the test mode, the pin control module 6 drives the IO bidirectional pin to output, and switches the driving source output by the IO bidirectional pin to the test main control module; in addition, after entering the test mode, the pin control module 6 disconnects the processor interface from the data transmission/reception path, and connects the data transmission/reception path to the response analysis module and the excitation generation module, respectively.
Referring to fig. 4, the internal structure of the dotted line is the circuit structure of the self-test method proposed by the present invention, and the external part of the dotted line is other interfaces or modules in the ethernet controller connected to the dotted line, wherein the control status register module mainly stores the configuration and status information of the entire controller; the data receiving path is an interface of a data receiving path in the controller at the processor end, and the data sending path is an interface of a data sending path in the controller at the processor end; the IO pin of the chip is an interface of the IO pin PAD in the controller chip.
The invention can be used in high bandwidth network and bus type controller chips, and is especially suitable for chips with limitation on controller pin number and hardware resources, complex interface protocol and high requirement on electrical characteristics.
In a specific embodiment, the self-developed gigabit ethernet controller LC9000 is selected as an object, and the hardware circuit of the present invention is integrated with the object to perform system-level and chip-level verification. The LC9000 is an autonomously developed ethernet controller with high bandwidth and high integration density, supports three rates of 1000M, 100M and 10M, and provides two physical layer interfaces of GPHY and SerDes. In addition, the LC9000 also supports an EEPROM interface and an asynchronous processor interface, and realizes flexible program self-loading and self-configuration processes, thereby simplifying the control of the processor on data receiving and transmitting.
The verification result shows that the invention realizes the design function, can correctly complete the test of the transceiver channel of the controller, and the test performance meets the expectation, thereby effectively reducing the complexity and the cost of chip test and aging.
The invention can ensure the functional correctness by performing functional simulation, and can perform experiments in the FPGA environment. In an experimental environment, the hardware overhead is first analyzed. ISE 13.2 is adopted to synthesize the invention, and 2803 SLICE LUTs are used in the aspect of hardware logic utilization rate; in the aspect of storage resources, data is not cached, so that the storage resources are not occupied; in other hardware aspects, such as IO pins and the like, no extra pins of the chip are occupied. The invention does not occupy excessive hardware resources, and keeps good compatibility with the controller chip in the aspects of IO pins, storage resources and the like.
The time consumption of the present invention during the test was analyzed. In the experiment, the test is carried out at the speed of 1000M, 100M and 10M respectively, and different loop depths and different frame lengths are set respectively. And each group of tests totally carry out 10000 times of data loop receiving and sending, and carry out statistics on each group of test time through the chipscope.
The experimental result shows that the difference of the test time of different loop depths can be ignored, and the maximum time consumed for completing a group of tests by the method is 1.49 seconds, so that the set expectation is reached, and the test requirements are met.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (10)
1. A built-in self-test method facing a transceiving path of an Ethernet controller is characterized by comprising the following steps:
s1, analyzing the test mode according to the test mode selection method, and judging whether the configuration of the test mode conforms to the regulation of the test mode selection method; if the configuration is correct, go to step S2; otherwise, the test is quitted, and the whole test is finished;
s2, switching a data receiving and transmitting path facing to the interface end of the processor, so that the data receiving and transmitting path is respectively connected with a self-testing unit in the chip;
s3, configuring the test environment according to the test mode obtained in the step S1, including the loopback depth, the work rate of the MAC and the PHY, and the duplex mode of the MAC and the PHY;
s4, generating a test data frame according to the test mode obtained in the step S1, sending the test data frame through a sending path, and starting a timer after the sending is finished;
s5, judging whether the self-test unit receives the data frame before the timer is overtime; if the data frame is received, step S6; otherwise, analyzing and positioning the fault existing in the test;
s6, caching the received data frame, and extracting the length, source address, destination address, VLAN ID and frame type of the data frame;
s7, comparing the received data frame with the data frame sent out in the step S4, and if the received data frame and the data frame are consistent, entering the step S8; otherwise, analyzing and positioning the fault existing in the test;
s8, recording and counting the test result and the test times, and then outputting the test result according to the specification of the test result feedback method;
s9, judging whether the test reaches the set test times according to the test mode obtained in the step S1; if the times are reached, the test is finished; otherwise, return to step S4 to continue the start of the test.
2. The Ethernet controller transceiver-oriented built-in self-test method according to claim 1, wherein in step S1, the test mode selection method employs IO pin multiplexing, and first determines reset, if reset is invalid, then ends, and if reset is valid, switches the designated output pin to the input pin, samples the input signal, and parses and records the corresponding test mode.
3. The Ethernet controller transceiver-oriented built-in self-test method as recited in claim 2, wherein the test parameters include loop depth, test rate, duplex mode, test times, data frame length, and data frame type, and the input values of the pins are sampled and stored during reset to record the parameters and complete the selection of the test mode.
4. The Ethernet controller transceiver path-oriented built-in self-test method of claim 1, wherein in step S3, the loop-back depth is where in the controller the data is to arrive at the receiving path from the transmitting path; the system comprises an MDI layer loop, a TBI layer loop, a PCS layer loop in a PHY, a GMII layer loop and a buffer area loop in an MAC; the operating rates of the MAC and PHY are the rates that the link needs to achieve in the test; the duplex mode of the MAC and PHY is tested in either full duplex or half duplex mode.
5. The ethernet controller transceiver path-oriented built-in self-test method according to claim 1, wherein in step S8, the test result feedback method uses IO pin multiplexing, switches a driving source of a designated output pin during the test, and outputs the test result through the output pin, and the information output by the test result includes: the total test times, the test success times, the test failure times and the fault positioning analysis results, wherein the test failure times comprise test overtime times and data frame receiving and sending inconsistent times.
6. The Ethernet controller transceiver path-oriented built-in self-test method as claimed in claim 1, wherein, during the test, when the timer is overtime or the received data frame is inconsistent with the transmitted data frame, the cause of the test failure is automatically analyzed and located according to the description of the failure analysis locating method, and finally the corresponding analysis result is returned, and the test is ended.
7. The Ethernet controller transceiver path-oriented built-in self-test method of claim 6, wherein the fault analysis positioning method specifically comprises: firstly, determining whether the loop depth is minimum, if so, generating a fault analysis positioning result, outputting the fault analysis positioning result, and ending; if the loop returning depth is not the minimum, reducing the loop returning depth to the previous level by adopting a downshifting mode, and reconfiguring the test environment; and according to the on-chip loop testing method, carrying out data transceiving test again, if the test is unsuccessful, returning to judge the loop depth again, if the test is successful, generating a fault analysis positioning result and outputting the fault analysis positioning result, and ending.
8. A built-in self-test system facing to a receiving and sending channel of an Ethernet controller is characterized in that the built-in self-test method facing to the receiving and sending channel of the Ethernet controller comprises a test main control module, wherein the test main control module can control the whole test process and a test link, the test main control module is connected with an IO pin of a chip through a pin control module, and the pin control module is used for realizing capture of a test mode, output of a test result and switching of a data receiving and sending path; the test main control module is connected with the data sending path through the excitation generating module, the excitation generating module completes the generation of the test data frame and transmits the test data frame to the data sending path according to the interface time sequence to realize the sending of the data frame; the test main control module is connected with the control state register module through the controller configuration module, and the controller configuration module is used for configuring the internal register of the chip; the test main control module is connected with the fault positioning module through the response analysis module, the response analysis module is connected with the data receiving path, the received data frames are cached, analyzed and compared, whether the data frames are consistent with the data frames generated by the excitation generation module or not is judged, then the data frames are fed back to the test main control module, the fault positioning module performs step-by-step test on the loop back path in an automatic downshift mode, analyzes and positions the loop back path with faults according to the test result, and sends the loop back to the test main control module.
9. The Ethernet controller transceiver-oriented built-in self-test system of claim 8, wherein the test main control module configures the corresponding register inside the chip through the controller configuration module according to the test mode obtained by the pin configuration module to construct a test environment; after the test environment is established, controlling an excitation generation module to generate a corresponding test data frame; continuously monitoring the state of the control response analysis module, and storing and analyzing the test result fed back by the control response analysis module; and under the condition that the test has faults, the test main control module starts a fault positioning module to analyze and position the faults existing in the test.
10. The Ethernet controller transceiver path-oriented built-in self-test system of claim 8, wherein the configuration information of the controller configuration module comprises a MAC loopback level, a PHY loopback level, a MAC working rate, a MAC duplex mode, a MAC reception filtering mode, a PHY working rate and a PHY duplex mode, and in the configuration process, the original value of the register is recorded first and then configured; during resetting, the pin control module drives the IO bidirectional pin as input, and adopts and analyzes the input value; after entering the test mode, the pin control module drives the IO bidirectional pin to be output and switches the output driving source to the test main control module; and after entering the test mode, the pin control module cuts off the connection between the processor interface and the data receiving and transmitting path, and connects the data receiving and transmitting path with the response analysis module and the excitation generation module respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010033571.0A CN111221694B (en) | 2020-01-13 | 2020-01-13 | Built-in self-test method and system for receiving and transmitting path of Ethernet controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010033571.0A CN111221694B (en) | 2020-01-13 | 2020-01-13 | Built-in self-test method and system for receiving and transmitting path of Ethernet controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111221694A true CN111221694A (en) | 2020-06-02 |
| CN111221694B CN111221694B (en) | 2023-02-24 |
Family
ID=70808357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010033571.0A Active CN111221694B (en) | 2020-01-13 | 2020-01-13 | Built-in self-test method and system for receiving and transmitting path of Ethernet controller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111221694B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110224887A (en) * | 2019-06-04 | 2019-09-10 | 北京挚友科技有限公司 | A kind of method and apparatus of Ethernet Y.1564 test frame automatic identification |
| CN114076889A (en) * | 2021-11-18 | 2022-02-22 | 长江存储科技有限责任公司 | Test system and test method |
| CN115242681A (en) * | 2022-09-20 | 2022-10-25 | 苏州浪潮智能科技有限公司 | System, method and equipment for testing communication module in chip and storage medium |
| CN116047390A (en) * | 2022-12-30 | 2023-05-02 | 北京航天测控技术有限公司 | Self-checking method, device, equipment and storage medium for signal testing system |
| CN116192706A (en) * | 2022-12-20 | 2023-05-30 | 珠海妙存科技有限公司 | UFS-based self-detection and self-resetting method and system |
| CN116306409A (en) * | 2023-05-22 | 2023-06-23 | 南京芯驰半导体科技有限公司 | Chip verification method, device, equipment and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030214979A1 (en) * | 2002-05-18 | 2003-11-20 | Kang Sung-Soo | Method and apparatus for multiplexing and demultiplexing variable-length packets |
| CN104730356A (en) * | 2013-12-18 | 2015-06-24 | 北京同方微电子有限公司 | Self-testing device supporting full card radio-frequency test and using method thereof |
| CN109165116A (en) * | 2018-08-15 | 2019-01-08 | 西安微电子技术研究所 | A kind of application Processing Interface circuit and method |
-
2020
- 2020-01-13 CN CN202010033571.0A patent/CN111221694B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030214979A1 (en) * | 2002-05-18 | 2003-11-20 | Kang Sung-Soo | Method and apparatus for multiplexing and demultiplexing variable-length packets |
| CN104730356A (en) * | 2013-12-18 | 2015-06-24 | 北京同方微电子有限公司 | Self-testing device supporting full card radio-frequency test and using method thereof |
| CN109165116A (en) * | 2018-08-15 | 2019-01-08 | 西安微电子技术研究所 | A kind of application Processing Interface circuit and method |
Non-Patent Citations (2)
| Title |
|---|
| 张保栋: "令牌环（TokenRing）", 《通信世界》 * |
| 胡湘娟等: "基于FPGA的内建自测试的实现研究", 《计算机测量与控制》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110224887A (en) * | 2019-06-04 | 2019-09-10 | 北京挚友科技有限公司 | A kind of method and apparatus of Ethernet Y.1564 test frame automatic identification |
| CN114076889A (en) * | 2021-11-18 | 2022-02-22 | 长江存储科技有限责任公司 | Test system and test method |
| CN115242681A (en) * | 2022-09-20 | 2022-10-25 | 苏州浪潮智能科技有限公司 | System, method and equipment for testing communication module in chip and storage medium |
| CN116192706A (en) * | 2022-12-20 | 2023-05-30 | 珠海妙存科技有限公司 | UFS-based self-detection and self-resetting method and system |
| CN116192706B (en) * | 2022-12-20 | 2024-01-26 | 珠海妙存科技有限公司 | UFS-based self-detection and self-resetting method and system |
| CN116047390A (en) * | 2022-12-30 | 2023-05-02 | 北京航天测控技术有限公司 | Self-checking method, device, equipment and storage medium for signal testing system |
| CN116306409A (en) * | 2023-05-22 | 2023-06-23 | 南京芯驰半导体科技有限公司 | Chip verification method, device, equipment and storage medium |
| CN116306409B (en) * | 2023-05-22 | 2023-08-08 | 南京芯驰半导体科技有限公司 | Chip verification method, device, equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111221694B (en) | 2023-02-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111221694B (en) | Built-in self-test method and system for receiving and transmitting path of Ethernet controller | |
| US7650555B2 (en) | Method and apparatus for characterizing components of a device under test using on-chip trace logic analyzer | |
| US8019832B2 (en) | Network core access architecture | |
| EP2605454B1 (en) | Network impairment unit with bandwidth-constrained packet duplication | |
| US7936685B2 (en) | Intelligent fast switch-over network tap system and methods | |
| CN111522700B (en) | Self-testing platform for testing serial RapidIO network switching module | |
| US20110182191A1 (en) | Testing Network Equipment | |
| US20060176943A1 (en) | Serializer deserializer (SERDES) testing | |
| TWI666884B (en) | Method for testing data packet signal transceivers using interleaved device setup and testing | |
| CN110808908B (en) | System and method for switching redundant network in real time across platforms | |
| US8719481B2 (en) | Method and arrangement for streaming data profiling | |
| CN116203400B (en) | Test method and system based on chip initialization | |
| CN100388692C (en) | Multi-mouth switching device and testing method for network exchanger | |
| CN112118144B (en) | Ethernet data frame output method and system | |
| CN106027292A (en) | Device used for configuration and testing of FlexRay network | |
| Concatto et al. | Improving yield of torus NoCs through fault-diagnosis-and-repair of interconnect faults | |
| US8000322B2 (en) | Crossbar switch debugging | |
| CN105553859A (en) | System and method for enabling SFP modules to be adaptive to interfaces | |
| US20070254665A1 (en) | Wireless Switches with JTAG Emulators | |
| CN110365530A (en) | A kind of test token passing network independently of network-on-chip | |
| CN101582011B (en) | Serializer/deserializer (Serdes) interface data acquisition method and device | |
| US20030217324A1 (en) | System and method for communicating between a number of elements and a method for configuring and testing the system | |
| WO2008110198A1 (en) | Hardware interface board for connecting an emulator to a network | |
| CN220693149U (en) | Intelligent clock system and FTTR BOB test equipment | |
| CN116825170B (en) | Automatic calibration architecture and chip for die-to-die interconnect |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |