CN111522700B - Self-testing platform for testing serial RapidIO network switching module - Google Patents
Self-testing platform for testing serial RapidIO network switching module Download PDFInfo
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- CN111522700B CN111522700B CN202010330336.XA CN202010330336A CN111522700B CN 111522700 B CN111522700 B CN 111522700B CN 202010330336 A CN202010330336 A CN 202010330336A CN 111522700 B CN111522700 B CN 111522700B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a self-testing platform for testing a serial RapidIO network switching module, which comprises bottom plate hardware and testing software, wherein the bottom plate hardware comprises a plurality of paths of port pins, 2 FPGA chips and 2 debugging serial ports; the port pins are used for guiding each outgoing port on the switching module to the bottom plate, and an external self-loop-back mode is adopted to enable any two port pins to form a self-loop-back relation; the debugging serial port is used for outputting a test request to the FPGA chip; one SRIO interface led out from the 2 FPGA chips is connected with any port pin in an external jumper mode according to test requirements, the same test software resides in the two FPGAs, and the test software comprises a driver of the switch, a RapidIO controller and a function test unit and is used for completing various test items. The method is suitable for testing the functions and the performances of various customized serial RapidIO network switching modules under the condition of not depending on a system testing environment.
Description
Technical Field
The invention belongs to the field of embedded system interconnection high-speed communication, and particularly relates to a self-testing platform for testing the function and performance of a serial RapidIO network switching module of a modern high-performance embedded system.
Background
At present, with the great revolution of I/O interconnection technology and system structure, the emerging interconnection technology is continuously emerging. The RapidIO interconnection architecture serves as an open standard and meets the wide application requirements of embedded infrastructure. RapidIO technology mostly adopts a Switch-based interconnection topology, and RapidIO end point devices are not directly interconnected but are interconnected through a RapidIO Switch. Communication links of a plurality of RapidIO end devices in the system are organized together through RapidIO switches, random interconnection and concurrent transmission of the RapidIO system can be achieved, and system bandwidth is increased in multiples.
With the increase of the number of RapidIO end equipment in the system, the number of required RapidIO switches is increased at the same time. In this application context, multiple RapidIO switches are often integrated into one or more dedicated RapidIO network switching modules.
The RapidIO network switching module is required to meet the requirement of high-speed real-time transmission of a large amount of data while meeting the requirement of free interconnection of RapidIO end equipment with different architectures and quantities. This puts higher requirements on the design of the RapidIO network switch module, and therefore how to verify the performance of the RapidIO network switch module becomes a hotspot of research in the industry.
In the past, the verification of the RapidIO network switching module depends on a system joint test environment and is tested by means of a respective terminal node module. The mode has great limitation to RapidIO network switching module design manufacturers, and the factory self-test of products is restricted by the integrated joint test condition.
Disclosure of Invention
Aiming at the problems, the invention provides a self-testing platform for testing the serial RapidIO network switching module, which is suitable for testing the functions and the performances of various customized serial RapidIO network switching modules under the condition of not depending on a system testing environment.
A self-test platform for testing a serial RapidIO network switching module comprises bottom plate hardware and test software, wherein the bottom plate hardware comprises a plurality of paths of port pins, 2 FPGA chips and 2 debugging serial ports;
the port pins are used for leading each outgoing port on the serial RapidIO network switching module to the bottom plate, and an external self-loop-back mode is adopted to enable any two port pins to form a self-loop-back relation through a jumper wire according to test requirements;
the debugging serial port is used for outputting a test request to the FPGA chip and receiving a test result fed back by the FPGA chip;
one SRIO interface led out from 2 FPGA chips is connected with any port pin in an external jumper wire mode according to test requirements so as to be connected with any outgoing port of the serial RapidIO network switching module, the same test software resides in the two FPGAs, and the test software comprises a driver of a switch, a RapidIO controller and a function test unit;
the switch driver is used for accessing a register of the serial RapidIO network switching module through the IIC interface to identify each outgoing port of the tested serial RapidIO network switching module and automatically searching a network topology structure, so that a self-loop transmission path of the same FPGA chip and a point-to-point transmission path between two FPGA chips are configured;
the RapidIO controller is used for realizing RapidIO communication and is provided with RapidIO packets for transmitting five transaction types of NWRITE, SWRITE, NREAD, doorbell and Message;
the function test unit designs corresponding test items according to different function requirements.
The invention has the beneficial effects that:
1. since the conventional embedded high-speed serial communication bus product test depends on a specific system integration environment, the single module design progress is limited by the integrated system environment progress. The invention provides a single module test solution, which can effectively improve the development progress of products.
2. The communication performance test of the traditional embedded high-speed serial communication bus product also depends on a specific system integration environment, and the performance test is completed by other modules in the system. The invention ensures the basic function of the test and provides a single module performance test method, so that the performance of the product can be tested conveniently and flexibly.
3. The embedded high-speed serial communication bus product has high requirements on signal quality, and the measurement of the signal quality is often caused by the interconnection of two modules, so that the essential reasons cannot be distinguished. The self-testing platform provided by the invention can isolate the influence of other modules, analyze the quality of high-speed signals of the module and facilitate the timely isolation of problems.
Drawings
Fig. 1 is a schematic structural diagram of a serial RapidIO network switching module shown in the embodiment.
Fig. 2 is a schematic diagram of a backplane hardware structure of a self-test platform for testing a serial RapidIO network switch module according to an embodiment.
Fig. 3 is a schematic diagram of a testing software framework of a self-testing platform for testing a serial RapidIO network switching module according to an embodiment.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
The self-testing platform for testing the serial RapidIO network switching module in this embodiment tests the port connection state of the serial RapidIO network switching module, and performs the functions of switching transmission delay, end-to-end transmission bandwidth, port transmission error rate, and automatic signal quality optimization without a system integration joint test environment or other terminal node modules. The embodiment can improve the product yield of a factory to a great extent, and simultaneously provides a means for isolating faults of other RapidIO terminal node modules in the system to serve the joint test of the whole system.
The self-test platform for testing the serial RapidIO network switching module comprises a backplane hardware and a test software. The hardware of the bottom plate is shown in fig. 2, and comprises 20 paths of 4X port pins, 2 pieces of XC7a200T FPGA chips, and 2 debugging serial ports.
The port pins are used for leading each outgoing port on the serial RapidIO network switching module to the bottom plate, and an external self-loop-back mode is adopted, so that a self-loop-back relation is formed between any two port pins through a jumper wire according to test requirements.
The debugging serial port is used for outputting a corresponding test request to the FPGA chip and receiving a test result fed back by the FPGA chip.
Two xilinx company FPGA chips XC7A200T are respectively led out with a 4X SRIO interface, and can be connected with any port pin (in the figure, the default FPGA1 is connected with the pin 1, and the FPGA2 is connected with the pin 20) in an external jumper mode according to the test requirement, so that the two xlinx company FPGA chips are connected with any outgoing port of the serial RapidIO network switching module. One of the two FPGA chips is used as a main test node FPGA, the other one is used as a slave test node FPGA, and the same test software resides in the two FPGAs.
The test software is shown in fig. 3, and comprises FPGA bottom logic and Microblaze soft core software. The FPGA bottom layer logic provides a basic hardware platform, and Microblaze soft core software mainly comprises a driver of a switch, a 1-path RapidIO controller and a function test unit.
And the switch driver is used for accessing the register of the serial RapidIO network switching module through the IIC interface to identify each outgoing port of the tested serial RapidIO network switching module and automatically searching a network topology structure, so that a self-loop transmission path of the same FPGA chip and a point-to-point transmission path between two FPGA chips are configured.
The RapidIO controller is used for realizing RapidIO communication and is provided with basic logic layer transaction packets for transmitting NWRITE, SWRITE, NREAD, doorbell, message and the like.
The function test unit designs corresponding test items according to different function requirements, and comprises a port connection state test unit, a transmission delay test unit, a transmission bandwidth test unit, an error rate test unit, a port signal quality automatic optimization unit and the like.
Port connection state test unit: and calling a switch driver to access a register on the tested serial RapidIO network switching module after receiving the connection test instruction so as to obtain the link state of each outgoing Port, evaluating the outgoing Port of the RapidIO network switching module, and if the link state of the corresponding Port is Port OK after passing through a self-loop, proving that the Port is normal.
A transmission delay test unit: and after receiving the transmission delay test command, calling the RapidIO controller to send a RapidIO packet with the transaction type of Doorbell to the tested serial RapidIO network switching module, obtaining delay time according to the sending time and the receiving time of the RapidIO packet, and outputting a test result to the debugging serial port. The transmission path of the RapidIO packet in the tested serial RapidIO network switching module can be a self-loop transmission path configured by a switch driver, and can also be a point-to-point transmission path.
Transmission bandwidth test unit: after receiving the bandwidth test instruction, calling a RapidIO controller between a main test node FPGA and a slave test node FPGA according to a point-to-point transmission path configured by a switch driver to bidirectionally ping-pong send three RapidIO packets with different transaction types of NWRITE, SWRITE and NREAD, testing the transmission bandwidth between any two outgoing ports of a tested serial RapidIO network switching module, and outputting a test result to an FPGA debugging serial port. The bandwidth of the serial RapidIO network switching module under the condition of no load can be tested by modifying the type and the size of the RapidIO packet.
An error rate test unit: after receiving the switching transmission success rate test instruction, according to a point-to-point transmission path configured by a switch driver, the main test node FPGA calls a RapidIO controller to send NWRITE, SWRITE, NREAD, doorBell and Message RapidIO packets of different transaction types to the slave test node FPGA after sequentially passing through a tested serial RapidIO network switching module, after transmission is completed, the main test node FPGA drives an access register through the switch, so that the error state of an outgoing port connected with the slave test node FPGA is obtained, the success rate of forwarding the outgoing port RapidIO packets, the packet retransmission rate, the error rate and the like are calculated, and the result is output to a mode-adjusting serial port.
The port signal quality automatic optimization unit: after receiving the port optimization instruction, the main test node FPGA firstly adjusts parameters of a register of an outgoing port connected to the auxiliary test node FPGA, then calls an error rate test unit to test the error rate of the outgoing port, determines a parameter combination with the lowest error rate and the highest transmission rate through repeated adjustment and test processes, and outputs a test result to a debugging serial port.
The invention is illustrated below by a set of test procedures.
For example, a serial RapidIO network switch module composed of 5 switch chips of domestic NMS1800 is used as a test product, as shown in fig. 1, the switch chips are connected to form a full switch network through 2 paths of 4X outgoing ports, and each NMS1800 leads out 4 paths of 4X outgoing ports to 20 paths of outgoing ports, which are total, to access to a self-test platform.
In the test process, a self-test platform with 20 paths of 4X port pins is used for testing the tested serial RapidIO network switching module, and 20 paths of 4X outgoing ports of the serial RapidIO network switching module are sequentially connected with the 20 paths of 4X port pins of the self-test platform. Under the connection mode, the self-test platform mainly sets the following test points according to the use requirement of the serial RapidIO switching module:
1. port connection status testing
Connecting a port pin 1 on the self-testing platform with an SRIO port of a main testing node FPGA through a jumper joint, and connecting a port pin 20 with an SRIO port of a slave testing node FPGA; tx + and Rx + of each differential signal pin from the port pin 2 to the port pin 19 are in short circuit, and Tx-and Rx-are in short circuit, so that a self-loop is formed.
After the port leading ports are connected, a connection test instruction can be input into the FPGA through any debugging serial port of the FPGA, and the test unit checks link states of all 20 ports by reading registers of all switching chips on the serial RapidIO network switching module. If the link state of the corresponding Port is Port OK after passing through the self loop, the Port is proved to be normal.
RapidIO switching Module Transmission delay test
Any one FPGA is selected to be connected with any one of the 20 paths of 4X port pins of the test platform in the attached drawing, the FPGA is used as a main test node after connection, and the rest 19 paths of 4X port pins on the test platform are in short circuit through jumper wires to form a self-loop.
Firstly, after a configuration routing command is input into a debugging serial port of a main test node FPGA, a switch driver can automatically identify a test node port, and all commands are not different due to different ports. The switch driver will automatically search for the network topology and configure the self-looping test path.
The method comprises the steps that a transmission delay test command is input into a serial port of a main test node FPGA, a transmission delay test unit calls an RapidIO controller to send a RapidIO packet with a transaction type of Doorbell to a serial RapidIO network switching module to be tested, the sending time of the RapidIO packet is recorded, the RapidIO packet is returned to the main test node FPGA through a configured self-loop test path, the time of receiving the RapidIO packet is recorded, and the comprehensive routing delay time of the switching module is tested in the mode.
In addition, the main test node FPGA can be connected with any one of the 20 paths of 4X port pins, the auxiliary test node FPGA is connected with any one of the rest 19 paths of 4X port pins, and the rest 18 paths of 4X port pins on the test platform are in short circuit through jumper wires to form a self-loop.
Firstly, after a configuration routing command is input into a debugging serial port of a main test node FPGA, a switch driver can automatically identify a test node port, and all commands are not different due to different ports. The switch driver will automatically search for the network topology and configure point-to-point transmission paths between the two FPGA chips.
After the connection is successful, inputting a point-to-point transmission delay test instruction in a serial port of the main test node, and calling a RapidIO controller by a transmission delay test unit to send a RapidIO packet with a transaction type of DOORBELL to the slave test node; and after receiving the RapidIO packet from the slave test node, returning the RapidIO packet to the main test node FPGA in the original path, and after calculating the delay, displaying the result in the debugging serial port of the main test node FPGA by the main test node FPGA.
By the test mode, the test platform supports testing any two-point transmission delay.
End-to-end transmission bandwidth test of RapidIO switching module
The two FPGAs respectively select one port of the 20-path 4X port pins, one FPGA is selected as a main test node FPGA, after connection, a bandwidth test instruction is input through a main test node FPGA debugging serial port, and a transmission bandwidth test unit of the main test node firstly calls a switch driver to configure a point-to-point test path according to the pin ports where the two FPGAs are located. And then, a RapidIO controller is called to bidirectionally ping-pong send RapidIO packets with three different transaction types of NWRITE, SWRITE and NREAD between the main test node FPGA and the auxiliary test node FPGA, the transmission bandwidth between any two outgoing ports of the serial RapidIO network switching module is tested, and the test result is output to the FPGA debugging serial port.
The type and the size of the RapidIO packet can be modified through parameters carried by the bandwidth test instruction, and the bandwidth of the serial RapidIO network switching module under different load conditions can be tested.
Testing port transmission error rate of RapidIO switching module
And the two FPGAs respectively select one port pin of the 20 paths of 4X port pins, and one FPGA is selected as a main test node. After connection, a switching transmission success rate test instruction is input through a main test node FPGA debugging serial port, and the main test node FPGA calls a switch to drive a point-to-point test path configured according to pin ports where the two FPGAs are located. And the main test node FPGA calls the RapidIO controller again to send the RapidIO packets with the five different transaction types of NWRITE, SWRITE, NREAD, doorbell and Message to the slave test node FPGA after sequentially passing through the serial RapidIO network switching module. And after the RapidIO packet is transmitted, the main test node FPGA calls the switch again to drive and read the register of the serial RapidIO network switching module, so that error state statistics is carried out on the pin port where the slave test node FPGA is located, the RapidIO packet forwarding success rate, the packet retransmission rate, the error rate and the like of the pin port where the slave test node FPGA is located are calculated, and the result is output to the serial port.
Automatic optimization of RapidIO switch module signal quality
And aiming at outgoing ports with poor signal quality and high transmission error rate, which are found in the error rate test, selecting any one FPGA as a slave test node FPGA to be connected with the outgoing port with the high error rate, and optionally selecting one outgoing port with the normal error rate to be connected with another FPGA as a master test node. After the connection is successful, optimizing instructions at a debugging serial port input port of the main test node FPGA, adjusting parameters of a register of an outgoing port connected to the slave test node FPGA by the main test node FPGA, calling an error rate test unit to test the error rate of the outgoing port, determining a parameter combination with the lowest error rate and the highest transmission rate through repeated adjustment and test processes, and outputting a test result to the debugging serial port.
The self-testing platform shown in the embodiment solves the problem of product self-testing of serial RapidIO network switching module design manufacturers, greatly improves the product development period, improves the delivery success rate, and simultaneously provides an effective platform for RapidIO switching network system joint test and fault isolation.
According to the self-testing platform provided by the embodiment, other switching module self-testing platforms based on the RapidIO switch can be designed, the method is comprehensive in design and testing, is a perfect testing scheme for the serial RapidIO switching module, is independent of a hardware platform in application, is wide in application range, and has remarkable market prospect and economic benefit.
In summary, the present invention is only a preferred embodiment, and not intended to limit the scope of the invention, and all equivalent changes and modifications in the shape, structure, characteristics and spirit of the present invention described in the claims should be included in the scope of the present invention.
Claims (8)
1. A self-test platform for testing a serial RapidIO network switching module comprises a bottom plate hardware and a test software, and is characterized in that the bottom plate hardware comprises a plurality of paths of port pins, 2 FPGA chips and 2 debugging serial ports;
the port pins are used for leading each outgoing port on the serial RapidIO network switching module to the bottom plate, and the external self-loop-back mode is adopted to enable any two port pins to form a self-loop-back relation through a jumper wire according to the test requirement;
the debugging serial port is used for outputting a test request to the FPGA chip and receiving a test result fed back by the FPGA chip;
one SRIO interface led out from 2 FPGA chips is connected with any port pin in an external jumper wire mode according to test requirements so as to be connected with any outgoing port of the serial RapidIO network switching module, the same test software resides in the two FPGAs, and the test software comprises a driver of a switch, a RapidIO controller and a function test unit;
the switch driver is used for accessing a register of the serial RapidIO network switching module through the IIC interface to identify each outgoing port of the tested serial RapidIO network switching module and automatically searching a network topology structure, so that a self-loop transmission path of the same FPGA chip and a point-to-point transmission path between two FPGA chips are configured;
the RapidIO controller is used for realizing RapidIO communication and is provided with RapidIO packets for transmitting five transaction types of NWRITE, SWRITE, NREAD, doorbell and Message;
the function test unit designs corresponding test items according to different function requirements.
2. The self-test platform for testing the serial RapidIO network switching module of claim 1, wherein the function test unit comprises a port connection state test unit, and the function test unit calls a switch driver to access a register on the tested serial RapidIO network switching module after receiving a connection test instruction, so as to obtain link states of outgoing ports and evaluate an outgoing port of the RapidIO network switching module.
3. The self-test platform for testing the serial RapidIO network switching module as recited in claim 1, characterized in that the function test unit comprises a transmission delay test unit, after receiving the transmission delay test command, calls the RapidIO controller to send a RapidIO packet with a transaction type of DoorBell to the serial RapidIO network switching module to be tested, obtains delay time according to the sending time and the receiving time of the RapidIO packet, and outputs the test result to the debugging serial port.
4. The self-test platform for testing a serial RapidIO network switch module of claim 3, wherein the transmission delay test unit sends RapidIO packets using a self-loop transmission path or a point-to-point transmission path configured by a switch driver.
5. The self-test platform for testing the serial RapidIO network switching module as claimed in claim 1, characterized in that the function test unit comprises a transmission bandwidth test unit, after receiving a bandwidth test instruction, according to a point-to-point transmission path configured by a switch driver, a RapidIO controller is called between the master test node FPGA and the slave test node FPGA to send the RapidIO packets with three different transaction types of NWRITE, SWRITE and NREAD in a bidirectional ping-pong manner, the transmission bandwidth between any two outgoing ports of the serial RapidIO network switching module to be tested is tested, and a test result is output to the FPGA debugging serial port.
6. The self-test platform for testing the serial RapidIO network switch module of claim 1, wherein the functional test unit comprises a transmission bandwidth test unit for testing the bandwidth of the serial RapidIO network switch module without load by modifying the type and the packet size of a RapidIO packet.
7. The self-test platform for testing the serial RapidIO network switching module as claimed in claim 1, characterized in that the function test unit comprises a bit error rate test unit, after receiving the switching transmission success rate test instruction, according to the point-to-point transmission path configured by the switch driver, the master test node FPGA calls the RapidIO controller to send the RapidIO packets of five different transaction types including NWRITE, SWRITE, NREAD, doorbell and Message to the slave test node FPGA after sequentially passing through the tested serial RapidIO network switching module, after the transmission is completed, the master test node FPGA drives the access register through the switch, thereby obtaining the error state of the outgoing port connected with the slave test node FPGA, calculating the success rate, the packet retransmission rate and the bit error rate of the RapidIO packet forwarding to the outgoing port, and outputting the result to the tuning serial port.
8. The self-test platform for testing the serial RapidIO network switching module as claimed in claim 7, wherein the function test unit comprises a port signal quality automatic optimization unit, after receiving a port optimization instruction, the main test node FPGA adjusts parameters of a register of an outgoing port connected to the slave test node FPGA, then calls the error rate test unit to test the error rate of the outgoing port, determines a parameter combination with the lowest error rate and the highest transmission rate through repeated adjustment and test processes, and outputs the test result to the debugging serial port.
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| CN112019457B (en) * | 2020-08-31 | 2022-09-06 | 北京计算机技术及应用研究所 | High-speed switching device based on localization SRIO |
| CN112242922A (en) * | 2020-09-04 | 2021-01-19 | 苏州浪潮智能科技有限公司 | Method, device and equipment for constructing network topology and readable medium |
| CN113704163B (en) * | 2021-09-08 | 2024-04-19 | 天津津航计算技术研究所 | Testing device and method for verifying SRIO protocol integrity |
| CN113676380B (en) * | 2021-09-30 | 2023-02-28 | 西安易朴通讯技术有限公司 | Switch port testing method, electronic equipment and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5271000A (en) * | 1991-03-22 | 1993-12-14 | International Business Machines Corporation | Method and apparatus for testing and evaluation of distributed networks |
| CN104243174A (en) * | 2014-10-10 | 2014-12-24 | 沈辉 | Network and SRIO (serial rapid input/output) data exchanging plate based on VPX bus and control method for network and SRIO data exchanging plate |
| CN107920001A (en) * | 2017-12-07 | 2018-04-17 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The debugging apparatus of RapidIO communication middlewares |
| CN109218231A (en) * | 2018-09-21 | 2019-01-15 | 中国航空无线电电子研究所 | A kind of RapidIO exchange network |
| CN109388530A (en) * | 2018-08-22 | 2019-02-26 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Blade server-oriented automatic test platform and test method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070104219A1 (en) * | 2005-11-09 | 2007-05-10 | Honeywell International Inc. | System and method to facilitate testing of rapidio components |
-
2020
- 2020-04-24 CN CN202010330336.XA patent/CN111522700B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5271000A (en) * | 1991-03-22 | 1993-12-14 | International Business Machines Corporation | Method and apparatus for testing and evaluation of distributed networks |
| CN104243174A (en) * | 2014-10-10 | 2014-12-24 | 沈辉 | Network and SRIO (serial rapid input/output) data exchanging plate based on VPX bus and control method for network and SRIO data exchanging plate |
| CN107920001A (en) * | 2017-12-07 | 2018-04-17 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The debugging apparatus of RapidIO communication middlewares |
| CN109388530A (en) * | 2018-08-22 | 2019-02-26 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Blade server-oriented automatic test platform and test method |
| CN109218231A (en) * | 2018-09-21 | 2019-01-15 | 中国航空无线电电子研究所 | A kind of RapidIO exchange network |
Non-Patent Citations (3)
| Title |
|---|
| RapidIO传输性能测试分析研究;田泽等;《电脑知识与技术》;20101005(第28期);全文 * |
| 基于SRIO的FPGA间数据交互系统设计与应用;张德民等;《重庆邮电大学学报(自然科学版)》;20131215(第06期);全文 * |
| 基于VPX标准的RapidIO交换和Flash存储模块设计;李宾等;《声学技术》;20111215(第06期);全文 * |
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